4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
28 * audiots Audio Driver
30 * This Audio Driver controls the T2 audio core in the ALI M1553
31 * southbridge chip. This chip supports multiple play streams, but just
32 * a single record stream. It also supports wave table synthesis and
33 * hardware MIDI and joystick ports. Unfortunately the MIDI ports are
34 * not available because their pins have been re-assigned to expose
35 * interrupts. We also aren't going to do anything with the joystick
36 * ports. The audio core controls an AC-97 V2.1 Codec.
38 * The DMA engine uses a single buffer which is large enough to hold
39 * two interrupts worth of data. When it gets to the mid point an
40 * interrupt is generated and data is either sent (for record) or
41 * requested and put in that half of the buffer (for play). When the
42 * second half is played we do the same, but the audio core loops the
43 * pointer back to the beginning.
45 * The audio core has a bug in silicon that doesn't let it read the AC-97
46 * Codec's register. T2 has provided an algorithm that attempts to read the
47 * the Codec several times. This is probably heuristic and thus isn't
48 * absolutely guaranteed to work. However we do have to place a limit on
49 * the looping, otherwise when we read a valid 0x00 we would never exit
50 * the loop. Unfortunately there is also a problem with writing the AC-97
51 * Codec's registers as well. Thus we read it back to verify the write.
53 * The AC'97 common code provides shadow state for AC'97 registers for us,
54 * so we only need to read those registers during early startup (primarily
55 * to determine codec id and capabilities.)
57 * We don't save any of the audio controller registers during normal
58 * operation. When we need to save register state we only have to save
59 * the aram and eram. The rest of the controller state is never modified
60 * from the initial programming. Thus restoring the controller state
61 * can be done from audiots_chip_init() as well.
64 * WARNING: The SME birdsnest platform uses a PCI bridge chip between the
65 * CPU and the southbridge containing the audio core. There is
66 * a bug in silicon that causes a bogus parity error. With the mixer
67 * reimplementation project, Bug 4374774, the audio driver is always
68 * set to the best precision and number of channels. Thus when turning
69 * the mixer on and off the only thing that changes is the sample rate.
70 * This change in programming doesn't trigger the silicon error.
71 * Thus the supported channels must always be 2 and the precision
72 * must always be 16-bits. This will keep any future change in the
73 * mixer from exposing this bug.
75 * Due to a hardware bug, system power management is not supported by this
78 * CAUTION: If audio controller state is changed outside of aram
79 * and eram then that information must be saved and restored
80 * during power management shutdown and bringup.
82 * NOTE: The AC-97 Codec's reset pin is set to PCI reset, so we
83 * can't power down the Codec all the way.
85 * NOTE: This driver depends on the drv/audio and misc/ac97
86 * modules being loaded first.
88 * NOTE: Don't OR the ap_stop register to stop a play or record. This
89 * will just stop all active channels because a read of ap_stop
90 * returns ap_start. Just set the ap_stop register with the
91 * channels you want to stop. The same goes for ap_start.
93 * NOTE: There is a hardware problem with P2 rev motherboards. After
94 * prolonged use, reading the AC97 register will always return
95 * busy. The AC97 register is now useless. Consequently, we are no
96 * longer able to program the Codec. This work around disables
97 * audio when this state is detected. It's not great, but its
98 * better than having audio blasting out at 100% all the time.
100 * NOTE: Power Management testing has also exposed this AC97 timeout
101 * problem. Management has decided this is too risky for customers
102 * and hence they want power management support removed from the
103 * audio subsystem. All PM support is now removed.
107 * Synchronization notes:
109 * The audio framework guarantees that our entry points are exclusive
110 * with suspend and resume. This includes data flow and control entry
113 * The audio framework guarantees that only one control is being
114 * accessed on any given audio device at a time.
116 * The audio framework guarantees that entry points are themselves
117 * serialized for a given engine.
119 * We have no interrupt routine or other internal asynchronous routines.
121 * Our device uses completely separate registers for each engine,
122 * except for the start/stop registers, which are implemented in a
123 * manner that allows for them to be accessed concurrently safely from
126 * Hence, it turns out that we simply don't need any locking in this
130 #include <sys/modctl.h>
131 #include <sys/kmem.h>
134 #include <sys/sunddi.h>
135 #include <sys/debug.h>
136 #include <sys/note.h>
137 #include <sys/audio/audio_driver.h>
138 #include <sys/audio/ac97.h>
142 * Module linkage routines for the kernel
144 static int audiots_attach(dev_info_t
*, ddi_attach_cmd_t
);
145 static int audiots_detach(dev_info_t
*, ddi_detach_cmd_t
);
146 static int audiots_quiesce(dev_info_t
*);
149 * Entry point routine prototypes
151 static int audiots_open(void *, int, unsigned *, caddr_t
*);
152 static void audiots_close(void *);
153 static int audiots_start(void *);
154 static void audiots_stop(void *);
155 static int audiots_format(void *);
156 static int audiots_channels(void *);
157 static int audiots_rate(void *);
158 static void audiots_chinfo(void *, int, unsigned *, unsigned *);
159 static uint64_t audiots_count(void *);
160 static void audiots_sync(void *, unsigned);
162 static audio_engine_ops_t audiots_engine_ops
= {
163 AUDIO_ENGINE_VERSION
,
179 * Local Routine Prototypes
181 static void audiots_power_up(audiots_state_t
*);
182 static void audiots_chip_init(audiots_state_t
*);
183 static uint16_t audiots_get_ac97(void *, uint8_t);
184 static void audiots_set_ac97(void *, uint8_t, uint16_t);
185 static int audiots_init_state(audiots_state_t
*, dev_info_t
*);
186 static int audiots_map_regs(dev_info_t
*, audiots_state_t
*);
187 static uint16_t audiots_read_ac97(audiots_state_t
*, int);
188 static void audiots_stop_everything(audiots_state_t
*);
189 static void audiots_destroy(audiots_state_t
*);
190 static int audiots_alloc_port(audiots_state_t
*, int);
193 * Global variables, but viewable only by this file.
196 /* anchor for soft state structures */
197 static void *audiots_statep
;
203 /* Device operations structure */
204 static struct dev_ops audiots_dev_ops
= {
205 DEVO_REV
, /* devo_rev */
207 NULL
, /* devo_getinfo */
208 nulldev
, /* devo_identify - obsolete */
209 nulldev
, /* devo_probe */
210 audiots_attach
, /* devo_attach */
211 audiots_detach
, /* devo_detach */
212 nodev
, /* devo_reset */
213 NULL
, /* devo_cb_ops */
214 NULL
, /* devo_bus_ops */
215 NULL
, /* devo_power */
216 audiots_quiesce
, /* devo_quiesce */
219 /* Linkage structure for loadable drivers */
220 static struct modldrv audiots_modldrv
= {
221 &mod_driverops
, /* drv_modops */
222 TS_MOD_NAME
, /* drv_linkinfo */
223 &audiots_dev_ops
/* drv_dev_ops */
226 /* Module linkage structure */
227 static struct modlinkage audiots_modlinkage
= {
228 MODREV_1
, /* ml_rev */
229 (void *)&audiots_modldrv
, /* ml_linkage */
230 NULL
/* NULL terminates the list */
235 * NOTE: Grover OBP v4.0.166 and rev G of the ALI Southbridge chip force the
236 * audiots driver to use the upper 2 GB DMA address range. However to maintain
237 * backwards compatibility with older systems/OBP, we're going to try the full
240 * Eventually, this will be set back to using the proper high 2 GB DMA range.
243 /* Device attribute structure - full 4 gig address range */
244 static ddi_dma_attr_t audiots_attr
= {
245 DMA_ATTR_VERSION
, /* version */
246 0x0000000000000000LL
, /* dlim_addr_lo */
247 0x00000000ffffffffLL
, /* dlim_addr_hi */
248 0x0000000000003fffLL
, /* DMA counter register - 16 bits */
249 0x0000000000000008LL
, /* DMA address alignment, 64-bit */
250 0x0000007f, /* 1 through 64 byte burst sizes */
251 0x00000001, /* min effective DMA size */
252 0x0000000000003fffLL
, /* maximum transfer size, 16k */
253 0x000000000000ffffLL
, /* segment boundary, 64k */
254 0x00000001, /* s/g list length, no s/g */
255 0x00000001, /* granularity of device, don't care */
259 static ddi_device_acc_attr_t ts_acc_attr
= {
265 static ddi_device_acc_attr_t ts_regs_attr
= {
267 DDI_STRUCTURE_LE_ACC
,
275 * Driver initialization, called when driver is first loaded.
276 * This is how access is initially given to all the static structures.
282 * ddi_soft_state_init() status, see ddi_soft_state_init(9f), or
283 * mod_install() status, see mod_install(9f)
290 audio_init_ops(&audiots_dev_ops
, TS_NAME
);
292 /* initialize the soft state */
293 if ((error
= ddi_soft_state_init(&audiots_statep
,
294 sizeof (audiots_state_t
), 1)) != 0) {
295 audio_fini_ops(&audiots_dev_ops
);
299 if ((error
= mod_install(&audiots_modlinkage
)) != 0) {
300 audio_fini_ops(&audiots_dev_ops
);
301 ddi_soft_state_fini(&audiots_statep
);
311 * Module de-initialization, called when the driver is to be unloaded.
317 * mod_remove() status, see mod_remove(9f)
324 if ((error
= mod_remove(&audiots_modlinkage
)) != 0) {
328 /* free the soft state internal structures */
329 ddi_soft_state_fini(&audiots_statep
);
332 audio_fini_ops(&audiots_dev_ops
);
341 * Module information, returns infomation about the driver.
344 * modinfo *modinfop Pointer to the opaque modinfo structure
347 * mod_info() status, see mod_info(9f)
350 _info(struct modinfo
*modinfop
)
354 error
= mod_info(&audiots_modlinkage
, modinfop
);
364 * Attach an instance of the audiots driver. This routine does the
365 * device dependent attach tasks.
368 * dev_info_t *dip Pointer to the device's dev_info struct
369 * ddi_attach_cmd_t cmd Attach command
372 * DDI_SUCCESS The driver was initialized properly
373 * DDI_FAILURE The driver couldn't be initialized properly
376 audiots_attach(dev_info_t
*dip
, ddi_attach_cmd_t cmd
)
378 audiots_state_t
*state
;
381 instance
= ddi_get_instance(dip
);
388 /* we've already allocated the state structure so get ptr */
389 state
= ddi_get_soft_state(audiots_statep
, instance
);
390 ASSERT(dip
== state
->ts_dip
);
392 /* suspend/resume resets the chip, so we have no more faults */
393 if (state
->ts_flags
& TS_AUDIO_READ_FAILED
) {
394 ddi_dev_report_fault(state
->ts_dip
,
395 DDI_SERVICE_RESTORED
,
397 "check port, gain, balance, and mute settings");
398 /* and clear the fault state flags */
400 ~(TS_AUDIO_READ_FAILED
|TS_READ_FAILURE_PRINTED
);
403 audiots_power_up(state
);
404 audiots_chip_init(state
);
406 ac97_reset(state
->ts_ac97
);
408 audio_dev_resume(state
->ts_adev
);
410 return (DDI_SUCCESS
);
413 return (DDI_FAILURE
);
416 /* before we do anything make sure that we haven't had a h/w failure */
417 if (ddi_get_devstate(dip
) == DDI_DEVSTATE_DOWN
) {
418 cmn_err(CE_WARN
, "%s%d: The audio hardware has "
419 "been disabled.", ddi_driver_name(dip
), instance
);
420 cmn_err(CE_CONT
, "Please reboot to restore audio.");
421 return (DDI_FAILURE
);
424 /* allocate the state structure */
425 if (ddi_soft_state_zalloc(audiots_statep
, instance
) == DDI_FAILURE
) {
426 cmn_err(CE_WARN
, "!%s%d: soft state allocate failed",
427 ddi_driver_name(dip
), instance
);
428 return (DDI_FAILURE
);
432 * WARNING: From here on all errors require that we free memory,
433 * including the state structure.
436 /* get the state structure - cannot fail */
437 state
= ddi_get_soft_state(audiots_statep
, instance
);
438 ASSERT(state
!= NULL
);
440 if ((state
->ts_adev
= audio_dev_alloc(dip
, 0)) == NULL
) {
441 cmn_err(CE_WARN
, "unable to allocate audio dev");
445 /* map in the registers, allocate DMA buffers, etc. */
446 if (audiots_map_regs(dip
, state
) == DDI_FAILURE
) {
447 audio_dev_warn(state
->ts_adev
, "unable to map registers");
451 /* initialize the audio state structures */
452 if (audiots_init_state(state
, dip
) == DDI_FAILURE
) {
453 audio_dev_warn(state
->ts_adev
, "init state structure failed");
458 audiots_power_up(state
);
460 /* initialize the audio controller */
461 audiots_chip_init(state
);
463 /* initialize the AC-97 Codec */
464 if (ac97_init(state
->ts_ac97
, state
->ts_adev
) != 0) {
468 /* put the engine interrupts into a known state -- all off */
469 ddi_put32(state
->ts_acch
, &state
->ts_regs
->aud_regs
.ap_ainten
,
472 /* call the framework attach routine */
473 if (audio_dev_register(state
->ts_adev
) != DDI_SUCCESS
) {
474 audio_dev_warn(state
->ts_adev
, "unable to register audio");
478 /* everything worked out, so report the device */
481 return (DDI_SUCCESS
);
484 audiots_destroy(state
);
485 return (DDI_FAILURE
);
492 * Detach an instance of the audiots driver.
495 * dev_info_t *dip Pointer to the device's dev_info struct
496 * ddi_detach_cmd_t cmd Detach command
499 * DDI_SUCCESS The driver was detached
500 * DDI_FAILURE The driver couldn't be detached
503 audiots_detach(dev_info_t
*dip
, ddi_detach_cmd_t cmd
)
505 audiots_state_t
*state
;
508 instance
= ddi_get_instance(dip
);
510 /* get the state structure */
511 if ((state
= ddi_get_soft_state(audiots_statep
, instance
)) == NULL
) {
512 cmn_err(CE_WARN
, "!%s%d: detach get soft state failed",
513 ddi_driver_name(dip
), instance
);
514 return (DDI_FAILURE
);
522 audio_dev_suspend(state
->ts_adev
);
524 /* stop playing and recording */
525 (void) audiots_stop_everything(state
);
527 return (DDI_SUCCESS
);
530 return (DDI_FAILURE
);
533 /* attempt to unregister from the framework first */
534 if (audio_dev_unregister(state
->ts_adev
) != DDI_SUCCESS
) {
535 return (DDI_FAILURE
);
538 audiots_destroy(state
);
540 return (DDI_SUCCESS
);
548 * Quiesce an instance of the audiots driver. Stops all DMA and
552 * dev_info_t *dip Pointer to the device's dev_info struct
555 * DDI_SUCCESS The driver was quiesced
556 * DDI_SUCCESS The driver was NOT quiesced
559 audiots_quiesce(dev_info_t
*dip
)
561 audiots_state_t
*state
;
564 instance
= ddi_get_instance(dip
);
566 /* get the state structure */
567 if ((state
= ddi_get_soft_state(audiots_statep
, instance
)) == NULL
) {
568 return (DDI_FAILURE
);
571 audiots_stop_everything(state
);
573 return (DDI_SUCCESS
);
580 * Ensure that the device is running in PCI power state D0.
583 audiots_power_up(audiots_state_t
*state
)
585 ddi_acc_handle_t pcih
= state
->ts_pcih
;
589 if ((pci_config_get16(pcih
, PCI_CONF_STAT
) & PCI_STAT_CAP
) == 0) {
590 /* does not implement PCI capabilities -- no PM */
594 ptr
= pci_config_get8(pcih
, PCI_CONF_CAP_PTR
);
596 if (ptr
== PCI_CAP_NEXT_PTR_NULL
) {
597 /* PM capability not found */
600 if (pci_config_get8(pcih
, ptr
+ PCI_CAP_ID
) == PCI_CAP_ID_PM
) {
604 ptr
= pci_config_get8(pcih
, ptr
+ PCI_CAP_NEXT_PTR
);
607 /* if we got here, then got valid PMCSR pointer */
610 /* check to see if we are already in state D0 */
611 pmcsr
= pci_config_get16(pcih
, ptr
);
612 if ((pmcsr
& PCI_PMCSR_STATE_MASK
) != PCI_PMCSR_D0
) {
614 /* D3hot (or any other state) -> D0 */
615 pmcsr
&= ~PCI_PMCSR_STATE_MASK
;
616 pmcsr
|= PCI_PMCSR_D0
;
617 pci_config_put16(pcih
, ptr
, pmcsr
);
621 * Wait for it to power up - PCI spec says 10 ms is enough.
622 * We double it. Note that no locks are held when this routine
623 * is called, so we can sleep (we are in attach context only).
625 * We do this delay even if already powerd up, just to make
626 * sure we aren't seeing something that *just* transitioned
629 delay(drv_usectohz(TS_20MS
));
631 /* clear PME# flag */
632 pmcsr
= pci_config_get16(pcih
, ptr
);
633 pci_config_put16(pcih
, ptr
, pmcsr
| PCI_PMCSR_PME_STAT
);
637 * audiots_chip_init()
640 * Initialize the audio core.
643 * audiots_state_t *state The device's state structure
646 audiots_chip_init(audiots_state_t
*state
)
648 ddi_acc_handle_t handle
= state
->ts_acch
;
649 audiots_regs_t
*regs
= state
->ts_regs
;
652 /* start with all interrupts & dma channels disabled */
653 ddi_put32(handle
, ®s
->aud_regs
.ap_stop
, TS_ALL_DMA_ENGINES
);
654 ddi_put32(handle
, ®s
->aud_regs
.ap_ainten
, TS_ALL_DMA_OFF
);
656 /* set global music and wave volume to 0dB */
657 ddi_put32(handle
, ®s
->aud_regs
.ap_volume
, 0x0);
659 /* enable end interrupts for all channels. */
660 ddi_put32(handle
, ®s
->aud_regs
.ap_cir_gc
, AP_CIR_GC_ENDLP_IE
);
662 /* for each stream, set gain and vol settings */
663 for (str
= 0; str
< TS_MAX_HW_CHANNELS
; str
++) {
665 * Set volume to all off, 1st left and then right.
666 * These are never changed, so we don't have to save them.
669 ®s
->aud_ram
[str
].eram
.eram_gvsel_pan_vol
,
670 (ERAM_WAVE_VOL
|ERAM_PAN_LEFT
|ERAM_PAN_0dB
|
671 ERAM_VOL_MAX_ATTEN
));
673 ®s
->aud_ram
[str
].eram
.eram_gvsel_pan_vol
,
674 (ERAM_WAVE_VOL
|ERAM_PAN_RIGHT
|ERAM_PAN_0dB
|
675 ERAM_VOL_MAX_ATTEN
));
678 * The envelope engine *MUST* remain in still mode (off).
679 * Otherwise bad things like gain randomly disappearing might
680 * happen. See bug #4332773.
683 ddi_put32(handle
, ®s
->aud_ram
[str
].eram
.eram_ebuf1
,
685 ddi_put32(handle
, ®s
->aud_ram
[str
].eram
.eram_ebuf2
,
688 /* program the initial eram and aram rate */
689 ddi_put16(handle
, ®s
->aud_ram
[str
].aram
.aram_delta
,
691 ddi_put16(handle
, ®s
->aud_ram
[str
].eram
.eram_ctrl_ec
,
692 ERAM_16_BITS
| ERAM_STEREO
| ERAM_LOOP_MODE
|
696 /* program channel 31 for record */
697 OR_SET_WORD(handle
, &state
->ts_regs
->aud_regs
.ap_global_control
,
698 (AP_CLOGAL_CTRL_E_PCMIN_CH31
|AP_CLOGAL_CTRL_PCM_OUT_AC97
|
699 AP_CLOGAL_CTRL_MMC_FROM_MIXER
|AP_CLOGAL_CTRL_PCM_OUT_TO_AC97
));
701 /* do a warm reset, which powers up the Codec */
702 OR_SET_WORD(handle
, &state
->ts_regs
->aud_regs
.ap_sctrl
,
703 AP_SCTRL_WRST_CODEC
);
705 AND_SET_WORD(handle
, &state
->ts_regs
->aud_regs
.ap_sctrl
,
706 ~AP_SCTRL_WRST_CODEC
);
708 /* do a warm reset via the Codec, yes, I'm being paranoid! */
709 audiots_set_ac97(state
, AC97_RESET_REGISTER
, 0);
711 /* Make sure the Codec is powered up. */
713 while ((audiots_get_ac97(state
, AC97_POWERDOWN_CTRL_STAT_REGISTER
) &
714 PCSR_POWERD_UP
) != PCSR_POWERD_UP
&& i
--) {
724 * Get the value in the specified AC-97 Codec register. There is a
725 * bug in silicon which forces us to do multiple reads of the Codec's
726 * register. This algorithm was provided by T2 and is heuristic in
727 * nature. Unfortunately we have no guarantees that the real answer
728 * isn't 0x0000, which is what we get when a read fails. So we loop
729 * TS_LOOP_CNT times before we give up. We just have to hope this is
730 * sufficient to give us the correct value.
733 * audiots_state_t *state The device's state structure
734 * int reg AC-97 register number
737 * unsigned short The value in the specified register
740 audiots_get_ac97(void *arg
, uint8_t reg
)
742 audiots_state_t
*state
= arg
;
743 ddi_acc_handle_t handle
= state
->ts_acch
;
750 if (state
->ts_revid
== AC_REV_ID1
) {
751 data
= &state
->ts_regs
->aud_regs
.ap_acrd_35D_data
;
753 data
= &state
->ts_regs
->aud_regs
.ap_acrdwr_data
;
756 /* make sure the register is good */
757 reg
&= AP_ACRD_INDEX_MASK
;
758 for (count
= TS_LOOP_CNT
; count
--; ) {
759 if ((first
= audiots_read_ac97(state
, reg
)) != 0) {
764 delay
= TS_DELAY_CNT
;
766 (void) ddi_get16(handle
, data
);
769 if ((next
= audiots_read_ac97(state
, reg
)) != 0) {
775 * Arggg, if you let the next read happen too soon then it fails.
776 * 12 usec fails, 13 usec succeeds. So set it to 20 for safety.
778 drv_usecwait(TS_20US
);
785 * audiots_init_state()
788 * This routine initializes the audio driver's state structure.
789 * This includes reading the properties.
791 * CAUTION: This routine cannot allocate resources, unless it frees
792 * them before returning for an error. Also, error_destroy:
793 * in audiots_attach() would need to be fixed as well.
795 * NOTE: birdsnest supports CD ROM input. We check for the cdrom
796 * property. If there we turn it on.
799 * audiots_state_t *state The device's state structure
800 * dev_info_t *dip Pointer to the device's dev_info struct
803 * DDI_SUCCESS State structure initialized
804 * DDI_FAILURE State structure not initialized
807 audiots_init_state(audiots_state_t
*state
, dev_info_t
*dip
)
809 state
->ts_ac97
= ac97_alloc(dip
, audiots_get_ac97
,
810 audiots_set_ac97
, state
);
812 if (state
->ts_ac97
== NULL
) {
813 return (DDI_FAILURE
);
816 /* save the device info pointer */
819 for (int i
= 0; i
< TS_NUM_PORTS
; i
++) {
820 if (audiots_alloc_port(state
, i
) != DDI_SUCCESS
) {
821 return (DDI_FAILURE
);
825 return (DDI_SUCCESS
);
833 * This routine maps the registers in.
835 * Once the config space registers are mapped in we determine if the
836 * audio core may be power managed. It should, but if it doesn't,
837 * then trying to may cause the core to hang.
839 * CAUTION: Make sure all errors call audio_dev_warn().
842 * dev_info_t *dip Pointer to the device's devinfo
843 * audiots_state_t *state The device's state structure
845 * DDI_SUCCESS Registers successfully mapped
846 * DDI_FAILURE Registers not successfully mapped
849 audiots_map_regs(dev_info_t
*dip
, audiots_state_t
*state
)
854 /* map in the registers, the config and memory mapped registers */
855 if (pci_config_setup(dip
, &state
->ts_pcih
) != DDI_SUCCESS
) {
856 audio_dev_warn(state
->ts_adev
,
857 "unable to map PCI configuration space");
858 return (DDI_FAILURE
);
861 /* Read the Audio Controller's vendor, device, and revision IDs */
863 (pci_config_get16(state
->ts_pcih
, PCI_CONF_VENID
) << 16) |
864 pci_config_get16(state
->ts_pcih
, PCI_CONF_DEVID
);
865 state
->ts_revid
= pci_config_get8(state
->ts_pcih
, PCI_CONF_REVID
);
867 if (ddi_regs_map_setup(dip
, TS_MEM_MAPPED_REGS
,
868 (caddr_t
*)&state
->ts_regs
, 0, 0, &ts_regs_attr
, &state
->ts_acch
) !=
870 audio_dev_warn(state
->ts_adev
,
871 "unable to map PCI device registers");
872 return (DDI_FAILURE
);
875 switch (state
->ts_devid
) {
883 (void) snprintf(rev
, sizeof (rev
), "Rev %x", state
->ts_revid
);
884 audio_dev_set_description(state
->ts_adev
, name
);
885 audio_dev_set_version(state
->ts_adev
, rev
);
887 return (DDI_SUCCESS
);
891 * audiots_alloc_port()
894 * This routine allocates the DMA handles and the memory for the
895 * DMA engines to use. It then binds each of the buffers to its
896 * respective handle, getting a DMA cookie.
898 * NOTE: All of the ddi_dma_... routines sleep if they cannot get
899 * memory. This means these calls should always succeed.
901 * NOTE: ddi_dma_alloc_handle() attempts to use the full 4 GB DMA address
902 * range. This is to work around Southbridge rev E/G OBP issues.
903 * (See Grover OBP note above)
905 * CAUTION: Make sure all errors call audio_dev_warn().
908 * audiots_port_t *state The port structure for a device stream
909 * int num The port number
912 * DDI_SUCCESS DMA resources mapped
913 * DDI_FAILURE DMA resources not successfully mapped
916 audiots_alloc_port(audiots_state_t
*state
, int num
)
918 audiots_port_t
*port
;
919 dev_info_t
*dip
= state
->ts_dip
;
920 audio_dev_t
*adev
= state
->ts_adev
;
923 ddi_dma_cookie_t cookie
;
926 ddi_acc_handle_t regsh
= state
->ts_acch
;
927 uint32_t *gcptr
= &state
->ts_regs
->aud_regs
.ap_cir_gc
;
929 port
= kmem_zalloc(sizeof (*port
), KM_SLEEP
);
930 state
->ts_ports
[num
] = port
;
932 port
->tp_state
= state
;
933 port
->tp_rate
= TS_RATE
;
935 if (num
== TS_INPUT_PORT
) {
937 caps
= ENGINE_INPUT_CAP
;
938 port
->tp_dma_stream
= 31;
939 port
->tp_sync_dir
= DDI_DMA_SYNC_FORKERNEL
;
942 caps
= ENGINE_OUTPUT_CAP
;
943 port
->tp_dma_stream
= 0;
944 port
->tp_sync_dir
= DDI_DMA_SYNC_FORDEV
;
947 port
->tp_dma_mask
= (1U << port
->tp_dma_stream
);
948 port
->tp_nframes
= 4096;
949 port
->tp_size
= port
->tp_nframes
* TS_FRAMESZ
;
951 /* allocate dma handle */
952 rc
= ddi_dma_alloc_handle(dip
, &audiots_attr
, DDI_DMA_SLEEP
,
953 NULL
, &port
->tp_dmah
);
954 if (rc
!= DDI_SUCCESS
) {
955 audio_dev_warn(adev
, "ddi_dma_alloc_handle failed: %d", rc
);
956 return (DDI_FAILURE
);
958 /* allocate DMA buffer */
959 rc
= ddi_dma_mem_alloc(port
->tp_dmah
, port
->tp_size
, &ts_acc_attr
,
960 DDI_DMA_CONSISTENT
, DDI_DMA_SLEEP
, NULL
, &port
->tp_kaddr
,
961 &port
->tp_size
, &port
->tp_acch
);
962 if (rc
== DDI_FAILURE
) {
963 audio_dev_warn(adev
, "dma_mem_alloc failed");
964 return (DDI_FAILURE
);
967 /* bind DMA buffer */
968 rc
= ddi_dma_addr_bind_handle(port
->tp_dmah
, NULL
,
969 port
->tp_kaddr
, port
->tp_size
, dir
|DDI_DMA_CONSISTENT
,
970 DDI_DMA_SLEEP
, NULL
, &cookie
, &count
);
971 if (rc
!= DDI_DMA_MAPPED
) {
973 "ddi_dma_addr_bind_handle failed: %d", rc
);
974 return (DDI_FAILURE
);
978 port
->tp_paddr
= cookie
.dmac_address
;
979 if ((unsigned)port
->tp_paddr
& 0x80000000U
) {
980 ddi_put32(regsh
, gcptr
,
981 ddi_get32(regsh
, gcptr
) | AP_CIR_GC_SYS_MEM_4G_ENABLE
);
983 ddi_put32(regsh
, gcptr
,
984 ddi_get32(regsh
, gcptr
) & ~(AP_CIR_GC_SYS_MEM_4G_ENABLE
));
986 port
->tp_engine
= audio_engine_alloc(&audiots_engine_ops
, caps
);
987 if (port
->tp_engine
== NULL
) {
988 audio_dev_warn(adev
, "audio_engine_alloc failed");
989 return (DDI_FAILURE
);
992 audio_engine_set_private(port
->tp_engine
, port
);
993 audio_dev_add_engine(adev
, port
->tp_engine
);
995 return (DDI_SUCCESS
);
999 * audiots_read_ac97()
1002 * This routine actually reads the AC-97 Codec's register. It may
1003 * be called several times to succeed.
1006 * Revision M1535D B1-C of the ALI SouthBridge includes a workaround for
1007 * the broken busy flag. Resetting the busy flag requires a software tweak
1008 * to go with the worked around hardware. When we detect failure, we make
1009 * 10 attempts to reset the chip before we fail. This should reset the new
1010 * SB systems. On all SB systems, this will increse the read delay
1011 * slightly, but shouldn't bother it otherwise.
1014 * audiots_state_t *state The device's state structure
1015 * int reg AC-97 register number
1018 * unsigned short The value in the specified register
1021 audiots_read_ac97(audiots_state_t
*state
, int reg
)
1023 ddi_acc_handle_t acch
= state
->ts_acch
;
1026 uint32_t *stimer
= &state
->ts_regs
->aud_regs
.ap_stimer
;
1032 if (state
->ts_revid
== AC_REV_ID1
) {
1033 addr
= &state
->ts_regs
->aud_regs
.ap_acrd_35D_reg
;
1034 data
= &state
->ts_regs
->aud_regs
.ap_acrd_35D_data
;
1036 addr
= &state
->ts_regs
->aud_regs
.ap_acrdwr_reg
;
1037 data
= &state
->ts_regs
->aud_regs
.ap_acrdwr_data
;
1041 /* wait for ready to send read request */
1042 for (i
= 0; i
< TS_READ_TRIES
; i
++) {
1043 if (!(ddi_get16(acch
, addr
) & AP_ACRD_R_READ_BUSY
)) {
1046 /* don't beat on the bus */
1049 if (i
>= TS_READ_TRIES
) {
1050 if (resets
< TS_RESET_TRIES
) {
1051 /* Attempt to reset */
1052 drv_usecwait(TS_20US
);
1053 ddi_put16(acch
, addr
, TS_SB_RESET
);
1057 state
->ts_flags
|= TS_AUDIO_READ_FAILED
;
1058 if (!(state
->ts_flags
& TS_READ_FAILURE_PRINTED
)) {
1059 ddi_dev_report_fault(state
->ts_dip
,
1060 DDI_SERVICE_LOST
, DDI_DEVICE_FAULT
,
1061 "Unable to communicate with AC97 CODEC");
1062 audio_dev_warn(state
->ts_adev
,
1063 "The audio AC97 register has timed out.");
1064 audio_dev_warn(state
->ts_adev
,
1065 "Audio is now disabled.");
1066 audio_dev_warn(state
->ts_adev
,
1067 "Please reboot to restore audio.");
1069 /* Don't flood the console */
1070 state
->ts_flags
|= TS_READ_FAILURE_PRINTED
;
1076 /* program the register to read */
1077 ddi_put16(acch
, addr
, (reg
|AP_ACRD_W_PRIMARY_CODEC
|
1078 AP_ACRD_W_READ_MIXER_REG
|AP_ACRD_W_AUDIO_READ_REQ
&
1079 (~AP_ACWR_W_SELECT_WRITE
)));
1081 /* hardware bug work around */
1082 chk1
= ddi_get32(acch
, stimer
);
1083 chk2
= ddi_get32(acch
, stimer
);
1085 while (chk1
== chk2
&& i
) {
1086 chk2
= ddi_get32(acch
, stimer
);
1089 OR_SET_SHORT(acch
, addr
, AP_ACRD_W_READ_MIXER_REG
);
1093 /* wait again for read to send read request */
1094 for (i
= 0; i
< TS_READ_TRIES
; i
++) {
1095 if (!(ddi_get16(acch
, addr
) & AP_ACRD_R_READ_BUSY
)) {
1098 /* don't beat on the bus */
1101 if (i
>= TS_READ_TRIES
) {
1102 if (resets
< TS_RESET_TRIES
) {
1103 /* Attempt to reset */
1104 drv_usecwait(TS_20US
);
1105 ddi_put16(acch
, addr
, TS_SB_RESET
);
1109 state
->ts_flags
|= TS_AUDIO_READ_FAILED
;
1110 if (!(state
->ts_flags
& TS_READ_FAILURE_PRINTED
)) {
1111 ddi_dev_report_fault(state
->ts_dip
,
1112 DDI_SERVICE_LOST
, DDI_DEVICE_FAULT
,
1113 "Unable to communicate with AC97 CODEC");
1114 audio_dev_warn(state
->ts_adev
,
1115 "The audio AC97 register has timed out.");
1116 audio_dev_warn(state
->ts_adev
,
1117 "Audio is now disabled.");
1118 audio_dev_warn(state
->ts_adev
,
1119 "Please reboot to restore audio.");
1121 /* Don't flood the console */
1122 state
->ts_flags
|= TS_READ_FAILURE_PRINTED
;
1128 return (ddi_get16(acch
, data
));
1130 } /* audiots_read_ac97() */
1133 * audiots_set_ac97()
1136 * Set the value in the specified AC-97 Codec register. Just like
1137 * reading the AC-97 Codec, it is possible there is a problem writing
1138 * it as well. So we loop.
1141 * audiots_state_t *state The device's state structure
1142 * int reg AC-97 register number
1143 * uint16_t value The value to write
1146 audiots_set_ac97(void *arg
, uint8_t reg8
, uint16_t data
)
1148 audiots_state_t
*state
= arg
;
1149 ddi_acc_handle_t handle
= state
->ts_acch
;
1150 uint16_t *data_addr
= &state
->ts_regs
->aud_regs
.ap_acrdwr_data
;
1151 uint16_t *reg_addr
= &state
->ts_regs
->aud_regs
.ap_acrdwr_reg
;
1155 uint16_t reg
= reg8
;
1157 reg
&= AP_ACWR_INDEX_MASK
;
1159 /* Don't touch the reserved bits on the pre 35D+ SouthBridge */
1160 if (state
->ts_revid
== AC_REV_ID1
) {
1161 reg
|= AP_ACWR_W_PRIMARY_CODEC
|AP_ACWR_W_WRITE_MIXER_REG
;
1163 reg
|= AP_ACWR_W_PRIMARY_CODEC
|AP_ACWR_W_WRITE_MIXER_REG
|
1164 AP_ACWR_W_SELECT_WRITE
;
1167 for (count
= TS_LOOP_CNT
; count
--; ) {
1168 /* wait for ready to write */
1169 for (i
= 0; i
< TS_WAIT_CNT
; i
++) {
1170 if (!(ddi_get16(handle
, reg_addr
) &
1171 AP_ACWR_R_WRITE_BUSY
)) {
1172 /* ready to write */
1173 ddi_put16(handle
, reg_addr
, reg
);
1175 /* Write the data */
1176 ddi_put16(handle
, data_addr
, data
);
1180 if (i
>= TS_WAIT_CNT
) {
1185 /* wait for write to complete */
1186 for (i
= 0; i
< TS_WAIT_CNT
; i
++) {
1187 if (!(ddi_get16(handle
, reg_addr
) &
1188 AP_ACWR_R_WRITE_BUSY
)) {
1194 /* verify the value written */
1195 tmp_short
= audiots_get_ac97(state
, reg8
);
1196 if (data
== tmp_short
) {
1197 /* successfully loaded, so we can return */
1202 } /* audiots_set_ac97() */
1208 * Opens a DMA engine for use. Will also ensure the device is powered
1209 * up if not already done so.
1212 * void *arg The DMA engine to set up
1213 * int flag Open flags
1214 * unsigned *nframesp Receives number of frames
1215 * caddr_t *bufp Receives kernel data buffer
1222 audiots_open(void *arg
, int flag
, unsigned *nframesp
, caddr_t
*bufp
)
1224 audiots_port_t
*port
= arg
;
1226 _NOTE(ARGUNUSED(flag
));
1230 *nframesp
= port
->tp_nframes
;
1231 *bufp
= port
->tp_kaddr
;
1240 * Closes an audio DMA engine that was previously opened. Since
1241 * nobody is using it, we could take this opportunity to possibly power
1242 * down the entire device, or at least the DMA engine.
1245 * void *arg The DMA engine to shut down
1248 audiots_close(void *arg
)
1250 _NOTE(ARGUNUSED(arg
));
1257 * This is called by the framework to stop a port that is
1258 * transferring data.
1261 * void *arg The DMA engine to stop
1264 audiots_stop(void *arg
)
1266 audiots_port_t
*port
= arg
;
1267 audiots_state_t
*state
= port
->tp_state
;
1269 ddi_put32(state
->ts_acch
, &state
->ts_regs
->aud_regs
.ap_stop
,
1277 * This is called by the framework to start a port transferring data.
1280 * void *arg The DMA engine to start
1283 * 0 on success (never fails, errno if it did)
1286 audiots_start(void *arg
)
1288 audiots_port_t
*port
= arg
;
1289 audiots_state_t
*state
= port
->tp_state
;
1290 ddi_acc_handle_t handle
= state
->ts_acch
;
1291 audiots_regs_t
*regs
= state
->ts_regs
;
1292 audiots_aram_t
*aram
;
1293 audiots_eram_t
*eram
;
1299 aram
= ®s
->aud_ram
[port
->tp_dma_stream
].aram
;
1300 eram
= ®s
->aud_ram
[port
->tp_dma_stream
].eram
;
1304 gvsel
= ERAM_WAVE_VOL
| ERAM_PAN_0dB
| ERAM_VOL_DEFAULT
;
1305 ctrl
= ERAM_16_BITS
| ERAM_STEREO
| ERAM_LOOP_MODE
| ERAM_SIGNED_PCM
;
1307 delta
= (port
->tp_rate
<< TS_SRC_SHIFT
) / TS_RATE
;
1309 if (port
->tp_num
== TS_INPUT_PORT
) {
1310 delta
= (TS_RATE
<< TS_SRC_SHIFT
) / port
->tp_rate
;
1312 eso
= port
->tp_nframes
- 1;
1314 /* program the sample rate */
1315 ddi_put16(handle
, &aram
->aram_delta
, (uint16_t)delta
);
1317 /* program the precision, number of channels and loop mode */
1318 ddi_put16(handle
, &eram
->eram_ctrl_ec
, ctrl
);
1320 /* program the volume settings */
1321 ddi_put16(handle
, &eram
->eram_gvsel_pan_vol
, gvsel
);
1323 /* set ALPHA and FMS to 0 */
1324 ddi_put16(handle
, &aram
->aram_alpha_fms
, 0x0);
1327 ddi_put16(handle
, &aram
->aram_cso
, 0x0);
1330 ddi_put32(handle
, &aram
->aram_cptr_lba
,
1331 port
->tp_paddr
& ARAM_LBA_MASK
);
1334 ddi_put16(handle
, &aram
->aram_eso
, eso
);
1336 /* stop the DMA engines */
1337 ddi_put32(handle
, ®s
->aud_regs
.ap_stop
, port
->tp_dma_mask
);
1339 /* now make sure it starts playing */
1340 ddi_put32(handle
, ®s
->aud_regs
.ap_start
, port
->tp_dma_mask
);
1349 * This is called by the framework to query the channel offsets
1353 * void *arg The DMA engine to query
1354 * int chan Channel number.
1355 * unsigned *offset Starting offset of channel.
1356 * unsigned *incr Increment (in samples) between frames.
1359 * 0 indicating rate array is range instead of enumeration
1363 audiots_chinfo(void *arg
, int chan
, unsigned *offset
, unsigned *incr
)
1365 _NOTE(ARGUNUSED(arg
));
1374 * Called by the framework to query the format for the device.
1377 * void *arg The DMA engine to query
1380 * AUDIO_FORMAT_S16_LE.
1383 audiots_format(void *arg
)
1385 _NOTE(ARGUNUSED(arg
));
1387 return (AUDIO_FORMAT_S16_LE
);
1392 * audiots_channels()
1395 * Called by the framework to query the channnels for the device.
1398 * void *arg The DMA engine to query
1404 audiots_channels(void *arg
)
1406 _NOTE(ARGUNUSED(arg
));
1415 * Called by the framework to query the sample rates for the device.
1418 * void *arg The DMA engine to query
1421 * Sample rate in HZ (always 48000).
1424 audiots_rate(void *arg
)
1426 audiots_port_t
*port
= arg
;
1428 return (port
->tp_rate
);
1435 * This is called by the framework to get the engine's frame counter
1438 * void *arg The DMA engine to query
1441 * frame count for current engine
1444 audiots_count(void *arg
)
1446 audiots_port_t
*port
= arg
;
1447 audiots_state_t
*state
= port
->tp_state
;
1452 cso
= ddi_get16(state
->ts_acch
,
1453 &state
->ts_regs
->aud_ram
[port
->tp_dma_stream
].aram
.aram_cso
);
1455 n
= (cso
>= port
->tp_cso
) ?
1456 cso
- port
->tp_cso
:
1457 cso
+ port
->tp_nframes
- port
->tp_cso
;
1460 port
->tp_count
+= n
;
1461 val
= port
->tp_count
;
1470 * This is called by the framework to synchronize DMA caches.
1473 * void *arg The DMA engine to sync
1476 audiots_sync(void *arg
, unsigned nframes
)
1478 audiots_port_t
*port
= arg
;
1479 _NOTE(ARGUNUSED(nframes
));
1481 (void) ddi_dma_sync(port
->tp_dmah
, 0, 0, port
->tp_sync_dir
);
1485 * audiots_stop_everything()
1488 * This routine disables the address engine interrupt for all 32 DMA
1489 * engines. Just to be sure, it then explicitly issues a stop command to
1490 * the address engine and envelope engines for all 32 channels.
1494 * There is a hardware bug that generates a spurious interrupt
1495 * when the DMA engines are stopped. It's not consistent - it
1496 * happens every 1 out of 6 stops or so. It will show up as a
1497 * record interrupt. The problem is that once the driver is
1498 * detached or if the system goes into low power mode, nobody
1499 * will service that interrupt. The system will eventually become
1503 * audiots_state_t *state The device's state structure
1506 audiots_stop_everything(audiots_state_t
*state
)
1508 if (state
->ts_acch
== NULL
)
1511 ddi_put32(state
->ts_acch
, &state
->ts_regs
->aud_regs
.ap_ainten
,
1514 ddi_put32(state
->ts_acch
, &state
->ts_regs
->aud_regs
.ap_stop
,
1515 TS_ALL_DMA_ENGINES
);
1517 ddi_put32(state
->ts_acch
, &state
->ts_regs
->aud_regs
.ap_aint
,
1518 TS_ALL_DMA_ENGINES
);
1522 * audiots_free_port()
1525 * This routine unbinds the DMA cookies, frees the DMA buffers,
1526 * deallocates the DMA handles.
1529 * audiots_port_t *port The port structure for a device stream.
1532 audiots_free_port(audiots_port_t
*port
)
1537 if (port
->tp_engine
) {
1538 audio_dev_remove_engine(port
->tp_state
->ts_adev
,
1540 audio_engine_free(port
->tp_engine
);
1542 if (port
->tp_paddr
) {
1543 (void) ddi_dma_unbind_handle(port
->tp_dmah
);
1545 if (port
->tp_acch
) {
1546 ddi_dma_mem_free(&port
->tp_acch
);
1548 if (port
->tp_dmah
) {
1549 ddi_dma_free_handle(&port
->tp_dmah
);
1551 kmem_free(port
, sizeof (*port
));
1558 * This routine releases all resources held by the device instance,
1559 * as part of either detach or a failure in attach.
1562 * audiots_state_t *state The device soft state.
1565 audiots_destroy(audiots_state_t
*state
)
1567 audiots_stop_everything(state
);
1569 for (int i
= 0; i
< TS_NUM_PORTS
; i
++)
1570 audiots_free_port(state
->ts_ports
[i
]);
1573 ddi_regs_map_free(&state
->ts_acch
);
1576 pci_config_teardown(&state
->ts_pcih
);
1579 ac97_free(state
->ts_ac97
);
1582 audio_dev_free(state
->ts_adev
);
1584 ddi_soft_state_free(audiots_statep
, ddi_get_instance(state
->ts_dip
));