usr/src/uts/common/io/axf/ax88172reg.h

   1 /*
   2  * @(#)ax88172reg.h     1.1 09/06/15
   3  * Macro definitions for ASIX AX88172 USB to fast ethernet controler
   4  * based on ASIX AX88172/88772 data sheet
   5  * This file is public domain. Coded by M.Murayama (KHF04453@nifty.com)
   6  */
   7
   8 #ifndef __AX88172_H__
   9 #define __AX88172_H__
  10
  11 /*
  12  * Vendor command definitions
  13  */
  14 #define VCMD_READ_SRAM                  0x02
  15 #define VCMD_WRITE_RXSRAM               0x03
  16 #define VCMD_WRITE_TXSRAM               0x04
  17 #define VCMD_SOFTWARE_MII_OP            0x06
  18 #define VCMD_READ_MII_REG               0x07
  19 #define VCMD_WRITE_MII_REG              0x08
  20 #define VCMD_READ_MII_OPMODE            0x09
  21 #define VCMD_HARDWARE_MII_OP            0x0a
  22 #define VCMD_READ_SROM                  0x0b
  23 #define VCMD_WRITE_SROM                 0x0c
  24 #define VCMD_WRITE_SROM_ENABLE          0x0d
  25 #define VCMD_WRITE_SROM_DISABLE         0x0e
  26 #define VCMD_READ_RXCTRL                0x0f
  27 #define VCMD_WRITE_RXCTRL               0x10
  28 #define VCMD_READ_IPGS                  0x11
  29 #define VCMD_WRITE_IPG                  0x12
  30 #define VCMD_WRITE_IPG1                 0x13
  31 #define VCMD_WRITE_IPG2                 0x14
  32 #define VCMD_READ_MCAST_FILTER          0x15
  33 #define VCMD_WRITE_MCAST_FILTER         0x16
  34 #define VCMD_READ_NODE_ID               0x17
  35 #define VCMD_READ_PHY_IDS               0x19
  36 #define VCMD_READ_MEDIUM_STATUS         0x1a
  37 #define VCMD_WRITE_MEDIUM_STATUS        0x1b
  38 #define VCMD_SET_MONITOR_MODE           0x1c
  39 #define VCMD_GET_MONITOR_MODE           0x1d
  40 #define VCMD_READ_GPIO                  0x1e
  41 #define VCMD_WRITE_GPIO                 0x1f
  42
  43 /* ax88772 only,  currently not supported */
  44 #define VCMD_WRITE_IPGS_88772           0x12
  45 #define VCMD_READ_NODE_ID_88772         0x13
  46 #define VCMD_WRITE_NODE_ID_88772        0x14
  47 #define VCMD_WRITE_TEST_REG_88772       0x17
  48 #define VCMD_SOFTWARE_RESET_88772       0x20
  49 #define VCMD_READ_PHY_SELECT_88772      0x21
  50 #define VCMD_WRITE_PHY_SELECT_88772     0x22
  51
  52
  53 /*
  54  * Register definitions
  55  */
  56
  57 /* Rx control register */
  58 #define RCR_SO          0x80    /* Start Operation */
  59 #define RCR_AP_88772    0x20    /* accept physical address from mcast filter */
  60 #define RCR_AM          0x10    /* accept multicast address */
  61 #define RCR_AB          0x08    /* accept broadcast address */
  62 #define RCR_SEP         0x04    /* save error packet */
  63 #define RCR_AMALL       0x02    /* accept all multicast address */
  64 #define RCR_PRO         0x01    /* promiscious, all frames received */
  65
  66 #define RCR_MFB 0x0300
  67 #define         RCR_MFB_SHIFT   8
  68 #define         RCR_MFB_2K      (0U << RCR_MFB_SHIFT)
  69 #define         RCR_MFB_4K      (1U << RCR_MFB_SHIFT)
  70 #define         RCR_MFB_8K      (2U << RCR_MFB_SHIFT)
  71 #define         RCR_MFB_16K     (3U << RCR_MFB_SHIFT)
  72
  73 #define RCR_BITS        \
  74         "\020"  \
  75         "\010SO"        \
  76         "\006AP"        \
  77         "\005AM"        \
  78         "\004AB"        \
  79         "\003SEP"       \
  80         "\002AMALL"     \
  81         "\001PRO"
  82
  83 /* Medium status register */
  84 #define MSR_SM          0x1000  /* super mac support */
  85 #define MSR_SBP         0x0800  /* stop backpressure */
  86 #define MSR_PS          0x0200  /* port speed in mii mode */
  87 #define MSR_RE          0x0100  /* rx enable */
  88 #define MSR_PF          0x0080  /* check only length/type for pause frame */
  89 #define MSR_JFE         0x0040  /* jumbo frame enable */
  90 #define MSR_TFC         0x0020  /* tx flow control enable */
  91 #define MSR_RFC         0x0010  /* rx flow control enable (178) */
  92 #define MSR_FCEN        0x0010  /* flow control enable (172/772) */
  93 #define MSR_ENCK        0x0008  /* Enable GTX_CLK and TXC clock output (178) */
  94 #define MSR_TXABT       0x0004  /* Tx abort allow, always set */
  95 #define MSR_FDPX        0x0002  /* full duplex */
  96 #define MSR_GM          0x0001  /* Gigabit mode (178) */
  97
  98 #define MSR_BITS        \
  99         "\020"  \
 100         "\015SM"        \
 101         "\014SBP"       \
 102         "\012PS"        \
 103         "\011RE"        \
 104         "\005FCEN"      \
 105         "\004ENCK"      \
 106         "\003TXABT"     \
 107         "\002FDPX"      \
 108         "\001GM"
 109
 110 /* monitor mode register */
 111 #define MMR_RWMP        0x04    /* remote wakeup by magic pkt */
 112 #define MMR_RWLU        0x02    /* remote wakeup by linkup */
 113 #define MMR_MOM         0x01    /* monitor mode 1:en, 0:dis */
 114
 115 #define MMR_BITS        \
 116         "\020"  \
 117         "\003RWMP"      \
 118         "\002RWLU"      \
 119         "\001MOM"
 120
 121 /* GPIO register */
 122 #define GPIO_RSE        0x80    /* reload serial eeprom (88772) */
 123 #define GPIO_DATA2      0x20
 124 #define GPIO_EN2        0x10
 125 #define GPIO_DATA1      0x08
 126 #define GPIO_EN1        0x04
 127 #define GPIO_DATA0      0x02
 128 #define GPIO_EN0        0x01
 129
 130 #define GPIO_BITS       \
 131         "\020"          \
 132         "\010RSE"       \
 133         "\006DATA2"     \
 134         "\005EN2"       \
 135         "\004DATA1"     \
 136         "\003EN1"       \
 137         "\002DATA0"     \
 138         "\001EN0"
 139
 140 /* Software reset register */
 141 #define SWRST_IPPD      0x40    /* internal phy power down control */
 142 #define SWRST_IPRL      0x20    /* internal phy reset control */
 143 #define SWRST_BZ        0x10    /* force Bulk In to return zero-length pkt */
 144 #define SWRST_PRL       0x08    /* external phy reset pin level */
 145 #define SWRST_PRTE      0x04    /* external phy tri-state enable */
 146 #define SWRST_RT        0x02    /* clear frame length error for Bulk-Out */
 147 #define SWRST_RR        0x01    /* clear frame length error for Bulk-In */
 148
 149 #define SWRST_BITS      \
 150         "\020"          \
 151         "\007IPPD"      \
 152         "\006IPRL"      \
 153         "\005BZ"        \
 154         "\004PRL"       \
 155         "\003PRTE"      \
 156         "\002RT"        \
 157         "\001RR"
 158
 159 /* Software PHY Select Status register */
 160 #define SPSS_ASEL       0x02    /* 1:auto select 0:manual select */
 161 #define SPSS_PSEL       0x01    /* 1:intenal phy, 0:external (when ASEL=0) */
 162
 163 #endif /* __AX88172_H__ */