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preprocessor cleanup: __xpv
[unleashed.git] / usr / src / uts / i86pc / io / pci / pci_tools.c
blobe288a17b44d998acd19d6d4e1c5d8e45c3429863
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24
25 #include <sys/sysmacros.h>
26 #include <sys/types.h>
27 #include <sys/mkdev.h>
28 #include <sys/stat.h>
29 #include <sys/sunddi.h>
30 #include <vm/seg_kmem.h>
31 #include <sys/machparam.h>
32 #include <sys/sunndi.h>
33 #include <sys/ontrap.h>
34 #include <sys/psm.h>
35 #include <sys/pcie.h>
36 #include <sys/pci_cfgspace.h>
37 #include <sys/pci_tools.h>
38 #include <io/pci/pci_tools_ext.h>
39 #include <sys/apic.h>
40 #include <sys/apix.h>
41 #include <io/pci/pci_var.h>
42 #include <sys/pci_impl.h>
43 #include <sys/promif.h>
44 #include <sys/x86_archext.h>
45 #include <sys/cpuvar.h>
46 #include <sys/pci_cfgacc.h>
47
48
49 #define PCIEX_BDF_OFFSET_DELTA 4
50 #define PCIEX_REG_FUNC_SHIFT (PCI_REG_FUNC_SHIFT + PCIEX_BDF_OFFSET_DELTA)
51 #define PCIEX_REG_DEV_SHIFT (PCI_REG_DEV_SHIFT + PCIEX_BDF_OFFSET_DELTA)
52 #define PCIEX_REG_BUS_SHIFT (PCI_REG_BUS_SHIFT + PCIEX_BDF_OFFSET_DELTA)
53
54 #define SUCCESS 0
55
56 extern uint64_t mcfg_mem_base;
57 int pcitool_debug = 0;
58
59 /*
60 * Offsets of BARS in config space. First entry of 0 means config space.
61 * Entries here correlate to pcitool_bars_t enumerated type.
62 */
63 static uint8_t pci_bars[] = {
64 0x0,
65 PCI_CONF_BASE0,
66 PCI_CONF_BASE1,
67 PCI_CONF_BASE2,
68 PCI_CONF_BASE3,
69 PCI_CONF_BASE4,
70 PCI_CONF_BASE5,
71 PCI_CONF_ROM
72 };
73
74 /* Max offset allowed into config space for a particular device. */
75 static uint64_t max_cfg_size = PCI_CONF_HDR_SIZE;
76
77 static uint64_t pcitool_swap_endian(uint64_t data, int size);
78 static int pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag,
79 boolean_t io_access);
80 static int pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag);
81 static int pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr,
82 boolean_t write_flag);
83 static uint64_t pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages);
84 static void pcitool_unmap(uint64_t virt_addr, size_t num_pages);
85
86 /* Extern declarations */
87 extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *,
88 psm_intr_op_t, int *);
89
90 int
91 pcitool_init(dev_info_t *dip, boolean_t is_pciex)
92 {
93 int instance = ddi_get_instance(dip);
94
95 /* Create pcitool nodes for register access and interrupt routing. */
96
97 if (ddi_create_minor_node(dip, PCI_MINOR_REG, S_IFCHR,
98 PCI_MINOR_NUM(instance, PCI_TOOL_REG_MINOR_NUM),
99 DDI_NT_REGACC, 0) != DDI_SUCCESS) {
100 return (DDI_FAILURE);
101 }
102
103 if (ddi_create_minor_node(dip, PCI_MINOR_INTR, S_IFCHR,
104 PCI_MINOR_NUM(instance, PCI_TOOL_INTR_MINOR_NUM),
105 DDI_NT_INTRCTL, 0) != DDI_SUCCESS) {
106 ddi_remove_minor_node(dip, PCI_MINOR_REG);
107 return (DDI_FAILURE);
108 }
109
110 if (is_pciex)
111 max_cfg_size = PCIE_CONF_HDR_SIZE;
112
113 return (DDI_SUCCESS);
114 }
115
116 void
117 pcitool_uninit(dev_info_t *dip)
118 {
119 ddi_remove_minor_node(dip, PCI_MINOR_INTR);
120 ddi_remove_minor_node(dip, PCI_MINOR_REG);
121 }
122
123 /*ARGSUSED*/
124 static int
125 pcitool_set_intr(dev_info_t *dip, void *arg, int mode)
126 {
127 ddi_intr_handle_impl_t info_hdl;
128 pcitool_intr_set_t iset;
129 uint32_t old_cpu;
130 int ret, result;
131 size_t copyinout_size;
132 int rval = SUCCESS;
133 apic_get_type_t type_info;
134
135 /* Version 1 of pcitool_intr_set_t doesn't have flags. */
136 copyinout_size = (size_t)&iset.flags - (size_t)&iset;
137
138 if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS)
139 return (EFAULT);
140
141 switch (iset.user_version) {
142 case PCITOOL_V1:
143 break;
144
145 case PCITOOL_V2:
146 copyinout_size = sizeof (pcitool_intr_set_t);
147 if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS)
148 return (EFAULT);
149 break;
150
151 default:
152 iset.status = PCITOOL_OUT_OF_RANGE;
153 rval = ENOTSUP;
154 goto done_set_intr;
155 }
156
157 if (iset.flags & PCITOOL_INTR_FLAG_SET_MSI) {
158 rval = ENOTSUP;
159 iset.status = PCITOOL_IO_ERROR;
160 goto done_set_intr;
161 }
162
163 info_hdl.ih_private = &type_info;
164
165 if ((*psm_intr_ops)(NULL, &info_hdl,
166 PSM_INTR_OP_APIC_TYPE, NULL) != PSM_SUCCESS) {
167 rval = ENOTSUP;
168 iset.status = PCITOOL_IO_ERROR;
169 goto done_set_intr;
170 }
171
172 if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) {
173 if (iset.old_cpu > type_info.avgi_num_cpu) {
174 rval = EINVAL;
175 iset.status = PCITOOL_INVALID_CPUID;
176 goto done_set_intr;
177 }
178 old_cpu = iset.old_cpu;
179 } else {
180 if ((old_cpu =
181 pci_get_cpu_from_vecirq(iset.ino, IS_VEC)) == -1) {
182 iset.status = PCITOOL_IO_ERROR;
183 rval = EINVAL;
184 goto done_set_intr;
185 }
186 }
187
188 if (iset.ino > type_info.avgi_num_intr) {
189 rval = EINVAL;
190 iset.status = PCITOOL_INVALID_INO;
191 goto done_set_intr;
192 }
193
194 iset.status = PCITOOL_SUCCESS;
195
196 old_cpu &= ~PSMGI_CPU_USER_BOUND;
197
198 /*
199 * For this locally-declared and used handle, ih_private will contain a
200 * CPU value, not an ihdl_plat_t as used for global interrupt handling.
201 */
202 if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) {
203 info_hdl.ih_vector = APIX_VIRTVECTOR(old_cpu, iset.ino);
204 } else {
205 info_hdl.ih_vector = iset.ino;
206 }
207 info_hdl.ih_private = (void *)(uintptr_t)iset.cpu_id;
208 info_hdl.ih_flags = PSMGI_INTRBY_VEC;
209 if (pcitool_debug)
210 prom_printf("user version:%d, flags:0x%x\n",
211 iset.user_version, iset.flags);
212
213 result = ENOTSUP;
214 if ((iset.user_version >= PCITOOL_V2) &&
215 (iset.flags & PCITOOL_INTR_FLAG_SET_GROUP)) {
216 ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_GRP_SET_CPU,
217 &result);
218 } else {
219 ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_SET_CPU,
220 &result);
221 }
222
223 if (ret != PSM_SUCCESS) {
224 switch (result) {
225 case EIO: /* Error making the change */
226 rval = EIO;
227 iset.status = PCITOOL_IO_ERROR;
228 break;
229 case ENXIO: /* Couldn't convert vector to irq */
230 rval = EINVAL;
231 iset.status = PCITOOL_INVALID_INO;
232 break;
233 case EINVAL: /* CPU out of range */
234 rval = EINVAL;
235 iset.status = PCITOOL_INVALID_CPUID;
236 break;
237 case ENOTSUP: /* Requested PSM intr ops missing */
238 rval = ENOTSUP;
239 iset.status = PCITOOL_IO_ERROR;
240 break;
241 }
242 }
243
244 /* Return original CPU. */
245 iset.cpu_id = old_cpu;
246
247 /* Return new vector */
248 if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) {
249 iset.ino = APIX_VIRTVEC_VECTOR(info_hdl.ih_vector);
250 }
251
252 done_set_intr:
253 iset.drvr_version = PCITOOL_VERSION;
254 if (ddi_copyout(&iset, arg, copyinout_size, mode) != DDI_SUCCESS)
255 rval = EFAULT;
256 return (rval);
257 }
258
259
260 /* It is assumed that dip != NULL */
261 static void
262 pcitool_get_intr_dev_info(dev_info_t *dip, pcitool_intr_dev_t *devs)
263 {
264 (void) strncpy(devs->driver_name,
265 ddi_driver_name(dip), MAXMODCONFNAME-2);
266 devs->driver_name[MAXMODCONFNAME-1] = '\0';
267 (void) ddi_pathname(dip, devs->path);
268 devs->dev_inst = ddi_get_instance(dip);
269 }
270
271 static int
272 pcitool_get_intr(dev_info_t *dip, void *arg, int mode)
273 {
274 /* Array part isn't used here, but oh well... */
275 pcitool_intr_get_t partial_iget;
276 pcitool_intr_get_t *iget = &partial_iget;
277 size_t iget_kmem_alloc_size = 0;
278 uint8_t num_devs_ret;
279 int copyout_rval;
280 int rval = SUCCESS;
281 int circ;
282 int i;
283
284 ddi_intr_handle_impl_t info_hdl;
285 apic_get_intr_t intr_info;
286 apic_get_type_t type_info;
287
288 /* Read in just the header part, no array section. */
289 if (ddi_copyin(arg, &partial_iget, PCITOOL_IGET_SIZE(0), mode) !=
290 DDI_SUCCESS)
291 return (EFAULT);
292
293 if (partial_iget.flags & PCITOOL_INTR_FLAG_GET_MSI) {
294 partial_iget.status = PCITOOL_IO_ERROR;
295 partial_iget.num_devs_ret = 0;
296 rval = ENOTSUP;
297 goto done_get_intr;
298 }
299
300 info_hdl.ih_private = &type_info;
301
302 if ((*psm_intr_ops)(NULL, &info_hdl,
303 PSM_INTR_OP_APIC_TYPE, NULL) != PSM_SUCCESS) {
304 iget->status = PCITOOL_IO_ERROR;
305 iget->num_devs_ret = 0;
306 rval = EINVAL;
307 goto done_get_intr;
308 }
309
310 if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) {
311 if (partial_iget.cpu_id > type_info.avgi_num_cpu) {
312 partial_iget.status = PCITOOL_INVALID_CPUID;
313 partial_iget.num_devs_ret = 0;
314 rval = EINVAL;
315 goto done_get_intr;
316 }
317 }
318
319 /* Validate argument. */
320 if ((partial_iget.ino & APIX_VIRTVEC_VECMASK) >
321 type_info.avgi_num_intr) {
322 partial_iget.status = PCITOOL_INVALID_INO;
323 partial_iget.num_devs_ret = 0;
324 rval = EINVAL;
325 goto done_get_intr;
326 }
327
328 num_devs_ret = partial_iget.num_devs_ret;
329 intr_info.avgi_dip_list = NULL;
330 intr_info.avgi_req_flags =
331 PSMGI_REQ_CPUID | PSMGI_REQ_NUM_DEVS | PSMGI_INTRBY_VEC;
332 /*
333 * For this locally-declared and used handle, ih_private will contain a
334 * pointer to apic_get_intr_t, not an ihdl_plat_t as used for
335 * global interrupt handling.
336 */
337 info_hdl.ih_private = &intr_info;
338
339 if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) {
340 info_hdl.ih_vector =
341 APIX_VIRTVECTOR(partial_iget.cpu_id, partial_iget.ino);
342 } else {
343 info_hdl.ih_vector = partial_iget.ino;
344 }
345
346 /* Caller wants device information returned. */
347 if (num_devs_ret > 0) {
348
349 intr_info.avgi_req_flags |= PSMGI_REQ_GET_DEVS;
350
351 /*
352 * Allocate room.
353 * If num_devs_ret == 0 iget remains pointing to partial_iget.
354 */
355 iget_kmem_alloc_size = PCITOOL_IGET_SIZE(num_devs_ret);
356 iget = kmem_alloc(iget_kmem_alloc_size, KM_SLEEP);
357
358 /* Read in whole structure to verify there's room. */
359 if (ddi_copyin(arg, iget, iget_kmem_alloc_size, mode) !=
360 SUCCESS) {
361
362 /* Be consistent and just return EFAULT here. */
363 kmem_free(iget, iget_kmem_alloc_size);
364
365 return (EFAULT);
366 }
367 }
368
369 bzero(iget, PCITOOL_IGET_SIZE(num_devs_ret));
370 iget->ino = info_hdl.ih_vector;
371
372 /*
373 * Lock device tree branch from the pci root nexus on down if info will
374 * be extracted from dips returned from the tree.
375 */
376 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) {
377 ndi_devi_enter(dip, &circ);
378 }
379
380 /* Call psm_intr_ops(PSM_INTR_OP_GET_INTR) to get information. */
381 if ((rval = (*psm_intr_ops)(NULL, &info_hdl,
382 PSM_INTR_OP_GET_INTR, NULL)) != PSM_SUCCESS) {
383 iget->status = PCITOOL_IO_ERROR;
384 iget->num_devs_ret = 0;
385 rval = EINVAL;
386 goto done_get_intr;
387 }
388
389 /*
390 * Fill in the pcitool_intr_get_t to be returned,
391 * with the CPU, num_devs_ret and num_devs.
392 */
393 if (intr_info.avgi_cpu_id == IRQ_UNBOUND ||
394 intr_info.avgi_cpu_id == IRQ_UNINIT)
395 iget->cpu_id = 0;
396 else
397 iget->cpu_id = intr_info.avgi_cpu_id & ~PSMGI_CPU_USER_BOUND;
398
399 /* Number of devices returned by apic. */
400 iget->num_devs = intr_info.avgi_num_devs;
401
402 /* Device info was returned. */
403 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) {
404
405 /*
406 * num devs returned is num devs ret by apic,
407 * space permitting.
408 */
409 iget->num_devs_ret = min(num_devs_ret, intr_info.avgi_num_devs);
410
411 /*
412 * Loop thru list of dips and extract driver, name and instance.
413 * Fill in the pcitool_intr_dev_t's with this info.
414 */
415 for (i = 0; i < iget->num_devs_ret; i++)
416 pcitool_get_intr_dev_info(intr_info.avgi_dip_list[i],
417 &iget->dev[i]);
418
419 /* Free kmem_alloc'ed memory of the apic_get_intr_t */
420 kmem_free(intr_info.avgi_dip_list,
421 intr_info.avgi_num_devs * sizeof (dev_info_t *));
422 }
423
424 done_get_intr:
425
426 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) {
427 ndi_devi_exit(dip, circ);
428 }
429
430 iget->drvr_version = PCITOOL_VERSION;
431 copyout_rval = ddi_copyout(iget, arg,
432 PCITOOL_IGET_SIZE(num_devs_ret), mode);
433
434 if (iget_kmem_alloc_size > 0)
435 kmem_free(iget, iget_kmem_alloc_size);
436
437 if (copyout_rval != DDI_SUCCESS)
438 rval = EFAULT;
439
440 return (rval);
441 }
442
443 /*ARGSUSED*/
444 static int
445 pcitool_intr_info(dev_info_t *dip, void *arg, int mode)
446 {
447 pcitool_intr_info_t intr_info;
448 ddi_intr_handle_impl_t info_hdl;
449 int rval = SUCCESS;
450 apic_get_type_t type_info;
451
452 /* If we need user_version, and to ret same user version as passed in */
453 if (ddi_copyin(arg, &intr_info, sizeof (pcitool_intr_info_t), mode) !=
454 DDI_SUCCESS) {
455 if (pcitool_debug)
456 prom_printf("Error reading arguments\n");
457 return (EFAULT);
458 }
459
460 if (intr_info.flags & PCITOOL_INTR_FLAG_GET_MSI)
461 return (ENOTSUP);
462
463 info_hdl.ih_private = &type_info;
464
465 /* For UPPC systems, psm_intr_ops has no entry for APIC_TYPE. */
466 if ((rval = (*psm_intr_ops)(NULL, &info_hdl,
467 PSM_INTR_OP_APIC_TYPE, NULL)) != PSM_SUCCESS) {
468 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UPPC;
469 intr_info.ctlr_version = 0;
470 intr_info.num_intr = APIC_MAX_VECTOR;
471 } else {
472 intr_info.ctlr_version = (uint32_t)info_hdl.ih_ver;
473 intr_info.num_cpu = type_info.avgi_num_cpu;
474 if (strcmp(type_info.avgi_type,
475 APIC_PCPLUSMP_NAME) == 0) {
476 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_PCPLUSMP;
477 intr_info.num_intr = type_info.avgi_num_intr;
478 } else if (strcmp(type_info.avgi_type,
479 APIC_APIX_NAME) == 0) {
480 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_APIX;
481 intr_info.num_intr = type_info.avgi_num_intr;
482 } else {
483 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UNKNOWN;
484 intr_info.num_intr = APIC_MAX_VECTOR;
485 }
486 }
487
488 intr_info.drvr_version = PCITOOL_VERSION;
489 if (ddi_copyout(&intr_info, arg, sizeof (pcitool_intr_info_t), mode) !=
490 DDI_SUCCESS) {
491 if (pcitool_debug)
492 prom_printf("Error returning arguments.\n");
493 rval = EFAULT;
494 }
495
496 return (rval);
497 }
498
499
500
501 /*
502 * Main function for handling interrupt CPU binding requests and queries.
503 * Need to implement later
504 */
505 int
506 pcitool_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode)
507 {
508 int rval;
509
510 switch (cmd) {
511
512 /* Associate a new CPU with a given vector */
513 case PCITOOL_DEVICE_SET_INTR:
514 rval = pcitool_set_intr(dip, arg, mode);
515 break;
516
517 case PCITOOL_DEVICE_GET_INTR:
518 rval = pcitool_get_intr(dip, arg, mode);
519 break;
520
521 case PCITOOL_SYSTEM_INTR_INFO:
522 rval = pcitool_intr_info(dip, arg, mode);
523 break;
524
525 default:
526 rval = ENOTSUP;
527 }
528
529 return (rval);
530 }
531
532 /*
533 * Perform register accesses on the nexus device itself.
534 * No explicit PCI nexus device for X86, so not applicable.
535 */
536
537 /*ARGSUSED*/
538 int
539 pcitool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode)
540 {
541 return (ENOTSUP);
542 }
543
544 /* Swap endianness. */
545 static uint64_t
546 pcitool_swap_endian(uint64_t data, int size)
547 {
548 typedef union {
549 uint64_t data64;
550 uint8_t data8[8];
551 } data_split_t;
552
553 data_split_t orig_data;
554 data_split_t returned_data;
555 int i;
556
557 orig_data.data64 = data;
558 returned_data.data64 = 0;
559
560 for (i = 0; i < size; i++) {
561 returned_data.data8[i] = orig_data.data8[size - 1 - i];
562 }
563
564 return (returned_data.data64);
565 }
566
567 /*
568 * A note about ontrap handling:
569 *
570 * X86 systems on which this module was tested return FFs instead of bus errors
571 * when accessing devices with invalid addresses. Ontrap handling, which
572 * gracefully handles kernel bus errors, is installed anyway for I/O and mem
573 * space accessing (not for pci config space), in case future X86 platforms
574 * require it.
575 */
576
577 /* Access device. prg is modified. */
578 static int
579 pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag,
580 boolean_t io_access)
581 {
582 int size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr);
583 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr);
584 int rval = SUCCESS;
585 uint64_t local_data;
586 pci_cfgacc_req_t req;
587 uint32_t max_offset;
588
589 if ((size <= 0) || (size > 8) || !ISP2(size)) {
590 prg->status = PCITOOL_INVALID_SIZE;
591 return (ENOTSUP);
592 }
593
594 /*
595 * NOTE: there is no way to verify whether or not the address is
596 * valid other than that it is within the maximum offset. The
597 * put functions return void and the get functions return -1 on error.
598 */
599
600 if (io_access)
601 max_offset = 0xFF;
602 else
603 max_offset = 0xFFF;
604 if (prg->offset + size - 1 > max_offset) {
605 prg->status = PCITOOL_INVALID_ADDRESS;
606 return (ENOTSUP);
607 }
608
609 prg->status = PCITOOL_SUCCESS;
610
611 req.rcdip = NULL;
612 req.bdf = PCI_GETBDF(prg->bus_no, prg->dev_no, prg->func_no);
613 req.offset = prg->offset;
614 req.size = size;
615 req.write = write_flag;
616 req.ioacc = io_access;
617 if (write_flag) {
618 if (big_endian) {
619 local_data = pcitool_swap_endian(prg->data, size);
620 } else {
621 local_data = prg->data;
622 }
623 VAL64(&req) = local_data;
624 pci_cfgacc_acc(&req);
625 } else {
626 pci_cfgacc_acc(&req);
627 switch (size) {
628 case 1:
629 local_data = VAL8(&req);
630 break;
631 case 2:
632 local_data = VAL16(&req);
633 break;
634 case 4:
635 local_data = VAL32(&req);
636 break;
637 case 8:
638 local_data = VAL64(&req);
639 break;
640 }
641 if (big_endian) {
642 prg->data =
643 pcitool_swap_endian(local_data, size);
644 } else {
645 prg->data = local_data;
646 }
647 }
648 /*
649 * Check if legacy IO config access is used, in which case
650 * only first 256 bytes are valid.
651 */
652 if (req.ioacc && (prg->offset + size - 1 > 0xFF)) {
653 prg->status = PCITOOL_INVALID_ADDRESS;
654 return (ENOTSUP);
655 }
656
657 /* Set phys_addr only if MMIO is used */
658 prg->phys_addr = 0;
659 if (!req.ioacc && mcfg_mem_base != 0) {
660 prg->phys_addr = mcfg_mem_base + prg->offset +
661 ((prg->bus_no << PCIEX_REG_BUS_SHIFT) |
662 (prg->dev_no << PCIEX_REG_DEV_SHIFT) |
663 (prg->func_no << PCIEX_REG_FUNC_SHIFT));
664 }
665
666 return (rval);
667 }
668
669 static int
670 pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag)
671 {
672 int port = (int)prg->phys_addr;
673 size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr);
674 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr);
675 int rval = SUCCESS;
676 on_trap_data_t otd;
677 uint64_t local_data;
678
679
680 /*
681 * on_trap works like setjmp.
682 *
683 * A non-zero return here means on_trap has returned from an error.
684 *
685 * A zero return here means that on_trap has just returned from setup.
686 */
687 if (on_trap(&otd, OT_DATA_ACCESS)) {
688 no_trap();
689 if (pcitool_debug)
690 prom_printf(
691 "pcitool_io_access: on_trap caught an error...\n");
692 prg->status = PCITOOL_INVALID_ADDRESS;
693 return (EFAULT);
694 }
695
696 if (write_flag) {
697
698 if (big_endian) {
699 local_data = pcitool_swap_endian(prg->data, size);
700 } else {
701 local_data = prg->data;
702 }
703
704 if (pcitool_debug)
705 prom_printf("Writing %ld byte(s) to port 0x%x\n",
706 size, port);
707
708 switch (size) {
709 case 1:
710 outb(port, (uint8_t)local_data);
711 break;
712 case 2:
713 outw(port, (uint16_t)local_data);
714 break;
715 case 4:
716 outl(port, (uint32_t)local_data);
717 break;
718 default:
719 rval = ENOTSUP;
720 prg->status = PCITOOL_INVALID_SIZE;
721 break;
722 }
723 } else {
724 if (pcitool_debug)
725 prom_printf("Reading %ld byte(s) from port 0x%x\n",
726 size, port);
727
728 switch (size) {
729 case 1:
730 local_data = inb(port);
731 break;
732 case 2:
733 local_data = inw(port);
734 break;
735 case 4:
736 local_data = inl(port);
737 break;
738 default:
739 rval = ENOTSUP;
740 prg->status = PCITOOL_INVALID_SIZE;
741 break;
742 }
743
744 if (rval == SUCCESS) {
745 if (big_endian) {
746 prg->data =
747 pcitool_swap_endian(local_data, size);
748 } else {
749 prg->data = local_data;
750 }
751 }
752 }
753
754 no_trap();
755 return (rval);
756 }
757
758 static int
759 pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr, boolean_t write_flag)
760 {
761 size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr);
762 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr);
763 int rval = DDI_SUCCESS;
764 on_trap_data_t otd;
765 uint64_t local_data;
766
767 /*
768 * on_trap works like setjmp.
769 *
770 * A non-zero return here means on_trap has returned from an error.
771 *
772 * A zero return here means that on_trap has just returned from setup.
773 */
774 if (on_trap(&otd, OT_DATA_ACCESS)) {
775 no_trap();
776 if (pcitool_debug)
777 prom_printf(
778 "pcitool_mem_access: on_trap caught an error...\n");
779 prg->status = PCITOOL_INVALID_ADDRESS;
780 return (EFAULT);
781 }
782
783 if (write_flag) {
784
785 if (big_endian) {
786 local_data = pcitool_swap_endian(prg->data, size);
787 } else {
788 local_data = prg->data;
789 }
790
791 switch (size) {
792 case 1:
793 *((uint8_t *)(uintptr_t)virt_addr) = local_data;
794 break;
795 case 2:
796 *((uint16_t *)(uintptr_t)virt_addr) = local_data;
797 break;
798 case 4:
799 *((uint32_t *)(uintptr_t)virt_addr) = local_data;
800 break;
801 case 8:
802 *((uint64_t *)(uintptr_t)virt_addr) = local_data;
803 break;
804 default:
805 rval = ENOTSUP;
806 prg->status = PCITOOL_INVALID_SIZE;
807 break;
808 }
809 } else {
810 switch (size) {
811 case 1:
812 local_data = *((uint8_t *)(uintptr_t)virt_addr);
813 break;
814 case 2:
815 local_data = *((uint16_t *)(uintptr_t)virt_addr);
816 break;
817 case 4:
818 local_data = *((uint32_t *)(uintptr_t)virt_addr);
819 break;
820 case 8:
821 local_data = *((uint64_t *)(uintptr_t)virt_addr);
822 break;
823 default:
824 rval = ENOTSUP;
825 prg->status = PCITOOL_INVALID_SIZE;
826 break;
827 }
828
829 if (rval == SUCCESS) {
830 if (big_endian) {
831 prg->data =
832 pcitool_swap_endian(local_data, size);
833 } else {
834 prg->data = local_data;
835 }
836 }
837 }
838
839 no_trap();
840 return (rval);
841 }
842
843 /*
844 * Map up to 2 pages which contain the address we want to access.
845 *
846 * Mapping should span no more than 8 bytes. With X86 it is possible for an
847 * 8 byte value to start on a 4 byte boundary, so it can cross a page boundary.
848 * We'll never have to map more than two pages.
849 */
850
851 static uint64_t
852 pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages)
853 {
854
855 uint64_t page_base = phys_addr & ~MMU_PAGEOFFSET;
856 uint64_t offset = phys_addr & MMU_PAGEOFFSET;
857 void *virt_base;
858 uint64_t returned_addr;
859 pfn_t pfn;
860
861 if (pcitool_debug)
862 prom_printf("pcitool_map: Called with PA:0x%p\n",
863 (void *)(uintptr_t)phys_addr);
864
865 *num_pages = 1;
866
867 /* Desired mapping would span more than two pages. */
868 if ((offset + size) > (MMU_PAGESIZE * 2)) {
869 if (pcitool_debug)
870 prom_printf("boundary violation: "
871 "offset:0x%" PRIx64 ", size:%ld, pagesize:0x%lx\n",
872 offset, (uintptr_t)size, (uintptr_t)MMU_PAGESIZE);
873 return (0);
874
875 } else if ((offset + size) > MMU_PAGESIZE) {
876 (*num_pages)++;
877 }
878
879 /* Get page(s) of virtual space. */
880 virt_base = vmem_alloc(heap_arena, ptob(*num_pages), VM_NOSLEEP);
881 if (virt_base == NULL) {
882 if (pcitool_debug)
883 prom_printf("Couldn't get virtual base address.\n");
884 return (0);
885 }
886
887 if (pcitool_debug)
888 prom_printf("Got base virtual address:0x%p\n", virt_base);
889
890 pfn = btop(page_base);
891
892 /* Now map the allocated virtual space to the physical address. */
893 hat_devload(kas.a_hat, virt_base, mmu_ptob(*num_pages), pfn,
894 PROT_READ | PROT_WRITE | HAT_STRICTORDER,
895 HAT_LOAD_LOCK);
896
897 returned_addr = ((uintptr_t)(virt_base)) + offset;
898
899 if (pcitool_debug)
900 prom_printf("pcitool_map: returning VA:0x%p\n",
901 (void *)(uintptr_t)returned_addr);
902
903 return (returned_addr);
904 }
905
906 /* Unmap the mapped page(s). */
907 static void
908 pcitool_unmap(uint64_t virt_addr, size_t num_pages)
909 {
910 void *base_virt_addr = (void *)(uintptr_t)(virt_addr & ~MMU_PAGEOFFSET);
911
912 hat_unload(kas.a_hat, base_virt_addr, ptob(num_pages),
913 HAT_UNLOAD_UNLOCK);
914 vmem_free(heap_arena, base_virt_addr, ptob(num_pages));
915 }
916
917
918 /* Perform register accesses on PCI leaf devices. */
919 /*ARGSUSED*/
920 int
921 pcitool_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode)
922 {
923 boolean_t write_flag = B_FALSE;
924 boolean_t io_access = B_TRUE;
925 int rval = 0;
926 pcitool_reg_t prg;
927 uint8_t size;
928
929 uint64_t base_addr;
930 uint64_t virt_addr;
931 size_t num_virt_pages;
932
933 switch (cmd) {
934 case (PCITOOL_DEVICE_SET_REG):
935 write_flag = B_TRUE;
936
937 /*FALLTHRU*/
938 case (PCITOOL_DEVICE_GET_REG):
939 if (pcitool_debug)
940 prom_printf("pci_dev_reg_ops set/get reg\n");
941 if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) !=
942 DDI_SUCCESS) {
943 if (pcitool_debug)
944 prom_printf("Error reading arguments\n");
945 return (EFAULT);
946 }
947
948 if (prg.barnum >= (sizeof (pci_bars) / sizeof (pci_bars[0]))) {
949 prg.status = PCITOOL_OUT_OF_RANGE;
950 rval = EINVAL;
951 goto done_reg;
952 }
953
954 if (pcitool_debug)
955 prom_printf("raw bus:0x%x, dev:0x%x, func:0x%x\n",
956 prg.bus_no, prg.dev_no, prg.func_no);
957 /* Validate address arguments of bus / dev / func */
958 if (((prg.bus_no &
959 (PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT)) !=
960 prg.bus_no) ||
961 ((prg.dev_no &
962 (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) !=
963 prg.dev_no) ||
964 ((prg.func_no &
965 (PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT)) !=
966 prg.func_no)) {
967 prg.status = PCITOOL_INVALID_ADDRESS;
968 rval = EINVAL;
969 goto done_reg;
970 }
971
972 size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr);
973
974 /* Proper config space desired. */
975 if (prg.barnum == 0) {
976
977 if (pcitool_debug)
978 prom_printf(
979 "config access: offset:0x%" PRIx64 ", "
980 "phys_addr:0x%" PRIx64 "\n",
981 prg.offset, prg.phys_addr);
982
983 if (prg.offset >= max_cfg_size) {
984 prg.status = PCITOOL_OUT_OF_RANGE;
985 rval = EINVAL;
986 goto done_reg;
987 }
988 if (max_cfg_size == PCIE_CONF_HDR_SIZE)
989 io_access = B_FALSE;
990
991 rval = pcitool_cfg_access(&prg, write_flag, io_access);
992 if (pcitool_debug)
993 prom_printf(
994 "config access: data:0x%" PRIx64 "\n",
995 prg.data);
996
997 /* IO/ MEM/ MEM64 space. */
998 } else {
999
1000 pcitool_reg_t prg2;
1001 bcopy(&prg, &prg2, sizeof (pcitool_reg_t));
1002
1003 /*
1004 * Translate BAR number into offset of the BAR in
1005 * the device's config space.
1006 */
1007 prg2.offset = pci_bars[prg2.barnum];
1008 prg2.acc_attr =
1009 PCITOOL_ACC_ATTR_SIZE_4 | PCITOOL_ACC_ATTR_ENDN_LTL;
1010
1011 if (pcitool_debug)
1012 prom_printf(
1013 "barnum:%d, bar_offset:0x%" PRIx64 "\n",
1014 prg2.barnum, prg2.offset);
1015 /*
1016 * Get Bus Address Register (BAR) from config space.
1017 * prg2.offset is the offset into config space of the
1018 * BAR desired. prg.status is modified on error.
1019 */
1020 rval = pcitool_cfg_access(&prg2, B_FALSE, B_TRUE);
1021 if (rval != SUCCESS) {
1022 if (pcitool_debug)
1023 prom_printf("BAR access failed\n");
1024 prg.status = prg2.status;
1025 goto done_reg;
1026 }
1027 /*
1028 * Reference proper PCI space based on the BAR.
1029 * If 64 bit MEM space, need to load other half of the
1030 * BAR first.
1031 */
1032
1033 if (pcitool_debug)
1034 prom_printf("bar returned is 0x%" PRIx64 "\n",
1035 prg2.data);
1036 if (!prg2.data) {
1037 if (pcitool_debug)
1038 prom_printf("BAR data == 0\n");
1039 rval = EINVAL;
1040 prg.status = PCITOOL_INVALID_ADDRESS;
1041 goto done_reg;
1042 }
1043 if (prg2.data == 0xffffffff) {
1044 if (pcitool_debug)
1045 prom_printf("BAR data == -1\n");
1046 rval = EINVAL;
1047 prg.status = PCITOOL_INVALID_ADDRESS;
1048 goto done_reg;
1049 }
1050
1051 /*
1052 * BAR has bits saying this space is IO space, unless
1053 * this is the ROM address register.
1054 */
1055 if (((PCI_BASE_SPACE_M & prg2.data) ==
1056 PCI_BASE_SPACE_IO) &&
1057 (prg2.offset != PCI_CONF_ROM)) {
1058 if (pcitool_debug)
1059 prom_printf("IO space\n");
1060
1061 prg2.data &= PCI_BASE_IO_ADDR_M;
1062 prg.phys_addr = prg2.data + prg.offset;
1063
1064 rval = pcitool_io_access(&prg, write_flag);
1065 if ((rval != SUCCESS) && (pcitool_debug))
1066 prom_printf("IO access failed\n");
1067
1068 goto done_reg;
1069
1070
1071 /*
1072 * BAR has bits saying this space is 64 bit memory
1073 * space, unless this is the ROM address register.
1074 *
1075 * The 64 bit address stored in two BAR cells is not
1076 * necessarily aligned on an 8-byte boundary.
1077 * Need to keep the first 4 bytes read,
1078 * and do a separate read of the high 4 bytes.
1079 */
1080
1081 } else if ((PCI_BASE_TYPE_ALL & prg2.data) &&
1082 (prg2.offset != PCI_CONF_ROM)) {
1083
1084 uint32_t low_bytes =
1085 (uint32_t)(prg2.data & ~PCI_BASE_TYPE_ALL);
1086
1087 /*
1088 * Don't try to read the next 4 bytes
1089 * past the end of BARs.
1090 */
1091 if (prg2.offset >= PCI_CONF_BASE5) {
1092 prg.status = PCITOOL_OUT_OF_RANGE;
1093 rval = EIO;
1094 goto done_reg;
1095 }
1096
1097 /*
1098 * Access device.
1099 * prg2.status is modified on error.
1100 */
1101 prg2.offset += 4;
1102 rval = pcitool_cfg_access(&prg2,
1103 B_FALSE, B_TRUE);
1104 if (rval != SUCCESS) {
1105 prg.status = prg2.status;
1106 goto done_reg;
1107 }
1108
1109 if (prg2.data == 0xffffffff) {
1110 prg.status = PCITOOL_INVALID_ADDRESS;
1111 prg.status = EFAULT;
1112 goto done_reg;
1113 }
1114
1115 prg2.data = (prg2.data << 32) + low_bytes;
1116 if (pcitool_debug)
1117 prom_printf(
1118 "64 bit mem space. "
1119 "64-bit bar is 0x%" PRIx64 "\n",
1120 prg2.data);
1121
1122 /* Mem32 space, including ROM */
1123 } else {
1124
1125 if (prg2.offset == PCI_CONF_ROM) {
1126 if (pcitool_debug)
1127 prom_printf(
1128 "Additional ROM "
1129 "checking\n");
1130 /* Can't write to ROM */
1131 if (write_flag) {
1132 prg.status = PCITOOL_ROM_WRITE;
1133 rval = EIO;
1134 goto done_reg;
1135
1136 /* ROM disabled for reading */
1137 } else if (!(prg2.data & 0x00000001)) {
1138 prg.status =
1139 PCITOOL_ROM_DISABLED;
1140 rval = EIO;
1141 goto done_reg;
1142 }
1143 }
1144
1145 if (pcitool_debug)
1146 prom_printf("32 bit mem space\n");
1147 }
1148
1149 /* Common code for all IO/MEM range spaces. */
1150
1151 base_addr = prg2.data;
1152 if (pcitool_debug)
1153 prom_printf(
1154 "addr portion of bar is 0x%" PRIx64 ", "
1155 "base=0x%" PRIx64 ", "
1156 "offset:0x%" PRIx64 "\n",
1157 prg2.data, base_addr, prg.offset);
1158 /*
1159 * Use offset provided by caller to index into
1160 * desired space, then access.
1161 * Note that prg.status is modified on error.
1162 */
1163 prg.phys_addr = base_addr + prg.offset;
1164
1165 virt_addr = pcitool_map(prg.phys_addr, size,
1166 &num_virt_pages);
1167 if (virt_addr == (uintptr_t)NULL) {
1168 prg.status = PCITOOL_IO_ERROR;
1169 rval = EIO;
1170 goto done_reg;
1171 }
1172
1173 rval = pcitool_mem_access(&prg, virt_addr, write_flag);
1174 pcitool_unmap(virt_addr, num_virt_pages);
1175 }
1176 done_reg:
1177 prg.drvr_version = PCITOOL_VERSION;
1178 if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) !=
1179 DDI_SUCCESS) {
1180 if (pcitool_debug)
1181 prom_printf("Error returning arguments.\n");
1182 rval = EFAULT;
1183 }
1184 break;
1185 default:
1186 rval = ENOTTY;
1187 break;
1188 }
1189 return (rval);
1190 }
Unleashed OS