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preprocessor cleanup: __xpv
[unleashed.git] / arch / x86 / kernel / platform / i86pc / os / trap.c
blobaf31f8247599259db19518566f5bfab172358c83
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
27 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
28 /* All Rights Reserved */
29 /* */
30 /* Copyright (c) 1987, 1988 Microsoft Corporation */
31 /* All Rights Reserved */
32 /* */
33
34 /*
35 * Copyright 2012 Joyent, Inc. All rights reserved.
36 */
37
38 #include <sys/types.h>
39 #include <sys/sysmacros.h>
40 #include <sys/param.h>
41 #include <sys/signal.h>
42 #include <sys/systm.h>
43 #include <sys/user.h>
44 #include <sys/proc.h>
45 #include <sys/disp.h>
46 #include <sys/class.h>
47 #include <sys/core.h>
48 #include <sys/syscall.h>
49 #include <sys/cpuvar.h>
50 #include <sys/vm.h>
51 #include <sys/sysinfo.h>
52 #include <sys/fault.h>
53 #include <sys/stack.h>
54 #include <sys/psw.h>
55 #include <sys/regset.h>
56 #include <sys/fp.h>
57 #include <sys/trap.h>
58 #include <sys/kmem.h>
59 #include <sys/vtrace.h>
60 #include <sys/cmn_err.h>
61 #include <sys/prsystm.h>
62 #include <sys/mutex_impl.h>
63 #include <sys/machsystm.h>
64 #include <sys/archsystm.h>
65 #include <sys/sdt.h>
66 #include <sys/avintr.h>
67 #include <sys/kobj.h>
68
69 #include <vm/hat.h>
70
71 #include <vm/seg_kmem.h>
72 #include <vm/as.h>
73 #include <vm/seg.h>
74 #include <vm/hat_pte.h>
75 #include <vm/hat_i86.h>
76
77 #include <sys/procfs.h>
78
79 #include <sys/reboot.h>
80 #include <sys/debug.h>
81 #include <sys/debugreg.h>
82 #include <sys/modctl.h>
83 #include <sys/aio_impl.h>
84 #include <sys/tnf.h>
85 #include <sys/tnf_probe.h>
86 #include <sys/cred.h>
87 #include <sys/mman.h>
88 #include <sys/x86_archext.h>
89 #include <sys/copyops.h>
90 #include <c2/audit.h>
91 #include <sys/ftrace.h>
92 #include <sys/panic.h>
93 #include <sys/traptrace.h>
94 #include <sys/ontrap.h>
95 #include <sys/cpc_impl.h>
96 #include <sys/bootconf.h>
97 #include <sys/bootinfo.h>
98 #include <sys/promif.h>
99 #include <sys/mach_mmu.h>
100 #include <sys/contract/process_impl.h>
101
102 #define USER 0x10000 /* user-mode flag added to trap type */
103
104 static const char *trap_type_mnemonic[] = {
105 "de", "db", "2", "bp",
106 "of", "br", "ud", "nm",
107 "df", "9", "ts", "np",
108 "ss", "gp", "pf", "15",
109 "mf", "ac", "mc", "xf"
110 };
111
112 static const char *trap_type[] = {
113 "Divide error", /* trap id 0 */
114 "Debug", /* trap id 1 */
115 "NMI interrupt", /* trap id 2 */
116 "Breakpoint", /* trap id 3 */
117 "Overflow", /* trap id 4 */
118 "BOUND range exceeded", /* trap id 5 */
119 "Invalid opcode", /* trap id 6 */
120 "Device not available", /* trap id 7 */
121 "Double fault", /* trap id 8 */
122 "Coprocessor segment overrun", /* trap id 9 */
123 "Invalid TSS", /* trap id 10 */
124 "Segment not present", /* trap id 11 */
125 "Stack segment fault", /* trap id 12 */
126 "General protection", /* trap id 13 */
127 "Page fault", /* trap id 14 */
128 "Reserved", /* trap id 15 */
129 "x87 floating point error", /* trap id 16 */
130 "Alignment check", /* trap id 17 */
131 "Machine check", /* trap id 18 */
132 "SIMD floating point exception", /* trap id 19 */
133 };
134
135 #define TRAP_TYPES (sizeof (trap_type) / sizeof (trap_type[0]))
136
137 #define SLOW_SCALL_SIZE 2
138 #define FAST_SCALL_SIZE 2
139
140 int tudebug = 0;
141 int tudebugbpt = 0;
142 int tudebugfpe = 0;
143 int tudebugsse = 0;
144
145 #if defined(TRAPDEBUG) || defined(lint)
146 int tdebug = 0;
147 int lodebug = 0;
148 int faultdebug = 0;
149 #else
150 #define tdebug 0
151 #define lodebug 0
152 #define faultdebug 0
153 #endif /* defined(TRAPDEBUG) || defined(lint) */
154
155 #if defined(TRAPTRACE)
156 /*
157 * trap trace record for cpu0 is allocated here.
158 * trap trace records for non-boot cpus are allocated in mp_startup_init().
159 */
160 static trap_trace_rec_t trap_tr0[TRAPTR_NENT];
161 trap_trace_ctl_t trap_trace_ctl[NCPU] = {
162 {
163 (uintptr_t)trap_tr0, /* next record */
164 (uintptr_t)trap_tr0, /* first record */
165 (uintptr_t)(trap_tr0 + TRAPTR_NENT), /* limit */
166 (uintptr_t)0 /* current */
167 },
168 };
169
170 /*
171 * default trap buffer size
172 */
173 size_t trap_trace_bufsize = TRAPTR_NENT * sizeof (trap_trace_rec_t);
174 int trap_trace_freeze = 0;
175 int trap_trace_off = 0;
176
177 /*
178 * A dummy TRAPTRACE entry to use after death.
179 */
180 trap_trace_rec_t trap_trace_postmort;
181
182 static void dump_ttrace(void);
183 #endif /* TRAPTRACE */
184 static void dumpregs(struct regs *);
185 static void showregs(uint_t, struct regs *, caddr_t);
186 static int kern_gpfault(struct regs *);
187
188 /*ARGSUSED*/
189 static int
190 die(uint_t type, struct regs *rp, caddr_t addr, processorid_t cpuid)
191 {
192 struct panic_trap_info ti;
193 const char *trap_name, *trap_mnemonic;
194
195 if (type < TRAP_TYPES) {
196 trap_name = trap_type[type];
197 trap_mnemonic = trap_type_mnemonic[type];
198 } else {
199 trap_name = "trap";
200 trap_mnemonic = "-";
201 }
202
203 #ifdef TRAPTRACE
204 TRAPTRACE_FREEZE;
205 #endif
206
207 ti.trap_regs = rp;
208 ti.trap_type = type & ~USER;
209 ti.trap_addr = addr;
210
211 curthread->t_panic_trap = &ti;
212
213 if (type == T_PGFLT && addr < (caddr_t)KERNELBASE) {
214 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p "
215 "occurred in module \"%s\" due to %s",
216 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr,
217 mod_containing_pc((caddr_t)rp->r_pc),
218 addr < (caddr_t)PAGESIZE ?
219 "a NULL pointer dereference" :
220 "an illegal access to a user address");
221 } else
222 panic("BAD TRAP: type=%x (#%s %s) rp=%p addr=%p",
223 type, trap_mnemonic, trap_name, (void *)rp, (void *)addr);
224 return (0);
225 }
226
227 /*
228 * Rewrite the instruction at pc to be an int $T_SYSCALLINT instruction.
229 *
230 * int <vector> is two bytes: 0xCD <vector>
231 */
232
233 static int
234 rewrite_syscall(caddr_t pc)
235 {
236 uchar_t instr[SLOW_SCALL_SIZE] = { 0xCD, T_SYSCALLINT };
237
238 if (uwrite(curthread->t_procp, instr, SLOW_SCALL_SIZE,
239 (uintptr_t)pc) != 0)
240 return (1);
241
242 return (0);
243 }
244
245 /*
246 * Test to see if the instruction at pc is sysenter or syscall. The second
247 * argument should be the x86 feature flag corresponding to the expected
248 * instruction.
249 *
250 * sysenter is two bytes: 0x0F 0x34
251 * syscall is two bytes: 0x0F 0x05
252 * int $T_SYSCALLINT is two bytes: 0xCD 0x91
253 */
254
255 static int
256 instr_is_other_syscall(caddr_t pc, int which)
257 {
258 uchar_t instr[FAST_SCALL_SIZE];
259
260 ASSERT(which == X86FSET_SEP || which == X86FSET_ASYSC || which == 0xCD);
261
262 if (copyin_nowatch(pc, (caddr_t)instr, FAST_SCALL_SIZE) != 0)
263 return (0);
264
265 switch (which) {
266 case X86FSET_SEP:
267 if (instr[0] == 0x0F && instr[1] == 0x34)
268 return (1);
269 break;
270 case X86FSET_ASYSC:
271 if (instr[0] == 0x0F && instr[1] == 0x05)
272 return (1);
273 break;
274 case 0xCD:
275 if (instr[0] == 0xCD && instr[1] == T_SYSCALLINT)
276 return (1);
277 break;
278 }
279
280 return (0);
281 }
282
283 static const char *
284 syscall_insn_string(int syscall_insn)
285 {
286 switch (syscall_insn) {
287 case X86FSET_SEP:
288 return ("sysenter");
289 case X86FSET_ASYSC:
290 return ("syscall");
291 case 0xCD:
292 return ("int");
293 default:
294 return ("Unknown");
295 }
296 }
297
298 static int
299 ldt_rewrite_syscall(struct regs *rp, proc_t *p, int syscall_insn)
300 {
301 caddr_t linearpc;
302 int return_code = 0;
303
304 mutex_enter(&p->p_ldtlock); /* Must be held across linear_pc() */
305
306 if (linear_pc(rp, p, &linearpc) == 0) {
307
308 /*
309 * If another thread beat us here, it already changed
310 * this site to the slower (int) syscall instruction.
311 */
312 if (instr_is_other_syscall(linearpc, 0xCD)) {
313 return_code = 1;
314 } else if (instr_is_other_syscall(linearpc, syscall_insn)) {
315
316 if (rewrite_syscall(linearpc) == 0) {
317 return_code = 1;
318 }
319 #ifdef DEBUG
320 else
321 cmn_err(CE_WARN, "failed to rewrite %s "
322 "instruction in process %d",
323 syscall_insn_string(syscall_insn),
324 p->p_pid);
325 #endif /* DEBUG */
326 }
327 }
328
329 mutex_exit(&p->p_ldtlock); /* Must be held across linear_pc() */
330
331 return (return_code);
332 }
333
334 /*
335 * Test to see if the instruction at pc is a system call instruction.
336 *
337 * The bytes of an lcall instruction used for the syscall trap.
338 * static uchar_t lcall[7] = { 0x9a, 0, 0, 0, 0, 0x7, 0 };
339 * static uchar_t lcallalt[7] = { 0x9a, 0, 0, 0, 0, 0x27, 0 };
340 */
341
342 #define LCALLSIZE 7
343
344 static int
345 instr_is_lcall_syscall(caddr_t pc)
346 {
347 uchar_t instr[LCALLSIZE];
348
349 if (copyin_nowatch(pc, (caddr_t)instr, LCALLSIZE) == 0 &&
350 instr[0] == 0x9a &&
351 instr[1] == 0 &&
352 instr[2] == 0 &&
353 instr[3] == 0 &&
354 instr[4] == 0 &&
355 (instr[5] == 0x7 || instr[5] == 0x27) &&
356 instr[6] == 0)
357 return (1);
358
359 return (0);
360 }
361
362 #ifdef __amd64
363
364 /*
365 * In the first revisions of amd64 CPUs produced by AMD, the LAHF and
366 * SAHF instructions were not implemented in 64-bit mode. Later revisions
367 * did implement these instructions. An extension to the cpuid instruction
368 * was added to check for the capability of executing these instructions
369 * in 64-bit mode.
370 *
371 * Intel originally did not implement these instructions in EM64T either,
372 * but added them in later revisions.
373 *
374 * So, there are different chip revisions by both vendors out there that
375 * may or may not implement these instructions. The easy solution is to
376 * just always emulate these instructions on demand.
377 *
378 * SAHF == store %ah in the lower 8 bits of %rflags (opcode 0x9e)
379 * LAHF == load the lower 8 bits of %rflags into %ah (opcode 0x9f)
380 */
381
382 #define LSAHFSIZE 1
383
384 static int
385 instr_is_lsahf(caddr_t pc, uchar_t *instr)
386 {
387 if (copyin_nowatch(pc, (caddr_t)instr, LSAHFSIZE) == 0 &&
388 (*instr == 0x9e || *instr == 0x9f))
389 return (1);
390 return (0);
391 }
392
393 /*
394 * Emulate the LAHF and SAHF instructions. The reference manuals define
395 * these instructions to always load/store bit 1 as a 1, and bits 3 and 5
396 * as a 0. The other, defined, bits are copied (the PS_ICC bits and PS_P).
397 *
398 * Note that %ah is bits 8-15 of %rax.
399 */
400 static void
401 emulate_lsahf(struct regs *rp, uchar_t instr)
402 {
403 if (instr == 0x9e) {
404 /* sahf. Copy bits from %ah to flags. */
405 rp->r_ps = (rp->r_ps & ~0xff) |
406 ((rp->r_rax >> 8) & PSL_LSAHFMASK) | PS_MB1;
407 } else {
408 /* lahf. Copy bits from flags to %ah. */
409 rp->r_rax = (rp->r_rax & ~0xff00) |
410 (((rp->r_ps & PSL_LSAHFMASK) | PS_MB1) << 8);
411 }
412 rp->r_pc += LSAHFSIZE;
413 }
414 #endif /* __amd64 */
415
416 #ifdef OPTERON_ERRATUM_91
417
418 /*
419 * Test to see if the instruction at pc is a prefetch instruction.
420 *
421 * The first byte of prefetch instructions is always 0x0F.
422 * The second byte is 0x18 for regular prefetch or 0x0D for AMD 3dnow prefetch.
423 * The third byte (ModRM) contains the register field bits (bits 3-5).
424 * These bits must be between 0 and 3 inclusive for regular prefetch and
425 * 0 and 1 inclusive for AMD 3dnow prefetch.
426 *
427 * In 64-bit mode, there may be a one-byte REX prefex (0x40-0x4F).
428 */
429
430 static int
431 cmp_to_prefetch(uchar_t *p)
432 {
433 #ifdef _LP64
434 if ((p[0] & 0xF0) == 0x40) /* 64-bit REX prefix */
435 p++;
436 #endif
437 return ((p[0] == 0x0F && p[1] == 0x18 && ((p[2] >> 3) & 7) <= 3) ||
438 (p[0] == 0x0F && p[1] == 0x0D && ((p[2] >> 3) & 7) <= 1));
439 }
440
441 static int
442 instr_is_prefetch(caddr_t pc)
443 {
444 uchar_t instr[4]; /* optional REX prefix plus 3-byte opcode */
445
446 return (copyin_nowatch(pc, instr, sizeof (instr)) == 0 &&
447 cmp_to_prefetch(instr));
448 }
449
450 #endif /* OPTERON_ERRATUM_91 */
451
452 /*
453 * Called from the trap handler when a processor trap occurs.
454 *
455 * Note: All user-level traps that might call stop() must exit
456 * trap() by 'goto out' or by falling through.
457 * Note Also: trap() is usually called with interrupts enabled, (PS_IE == 1)
458 * however, there are paths that arrive here with PS_IE == 0 so special care
459 * must be taken in those cases.
460 */
461 void
462 trap(struct regs *rp, caddr_t addr, processorid_t cpuid)
463 {
464 kthread_t *ct = curthread;
465 enum seg_rw rw;
466 unsigned type;
467 proc_t *p = ttoproc(ct);
468 klwp_t *lwp = ttolwp(ct);
469 uintptr_t lofault;
470 label_t *onfault;
471 faultcode_t pagefault(), res, errcode;
472 enum fault_type fault_type;
473 k_siginfo_t siginfo;
474 uint_t fault = 0;
475 int mstate;
476 int sicode = 0;
477 int watchcode;
478 int watchpage;
479 caddr_t vaddr;
480 int singlestep_twiddle;
481 size_t sz;
482 int ta;
483 #ifdef __amd64
484 uchar_t instr;
485 #endif
486
487 ASSERT_STACK_ALIGNED();
488
489 type = rp->r_trapno;
490 CPU_STATS_ADDQ(CPU, sys, trap, 1);
491
492 if (type == T_PGFLT) {
493
494 errcode = rp->r_err;
495 if (errcode & PF_ERR_WRITE)
496 rw = S_WRITE;
497 else if ((caddr_t)rp->r_pc == addr ||
498 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC)))
499 rw = S_EXEC;
500 else
501 rw = S_READ;
502
503 #if defined(__i386)
504 /*
505 * Pentium Pro work-around
506 */
507 if ((errcode & PF_ERR_PROT) && pentiumpro_bug4046376) {
508 uint_t attr;
509 uint_t priv_violation;
510 uint_t access_violation;
511
512 if (hat_getattr(addr < (caddr_t)kernelbase ?
513 curproc->p_as->a_hat : kas.a_hat, addr, &attr)
514 == -1) {
515 errcode &= ~PF_ERR_PROT;
516 } else {
517 priv_violation = (errcode & PF_ERR_USER) &&
518 !(attr & PROT_USER);
519 access_violation = (errcode & PF_ERR_WRITE) &&
520 !(attr & PROT_WRITE);
521 if (!priv_violation && !access_violation)
522 goto cleanup;
523 }
524 }
525 #endif /* __i386 */
526
527 } else if (type == T_SGLSTP && lwp != NULL)
528 lwp->lwp_pcb.pcb_drstat = (uintptr_t)addr;
529
530 if (tdebug)
531 showregs(type, rp, addr);
532
533 if (USERMODE(rp->r_cs)) {
534 /*
535 * Set up the current cred to use during this trap. u_cred
536 * no longer exists. t_cred is used instead.
537 * The current process credential applies to the thread for
538 * the entire trap. If trapping from the kernel, this
539 * should already be set up.
540 */
541 if (ct->t_cred != p->p_cred) {
542 cred_t *oldcred = ct->t_cred;
543 /*
544 * DTrace accesses t_cred in probe context. t_cred
545 * must always be either NULL, or point to a valid,
546 * allocated cred structure.
547 */
548 ct->t_cred = crgetcred();
549 crfree(oldcred);
550 }
551 ASSERT(lwp != NULL);
552 type |= USER;
553 ASSERT(lwptoregs(lwp) == rp);
554 lwp->lwp_state = LWP_SYS;
555
556 switch (type) {
557 case T_PGFLT + USER:
558 if ((caddr_t)rp->r_pc == addr)
559 mstate = LMS_TFAULT;
560 else
561 mstate = LMS_DFAULT;
562 break;
563 default:
564 mstate = LMS_TRAP;
565 break;
566 }
567
568 mstate = new_mstate(ct, mstate);
569
570 bzero(&siginfo, sizeof (siginfo));
571 }
572
573 switch (type) {
574 case T_PGFLT + USER:
575 case T_SGLSTP:
576 case T_SGLSTP + USER:
577 case T_BPTFLT + USER:
578 break;
579
580 default:
581 FTRACE_2("trap(): type=0x%lx, regs=0x%lx",
582 (ulong_t)type, (ulong_t)rp);
583 break;
584 }
585
586 switch (type) {
587 case T_SIMDFPE:
588 /* Make sure we enable interrupts before die()ing */
589 sti(); /* The SIMD exception comes in via cmninttrap */
590 /*FALLTHROUGH*/
591 default:
592 if (type & USER) {
593 if (tudebug)
594 showregs(type, rp, (caddr_t)0);
595 printf("trap: Unknown trap type %d in user mode\n",
596 type & ~USER);
597 siginfo.si_signo = SIGILL;
598 siginfo.si_code = ILL_ILLTRP;
599 siginfo.si_addr = (caddr_t)rp->r_pc;
600 siginfo.si_trapno = type & ~USER;
601 fault = FLTILL;
602 break;
603 } else {
604 (void) die(type, rp, addr, cpuid);
605 /*NOTREACHED*/
606 }
607
608 case T_PGFLT: /* system page fault */
609 /*
610 * If we're under on_trap() protection (see <sys/ontrap.h>),
611 * set ot_trap and bounce back to the on_trap() call site
612 * via the installed trampoline.
613 */
614 if ((ct->t_ontrap != NULL) &&
615 (ct->t_ontrap->ot_prot & OT_DATA_ACCESS)) {
616 ct->t_ontrap->ot_trap |= OT_DATA_ACCESS;
617 rp->r_pc = ct->t_ontrap->ot_trampoline;
618 goto cleanup;
619 }
620
621 /*
622 * If we have an Instruction fault in kernel mode, then that
623 * means we've tried to execute a user page (SMEP) or both of
624 * PAE and NXE are enabled. In either case, given that it's a
625 * kernel fault, we should panic immediately and not try to make
626 * any more forward progress. This indicates a bug in the
627 * kernel, which if execution continued, could be exploited to
628 * wreak havoc on the system.
629 */
630 if (errcode & PF_ERR_EXEC) {
631 (void) die(type, rp, addr, cpuid);
632 }
633
634 /*
635 * We need to check if SMAP is in play. If SMAP is in play, then
636 * any access to a user page will show up as a protection
637 * violation. To see if SMAP is enabled we first check if it's a
638 * user address and whether we have the feature flag set. If we
639 * do and the interrupted registers do not allow for user
640 * accesses (PS_ACHK is not enabled), then we need to die
641 * immediately.
642 */
643 if (addr < (caddr_t)kernelbase &&
644 is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE &&
645 (rp->r_ps & PS_ACHK) == 0) {
646 (void) die(type, rp, addr, cpuid);
647 }
648
649 /*
650 * See if we can handle as pagefault. Save lofault and onfault
651 * across this. Here we assume that an address less than
652 * KERNELBASE is a user fault. We can do this as copy.s
653 * routines verify that the starting address is less than
654 * KERNELBASE before starting and because we know that we
655 * always have KERNELBASE mapped as invalid to serve as a
656 * "barrier".
657 */
658 lofault = ct->t_lofault;
659 onfault = ct->t_onfault;
660 ct->t_lofault = 0;
661
662 mstate = new_mstate(ct, LMS_KFAULT);
663
664 if (addr < (caddr_t)kernelbase) {
665 res = pagefault(addr,
666 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 0);
667 if (res == FC_NOMAP &&
668 addr < p->p_usrstack &&
669 grow(addr))
670 res = 0;
671 } else {
672 res = pagefault(addr,
673 (errcode & PF_ERR_PROT)? F_PROT: F_INVAL, rw, 1);
674 }
675 (void) new_mstate(ct, mstate);
676
677 /*
678 * Restore lofault and onfault. If we resolved the fault, exit.
679 * If we didn't and lofault wasn't set, die.
680 */
681 ct->t_lofault = lofault;
682 ct->t_onfault = onfault;
683 if (res == 0)
684 goto cleanup;
685
686 #if defined(OPTERON_ERRATUM_93) && defined(_LP64)
687 if (lofault == 0 && opteron_erratum_93) {
688 /*
689 * Workaround for Opteron Erratum 93. On return from
690 * a System Managment Interrupt at a HLT instruction
691 * the %rip might be truncated to a 32 bit value.
692 * BIOS is supposed to fix this, but some don't.
693 * If this occurs we simply restore the high order bits.
694 * The HLT instruction is 1 byte of 0xf4.
695 */
696 uintptr_t rip = rp->r_pc;
697
698 if ((rip & 0xfffffffful) == rip) {
699 rip |= 0xfffffffful << 32;
700 if (hat_getpfnum(kas.a_hat, (caddr_t)rip) !=
701 PFN_INVALID &&
702 (*(uchar_t *)rip == 0xf4 ||
703 *(uchar_t *)(rip - 1) == 0xf4)) {
704 rp->r_pc = rip;
705 goto cleanup;
706 }
707 }
708 }
709 #endif /* OPTERON_ERRATUM_93 && _LP64 */
710
711 #ifdef OPTERON_ERRATUM_91
712 if (lofault == 0 && opteron_erratum_91) {
713 /*
714 * Workaround for Opteron Erratum 91. Prefetches may
715 * generate a page fault (they're not supposed to do
716 * that!). If this occurs we simply return back to the
717 * instruction.
718 */
719 caddr_t pc = (caddr_t)rp->r_pc;
720
721 /*
722 * If the faulting PC is not mapped, this is a
723 * legitimate kernel page fault that must result in a
724 * panic. If the faulting PC is mapped, it could contain
725 * a prefetch instruction. Check for that here.
726 */
727 if (hat_getpfnum(kas.a_hat, pc) != PFN_INVALID) {
728 if (cmp_to_prefetch((uchar_t *)pc)) {
729 #ifdef DEBUG
730 cmn_err(CE_WARN, "Opteron erratum 91 "
731 "occurred: kernel prefetch"
732 " at %p generated a page fault!",
733 (void *)rp->r_pc);
734 #endif /* DEBUG */
735 goto cleanup;
736 }
737 }
738 (void) die(type, rp, addr, cpuid);
739 }
740 #endif /* OPTERON_ERRATUM_91 */
741
742 if (lofault == 0)
743 (void) die(type, rp, addr, cpuid);
744
745 /*
746 * Cannot resolve fault. Return to lofault.
747 */
748 if (lodebug) {
749 showregs(type, rp, addr);
750 traceregs(rp);
751 }
752 if (FC_CODE(res) == FC_OBJERR)
753 res = FC_ERRNO(res);
754 else
755 res = EFAULT;
756 rp->r_r0 = res;
757 rp->r_pc = ct->t_lofault;
758 goto cleanup;
759
760 case T_PGFLT + USER: /* user page fault */
761 if (faultdebug) {
762 char *fault_str;
763
764 switch (rw) {
765 case S_READ:
766 fault_str = "read";
767 break;
768 case S_WRITE:
769 fault_str = "write";
770 break;
771 case S_EXEC:
772 fault_str = "exec";
773 break;
774 default:
775 fault_str = "";
776 break;
777 }
778 printf("user %s fault: addr=0x%lx errcode=0x%x\n",
779 fault_str, (uintptr_t)addr, errcode);
780 }
781
782 #if defined(OPTERON_ERRATUM_100) && defined(_LP64)
783 /*
784 * Workaround for AMD erratum 100
785 *
786 * A 32-bit process may receive a page fault on a non
787 * 32-bit address by mistake. The range of the faulting
788 * address will be
789 *
790 * 0xffffffff80000000 .. 0xffffffffffffffff or
791 * 0x0000000100000000 .. 0x000000017fffffff
792 *
793 * The fault is always due to an instruction fetch, however
794 * the value of r_pc should be correct (in 32 bit range),
795 * so we ignore the page fault on the bogus address.
796 */
797 if (p->p_model == DATAMODEL_ILP32 &&
798 (0xffffffff80000000 <= (uintptr_t)addr ||
799 (0x100000000 <= (uintptr_t)addr &&
800 (uintptr_t)addr <= 0x17fffffff))) {
801 if (!opteron_erratum_100)
802 panic("unexpected erratum #100");
803 if (rp->r_pc <= 0xffffffff)
804 goto out;
805 }
806 #endif /* OPTERON_ERRATUM_100 && _LP64 */
807
808 ASSERT(!(curthread->t_flag & T_WATCHPT));
809 watchpage = (pr_watch_active(p) && pr_is_watchpage(addr, rw));
810 #ifdef __i386
811 /*
812 * In 32-bit mode, the lcall (system call) instruction fetches
813 * one word from the stack, at the stack pointer, because of the
814 * way the call gate is constructed. This is a bogus
815 * read and should not be counted as a read watchpoint.
816 * We work around the problem here by testing to see if
817 * this situation applies and, if so, simply jumping to
818 * the code in locore.s that fields the system call trap.
819 * The registers on the stack are already set up properly
820 * due to the match between the call gate sequence and the
821 * trap gate sequence. We just have to adjust the pc.
822 */
823 if (watchpage && addr == (caddr_t)rp->r_sp &&
824 rw == S_READ && instr_is_lcall_syscall((caddr_t)rp->r_pc)) {
825 extern void watch_syscall(void);
826
827 rp->r_pc += LCALLSIZE;
828 watch_syscall(); /* never returns */
829 /* NOTREACHED */
830 }
831 #endif /* __i386 */
832 vaddr = addr;
833 if (!watchpage || (sz = instr_size(rp, &vaddr, rw)) <= 0)
834 fault_type = (errcode & PF_ERR_PROT)? F_PROT: F_INVAL;
835 else if ((watchcode = pr_is_watchpoint(&vaddr, &ta,
836 sz, NULL, rw)) != 0) {
837 if (ta) {
838 do_watch_step(vaddr, sz, rw,
839 watchcode, rp->r_pc);
840 fault_type = F_INVAL;
841 } else {
842 bzero(&siginfo, sizeof (siginfo));
843 siginfo.si_signo = SIGTRAP;
844 siginfo.si_code = watchcode;
845 siginfo.si_addr = vaddr;
846 siginfo.si_trapafter = 0;
847 siginfo.si_pc = (caddr_t)rp->r_pc;
848 fault = FLTWATCH;
849 break;
850 }
851 } else {
852 /* XXX pr_watch_emul() never succeeds (for now) */
853 if (rw != S_EXEC && pr_watch_emul(rp, vaddr, rw))
854 goto out;
855 do_watch_step(vaddr, sz, rw, 0, 0);
856 fault_type = F_INVAL;
857 }
858
859 res = pagefault(addr, fault_type, rw, 0);
860
861 /*
862 * If pagefault() succeeded, ok.
863 * Otherwise attempt to grow the stack.
864 */
865 if (res == 0 ||
866 (res == FC_NOMAP &&
867 addr < p->p_usrstack &&
868 grow(addr))) {
869 lwp->lwp_lastfault = FLTPAGE;
870 lwp->lwp_lastfaddr = addr;
871 if (prismember(&p->p_fltmask, FLTPAGE)) {
872 bzero(&siginfo, sizeof (siginfo));
873 siginfo.si_addr = addr;
874 (void) stop_on_fault(FLTPAGE, &siginfo);
875 }
876 goto out;
877 } else if (res == FC_PROT && addr < p->p_usrstack &&
878 (mmu.pt_nx != 0 && (errcode & PF_ERR_EXEC))) {
879 report_stack_exec(p, addr);
880 }
881
882 #ifdef OPTERON_ERRATUM_91
883 /*
884 * Workaround for Opteron Erratum 91. Prefetches may generate a
885 * page fault (they're not supposed to do that!). If this
886 * occurs we simply return back to the instruction.
887 *
888 * We rely on copyin to properly fault in the page with r_pc.
889 */
890 if (opteron_erratum_91 &&
891 addr != (caddr_t)rp->r_pc &&
892 instr_is_prefetch((caddr_t)rp->r_pc)) {
893 #ifdef DEBUG
894 cmn_err(CE_WARN, "Opteron erratum 91 occurred: "
895 "prefetch at %p in pid %d generated a trap!",
896 (void *)rp->r_pc, p->p_pid);
897 #endif /* DEBUG */
898 goto out;
899 }
900 #endif /* OPTERON_ERRATUM_91 */
901
902 if (tudebug)
903 showregs(type, rp, addr);
904 /*
905 * In the case where both pagefault and grow fail,
906 * set the code to the value provided by pagefault.
907 * We map all errors returned from pagefault() to SIGSEGV.
908 */
909 bzero(&siginfo, sizeof (siginfo));
910 siginfo.si_addr = addr;
911 switch (FC_CODE(res)) {
912 case FC_HWERR:
913 case FC_NOSUPPORT:
914 siginfo.si_signo = SIGBUS;
915 siginfo.si_code = BUS_ADRERR;
916 fault = FLTACCESS;
917 break;
918 case FC_ALIGN:
919 siginfo.si_signo = SIGBUS;
920 siginfo.si_code = BUS_ADRALN;
921 fault = FLTACCESS;
922 break;
923 case FC_OBJERR:
924 if ((siginfo.si_errno = FC_ERRNO(res)) != EINTR) {
925 siginfo.si_signo = SIGBUS;
926 siginfo.si_code = BUS_OBJERR;
927 fault = FLTACCESS;
928 }
929 break;
930 default: /* FC_NOMAP or FC_PROT */
931 siginfo.si_signo = SIGSEGV;
932 siginfo.si_code =
933 (res == FC_NOMAP)? SEGV_MAPERR : SEGV_ACCERR;
934 fault = FLTBOUNDS;
935 break;
936 }
937 break;
938
939 case T_ILLINST + USER: /* invalid opcode fault */
940 /*
941 * If the syscall instruction is disabled due to LDT usage, a
942 * user program that attempts to execute it will trigger a #ud
943 * trap. Check for that case here. If this occurs on a CPU which
944 * doesn't even support syscall, the result of all of this will
945 * be to emulate that particular instruction.
946 */
947 if (p->p_ldt != NULL &&
948 ldt_rewrite_syscall(rp, p, X86FSET_ASYSC))
949 goto out;
950
951 #ifdef __amd64
952 /*
953 * Emulate the LAHF and SAHF instructions if needed.
954 * See the instr_is_lsahf function for details.
955 */
956 if (p->p_model == DATAMODEL_LP64 &&
957 instr_is_lsahf((caddr_t)rp->r_pc, &instr)) {
958 emulate_lsahf(rp, instr);
959 goto out;
960 }
961 #endif
962
963 /*FALLTHROUGH*/
964
965 if (tudebug)
966 showregs(type, rp, (caddr_t)0);
967 siginfo.si_signo = SIGILL;
968 siginfo.si_code = ILL_ILLOPC;
969 siginfo.si_addr = (caddr_t)rp->r_pc;
970 fault = FLTILL;
971 break;
972
973 case T_ZERODIV + USER: /* integer divide by zero */
974 if (tudebug && tudebugfpe)
975 showregs(type, rp, (caddr_t)0);
976 siginfo.si_signo = SIGFPE;
977 siginfo.si_code = FPE_INTDIV;
978 siginfo.si_addr = (caddr_t)rp->r_pc;
979 fault = FLTIZDIV;
980 break;
981
982 case T_OVFLW + USER: /* integer overflow */
983 if (tudebug && tudebugfpe)
984 showregs(type, rp, (caddr_t)0);
985 siginfo.si_signo = SIGFPE;
986 siginfo.si_code = FPE_INTOVF;
987 siginfo.si_addr = (caddr_t)rp->r_pc;
988 fault = FLTIOVF;
989 break;
990
991 case T_NOEXTFLT + USER: /* math coprocessor not available */
992 if (tudebug && tudebugfpe)
993 showregs(type, rp, addr);
994 if (fpnoextflt(rp)) {
995 siginfo.si_signo = SIGILL;
996 siginfo.si_code = ILL_ILLOPC;
997 siginfo.si_addr = (caddr_t)rp->r_pc;
998 fault = FLTILL;
999 }
1000 break;
1001
1002 case T_EXTOVRFLT: /* extension overrun fault */
1003 /* check if we took a kernel trap on behalf of user */
1004 {
1005 extern void ndptrap_frstor(void);
1006 if (rp->r_pc != (uintptr_t)ndptrap_frstor) {
1007 sti(); /* T_EXTOVRFLT comes in via cmninttrap */
1008 (void) die(type, rp, addr, cpuid);
1009 }
1010 type |= USER;
1011 }
1012 /*FALLTHROUGH*/
1013 case T_EXTOVRFLT + USER: /* extension overrun fault */
1014 if (tudebug && tudebugfpe)
1015 showregs(type, rp, addr);
1016 if (fpextovrflt(rp)) {
1017 siginfo.si_signo = SIGSEGV;
1018 siginfo.si_code = SEGV_MAPERR;
1019 siginfo.si_addr = (caddr_t)rp->r_pc;
1020 fault = FLTBOUNDS;
1021 }
1022 break;
1023
1024 case T_EXTERRFLT: /* x87 floating point exception pending */
1025 /* check if we took a kernel trap on behalf of user */
1026 {
1027 extern void ndptrap_frstor(void);
1028 if (rp->r_pc != (uintptr_t)ndptrap_frstor) {
1029 sti(); /* T_EXTERRFLT comes in via cmninttrap */
1030 (void) die(type, rp, addr, cpuid);
1031 }
1032 type |= USER;
1033 }
1034 /*FALLTHROUGH*/
1035
1036 case T_EXTERRFLT + USER: /* x87 floating point exception pending */
1037 if (tudebug && tudebugfpe)
1038 showregs(type, rp, addr);
1039 if (sicode = fpexterrflt(rp)) {
1040 siginfo.si_signo = SIGFPE;
1041 siginfo.si_code = sicode;
1042 siginfo.si_addr = (caddr_t)rp->r_pc;
1043 fault = FLTFPE;
1044 }
1045 break;
1046
1047 case T_SIMDFPE + USER: /* SSE and SSE2 exceptions */
1048 if (tudebug && tudebugsse)
1049 showregs(type, rp, addr);
1050 if (!is_x86_feature(x86_featureset, X86FSET_SSE) &&
1051 !is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1052 /*
1053 * There are rumours that some user instructions
1054 * on older CPUs can cause this trap to occur; in
1055 * which case send a SIGILL instead of a SIGFPE.
1056 */
1057 siginfo.si_signo = SIGILL;
1058 siginfo.si_code = ILL_ILLTRP;
1059 siginfo.si_addr = (caddr_t)rp->r_pc;
1060 siginfo.si_trapno = type & ~USER;
1061 fault = FLTILL;
1062 } else if ((sicode = fpsimderrflt(rp)) != 0) {
1063 siginfo.si_signo = SIGFPE;
1064 siginfo.si_code = sicode;
1065 siginfo.si_addr = (caddr_t)rp->r_pc;
1066 fault = FLTFPE;
1067 }
1068
1069 sti(); /* The SIMD exception comes in via cmninttrap */
1070 break;
1071
1072 case T_BPTFLT: /* breakpoint trap */
1073 /*
1074 * Kernel breakpoint traps should only happen when kmdb is
1075 * active, and even then, it'll have interposed on the IDT, so
1076 * control won't get here. If it does, we've hit a breakpoint
1077 * without the debugger, which is very strange, and very
1078 * fatal.
1079 */
1080 if (tudebug && tudebugbpt)
1081 showregs(type, rp, (caddr_t)0);
1082
1083 (void) die(type, rp, addr, cpuid);
1084 break;
1085
1086 case T_SGLSTP: /* single step/hw breakpoint exception */
1087
1088 /* Now evaluate how we got here */
1089 if (lwp != NULL && (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP)) {
1090 /*
1091 * i386 single-steps even through lcalls which
1092 * change the privilege level. So we take a trap at
1093 * the first instruction in privileged mode.
1094 *
1095 * Set a flag to indicate that upon completion of
1096 * the system call, deal with the single-step trap.
1097 *
1098 * The same thing happens for sysenter, too.
1099 */
1100 singlestep_twiddle = 0;
1101 if (rp->r_pc == (uintptr_t)sys_sysenter ||
1102 rp->r_pc == (uintptr_t)brand_sys_sysenter) {
1103 singlestep_twiddle = 1;
1104 #if defined(__amd64)
1105 /*
1106 * Since we are already on the kernel's
1107 * %gs, on 64-bit systems the sysenter case
1108 * needs to adjust the pc to avoid
1109 * executing the swapgs instruction at the
1110 * top of the handler.
1111 */
1112 if (rp->r_pc == (uintptr_t)sys_sysenter)
1113 rp->r_pc = (uintptr_t)
1114 _sys_sysenter_post_swapgs;
1115 else
1116 rp->r_pc = (uintptr_t)
1117 _brand_sys_sysenter_post_swapgs;
1118 #endif
1119 }
1120 #if defined(__i386)
1121 else if (rp->r_pc == (uintptr_t)sys_call ||
1122 rp->r_pc == (uintptr_t)brand_sys_call) {
1123 singlestep_twiddle = 1;
1124 }
1125 #endif
1126 else {
1127 /* not on sysenter/syscall; uregs available */
1128 if (tudebug && tudebugbpt)
1129 showregs(type, rp, (caddr_t)0);
1130 }
1131 if (singlestep_twiddle) {
1132 rp->r_ps &= ~PS_T; /* turn off trace */
1133 lwp->lwp_pcb.pcb_flags |= DEBUG_PENDING;
1134 ct->t_post_sys = 1;
1135 aston(curthread);
1136 goto cleanup;
1137 }
1138 }
1139 /* XXX - needs review on debugger interface? */
1140 if (boothowto & RB_DEBUG)
1141 debug_enter(NULL);
1142 else
1143 (void) die(type, rp, addr, cpuid);
1144 break;
1145
1146 case T_NMIFLT: /* NMI interrupt */
1147 printf("Unexpected NMI in system mode\n");
1148 goto cleanup;
1149
1150 case T_NMIFLT + USER: /* NMI interrupt */
1151 printf("Unexpected NMI in user mode\n");
1152 break;
1153
1154 case T_GPFLT: /* general protection violation */
1155 /*
1156 * Any #GP that occurs during an on_trap .. no_trap bracket
1157 * with OT_DATA_ACCESS or OT_SEGMENT_ACCESS protection,
1158 * or in a on_fault .. no_fault bracket, is forgiven
1159 * and we trampoline. This protection is given regardless
1160 * of whether we are 32/64 bit etc - if a distinction is
1161 * required then define new on_trap protection types.
1162 *
1163 * On amd64, we can get a #gp from referencing addresses
1164 * in the virtual address hole e.g. from a copyin or in
1165 * update_sregs while updating user segment registers.
1166 *
1167 * On the 32-bit hypervisor we could also generate one in
1168 * mfn_to_pfn by reaching around or into where the hypervisor
1169 * lives which is protected by segmentation.
1170 */
1171
1172 /*
1173 * If we're under on_trap() protection (see <sys/ontrap.h>),
1174 * set ot_trap and trampoline back to the on_trap() call site
1175 * for OT_DATA_ACCESS or OT_SEGMENT_ACCESS.
1176 */
1177 if (ct->t_ontrap != NULL) {
1178 int ttype = ct->t_ontrap->ot_prot &
1179 (OT_DATA_ACCESS | OT_SEGMENT_ACCESS);
1180
1181 if (ttype != 0) {
1182 ct->t_ontrap->ot_trap |= ttype;
1183 if (tudebug)
1184 showregs(type, rp, (caddr_t)0);
1185 rp->r_pc = ct->t_ontrap->ot_trampoline;
1186 goto cleanup;
1187 }
1188 }
1189
1190 /*
1191 * If we're under lofault protection (copyin etc.),
1192 * longjmp back to lofault with an EFAULT.
1193 */
1194 if (ct->t_lofault) {
1195 /*
1196 * Fault is not resolvable, so just return to lofault
1197 */
1198 if (lodebug) {
1199 showregs(type, rp, addr);
1200 traceregs(rp);
1201 }
1202 rp->r_r0 = EFAULT;
1203 rp->r_pc = ct->t_lofault;
1204 goto cleanup;
1205 }
1206
1207 /*
1208 * We fall through to the next case, which repeats
1209 * the OT_SEGMENT_ACCESS check which we've already
1210 * done, so we'll always fall through to the
1211 * T_STKFLT case.
1212 */
1213 /*FALLTHROUGH*/
1214 case T_SEGFLT: /* segment not present fault */
1215 /*
1216 * One example of this is #NP in update_sregs while
1217 * attempting to update a user segment register
1218 * that points to a descriptor that is marked not
1219 * present.
1220 */
1221 if (ct->t_ontrap != NULL &&
1222 ct->t_ontrap->ot_prot & OT_SEGMENT_ACCESS) {
1223 ct->t_ontrap->ot_trap |= OT_SEGMENT_ACCESS;
1224 if (tudebug)
1225 showregs(type, rp, (caddr_t)0);
1226 rp->r_pc = ct->t_ontrap->ot_trampoline;
1227 goto cleanup;
1228 }
1229 /*FALLTHROUGH*/
1230 case T_STKFLT: /* stack fault */
1231 case T_TSSFLT: /* invalid TSS fault */
1232 if (tudebug)
1233 showregs(type, rp, (caddr_t)0);
1234 if (kern_gpfault(rp))
1235 (void) die(type, rp, addr, cpuid);
1236 goto cleanup;
1237
1238 /*
1239 * ONLY 32-bit PROCESSES can USE a PRIVATE LDT! 64-bit apps
1240 * should have no need for them, so we put a stop to it here.
1241 *
1242 * So: not-present fault is ONLY valid for 32-bit processes with
1243 * a private LDT trying to do a system call. Emulate it.
1244 *
1245 * #gp fault is ONLY valid for 32-bit processes also, which DO NOT
1246 * have a private LDT, and are trying to do a system call. Emulate it.
1247 */
1248
1249 case T_SEGFLT + USER: /* segment not present fault */
1250 case T_GPFLT + USER: /* general protection violation */
1251 #ifdef _SYSCALL32_IMPL
1252 if (p->p_model != DATAMODEL_NATIVE) {
1253 #endif /* _SYSCALL32_IMPL */
1254 if (instr_is_lcall_syscall((caddr_t)rp->r_pc)) {
1255 if (type == T_SEGFLT + USER)
1256 ASSERT(p->p_ldt != NULL);
1257
1258 if ((p->p_ldt == NULL && type == T_GPFLT + USER) ||
1259 type == T_SEGFLT + USER) {
1260
1261 /*
1262 * The user attempted a system call via the obsolete
1263 * call gate mechanism. Because the process doesn't have
1264 * an LDT (i.e. the ldtr contains 0), a #gp results.
1265 * Emulate the syscall here, just as we do above for a
1266 * #np trap.
1267 */
1268
1269 /*
1270 * Since this is a not-present trap, rp->r_pc points to
1271 * the trapping lcall instruction. We need to bump it
1272 * to the next insn so the app can continue on.
1273 */
1274 rp->r_pc += LCALLSIZE;
1275 lwp->lwp_regs = rp;
1276
1277 /*
1278 * Normally the microstate of the LWP is forced back to
1279 * LMS_USER by the syscall handlers. Emulate that
1280 * behavior here.
1281 */
1282 mstate = LMS_USER;
1283
1284 dosyscall();
1285 goto out;
1286 }
1287 }
1288 #ifdef _SYSCALL32_IMPL
1289 }
1290 #endif /* _SYSCALL32_IMPL */
1291 /*
1292 * If the current process is using a private LDT and the
1293 * trapping instruction is sysenter, the sysenter instruction
1294 * has been disabled on the CPU because it destroys segment
1295 * registers. If this is the case, rewrite the instruction to
1296 * be a safe system call and retry it. If this occurs on a CPU
1297 * which doesn't even support sysenter, the result of all of
1298 * this will be to emulate that particular instruction.
1299 */
1300 if (p->p_ldt != NULL &&
1301 ldt_rewrite_syscall(rp, p, X86FSET_SEP))
1302 goto out;
1303
1304 /*FALLTHROUGH*/
1305
1306 case T_BOUNDFLT + USER: /* bound fault */
1307 case T_STKFLT + USER: /* stack fault */
1308 case T_TSSFLT + USER: /* invalid TSS fault */
1309 if (tudebug)
1310 showregs(type, rp, (caddr_t)0);
1311 siginfo.si_signo = SIGSEGV;
1312 siginfo.si_code = SEGV_MAPERR;
1313 siginfo.si_addr = (caddr_t)rp->r_pc;
1314 fault = FLTBOUNDS;
1315 break;
1316
1317 case T_ALIGNMENT + USER: /* user alignment error (486) */
1318 if (tudebug)
1319 showregs(type, rp, (caddr_t)0);
1320 bzero(&siginfo, sizeof (siginfo));
1321 siginfo.si_signo = SIGBUS;
1322 siginfo.si_code = BUS_ADRALN;
1323 siginfo.si_addr = (caddr_t)rp->r_pc;
1324 fault = FLTACCESS;
1325 break;
1326
1327 case T_SGLSTP + USER: /* single step/hw breakpoint exception */
1328 if (tudebug && tudebugbpt)
1329 showregs(type, rp, (caddr_t)0);
1330
1331 /* Was it single-stepping? */
1332 if (lwp->lwp_pcb.pcb_drstat & DR_SINGLESTEP) {
1333 pcb_t *pcb = &lwp->lwp_pcb;
1334
1335 rp->r_ps &= ~PS_T;
1336 /*
1337 * If both NORMAL_STEP and WATCH_STEP are in effect,
1338 * give precedence to WATCH_STEP. If neither is set,
1339 * user must have set the PS_T bit in %efl; treat this
1340 * as NORMAL_STEP.
1341 */
1342 if ((fault = undo_watch_step(&siginfo)) == 0 &&
1343 ((pcb->pcb_flags & NORMAL_STEP) ||
1344 !(pcb->pcb_flags & WATCH_STEP))) {
1345 siginfo.si_signo = SIGTRAP;
1346 siginfo.si_code = TRAP_TRACE;
1347 siginfo.si_addr = (caddr_t)rp->r_pc;
1348 fault = FLTTRACE;
1349 }
1350 pcb->pcb_flags &= ~(NORMAL_STEP|WATCH_STEP);
1351 }
1352 break;
1353
1354 case T_BPTFLT + USER: /* breakpoint trap */
1355 if (tudebug && tudebugbpt)
1356 showregs(type, rp, (caddr_t)0);
1357 /*
1358 * int 3 (the breakpoint instruction) leaves the pc referring
1359 * to the address one byte after the breakpointed address.
1360 * If the P_PR_BPTADJ flag has been set via /proc, We adjust
1361 * it back so it refers to the breakpointed address.
1362 */
1363 if (p->p_proc_flag & P_PR_BPTADJ)
1364 rp->r_pc--;
1365 siginfo.si_signo = SIGTRAP;
1366 siginfo.si_code = TRAP_BRKPT;
1367 siginfo.si_addr = (caddr_t)rp->r_pc;
1368 fault = FLTBPT;
1369 break;
1370
1371 case T_AST:
1372 /*
1373 * This occurs only after the cs register has been made to
1374 * look like a kernel selector, either through debugging or
1375 * possibly by functions like setcontext(). The thread is
1376 * about to cause a general protection fault at common_iret()
1377 * in locore. We let that happen immediately instead of
1378 * doing the T_AST processing.
1379 */
1380 goto cleanup;
1381
1382 case T_AST + USER: /* profiling, resched, h/w error pseudo trap */
1383 if (lwp->lwp_pcb.pcb_flags & ASYNC_HWERR) {
1384 proc_t *p = ttoproc(curthread);
1385 extern void print_msg_hwerr(ctid_t ct_id, proc_t *p);
1386
1387 lwp->lwp_pcb.pcb_flags &= ~ASYNC_HWERR;
1388 print_msg_hwerr(p->p_ct_process->conp_contract.ct_id,
1389 p);
1390 contract_process_hwerr(p->p_ct_process, p);
1391 siginfo.si_signo = SIGKILL;
1392 siginfo.si_code = SI_NOINFO;
1393 } else if (lwp->lwp_pcb.pcb_flags & CPC_OVERFLOW) {
1394 lwp->lwp_pcb.pcb_flags &= ~CPC_OVERFLOW;
1395 if (kcpc_overflow_ast()) {
1396 /*
1397 * Signal performance counter overflow
1398 */
1399 if (tudebug)
1400 showregs(type, rp, (caddr_t)0);
1401 bzero(&siginfo, sizeof (siginfo));
1402 siginfo.si_signo = SIGEMT;
1403 siginfo.si_code = EMT_CPCOVF;
1404 siginfo.si_addr = (caddr_t)rp->r_pc;
1405 fault = FLTCPCOVF;
1406 }
1407 }
1408
1409 break;
1410 }
1411
1412 /*
1413 * We can't get here from a system trap
1414 */
1415 ASSERT(type & USER);
1416
1417 if (fault) {
1418 /* We took a fault so abort single step. */
1419 lwp->lwp_pcb.pcb_flags &= ~(NORMAL_STEP|WATCH_STEP);
1420 /*
1421 * Remember the fault and fault adddress
1422 * for real-time (SIGPROF) profiling.
1423 */
1424 lwp->lwp_lastfault = fault;
1425 lwp->lwp_lastfaddr = siginfo.si_addr;
1426
1427 DTRACE_PROC2(fault, int, fault, ksiginfo_t *, &siginfo);
1428
1429 /*
1430 * If a debugger has declared this fault to be an
1431 * event of interest, stop the lwp. Otherwise just
1432 * deliver the associated signal.
1433 */
1434 if (siginfo.si_signo != SIGKILL &&
1435 prismember(&p->p_fltmask, fault) &&
1436 stop_on_fault(fault, &siginfo) == 0)
1437 siginfo.si_signo = 0;
1438 }
1439
1440 if (siginfo.si_signo)
1441 trapsig(&siginfo, (fault != FLTFPE && fault != FLTCPCOVF));
1442
1443 if (lwp->lwp_oweupc)
1444 profil_tick(rp->r_pc);
1445
1446 if (ct->t_astflag | ct->t_sig_check) {
1447 /*
1448 * Turn off the AST flag before checking all the conditions that
1449 * may have caused an AST. This flag is on whenever a signal or
1450 * unusual condition should be handled after the next trap or
1451 * syscall.
1452 */
1453 astoff(ct);
1454 /*
1455 * If a single-step trap occurred on a syscall (see above)
1456 * recognize it now. Do this before checking for signals
1457 * because deferred_singlestep_trap() may generate a SIGTRAP to
1458 * the LWP or may otherwise mark the LWP to call issig(FORREAL).
1459 */
1460 if (lwp->lwp_pcb.pcb_flags & DEBUG_PENDING)
1461 deferred_singlestep_trap((caddr_t)rp->r_pc);
1462
1463 ct->t_sig_check = 0;
1464
1465 /*
1466 * As in other code paths that check against TP_CHANGEBIND,
1467 * we perform the check first without p_lock held -- only
1468 * acquiring p_lock in the unlikely event that it is indeed
1469 * set. This is safe because we are doing this after the
1470 * astoff(); if we are racing another thread setting
1471 * TP_CHANGEBIND on us, we will pick it up on a subsequent
1472 * lap through.
1473 */
1474 if (curthread->t_proc_flag & TP_CHANGEBIND) {
1475 mutex_enter(&p->p_lock);
1476 if (curthread->t_proc_flag & TP_CHANGEBIND) {
1477 timer_lwpbind();
1478 curthread->t_proc_flag &= ~TP_CHANGEBIND;
1479 }
1480 mutex_exit(&p->p_lock);
1481 }
1482
1483 /*
1484 * for kaio requests that are on the per-process poll queue,
1485 * aiop->aio_pollq, they're AIO_POLL bit is set, the kernel
1486 * should copyout their result_t to user memory. by copying
1487 * out the result_t, the user can poll on memory waiting
1488 * for the kaio request to complete.
1489 */
1490 if (p->p_aio)
1491 aio_cleanup(0);
1492 /*
1493 * If this LWP was asked to hold, call holdlwp(), which will
1494 * stop. holdlwps() sets this up and calls pokelwps() which
1495 * sets the AST flag.
1496 *
1497 * Also check TP_EXITLWP, since this is used by fresh new LWPs
1498 * through lwp_rtt(). That flag is set if the lwp_create(2)
1499 * syscall failed after creating the LWP.
1500 */
1501 if (ISHOLD(p))
1502 holdlwp();
1503
1504 /*
1505 * All code that sets signals and makes ISSIG evaluate true must
1506 * set t_astflag afterwards.
1507 */
1508 if (ISSIG_PENDING(ct, lwp, p)) {
1509 if (issig(FORREAL))
1510 psig();
1511 ct->t_sig_check = 1;
1512 }
1513
1514 if (ct->t_rprof != NULL) {
1515 realsigprof(0, 0, 0);
1516 ct->t_sig_check = 1;
1517 }
1518
1519 /*
1520 * /proc can't enable/disable the trace bit itself
1521 * because that could race with the call gate used by
1522 * system calls via "lcall". If that happened, an
1523 * invalid EFLAGS would result. prstep()/prnostep()
1524 * therefore schedule an AST for the purpose.
1525 */
1526 if (lwp->lwp_pcb.pcb_flags & REQUEST_STEP) {
1527 lwp->lwp_pcb.pcb_flags &= ~REQUEST_STEP;
1528 rp->r_ps |= PS_T;
1529 }
1530 if (lwp->lwp_pcb.pcb_flags & REQUEST_NOSTEP) {
1531 lwp->lwp_pcb.pcb_flags &= ~REQUEST_NOSTEP;
1532 rp->r_ps &= ~PS_T;
1533 }
1534 }
1535
1536 out: /* We can't get here from a system trap */
1537 ASSERT(type & USER);
1538
1539 if (ISHOLD(p))
1540 holdlwp();
1541
1542 /*
1543 * Set state to LWP_USER here so preempt won't give us a kernel
1544 * priority if it occurs after this point. Call CL_TRAPRET() to
1545 * restore the user-level priority.
1546 *
1547 * It is important that no locks (other than spinlocks) be entered
1548 * after this point before returning to user mode (unless lwp_state
1549 * is set back to LWP_SYS).
1550 */
1551 lwp->lwp_state = LWP_USER;
1552
1553 if (ct->t_trapret) {
1554 ct->t_trapret = 0;
1555 thread_lock(ct);
1556 CL_TRAPRET(ct);
1557 thread_unlock(ct);
1558 }
1559 if (CPU->cpu_runrun || curthread->t_schedflag & TS_ANYWAITQ)
1560 preempt();
1561 prunstop();
1562 (void) new_mstate(ct, mstate);
1563
1564 return;
1565
1566 cleanup: /* system traps end up here */
1567 ASSERT(!(type & USER));
1568 }
1569
1570 /*
1571 * Patch non-zero to disable preemption of threads in the kernel.
1572 */
1573 int IGNORE_KERNEL_PREEMPTION = 0; /* XXX - delete this someday */
1574
1575 struct kpreempt_cnts { /* kernel preemption statistics */
1576 int kpc_idle; /* executing idle thread */
1577 int kpc_intr; /* executing interrupt thread */
1578 int kpc_clock; /* executing clock thread */
1579 int kpc_blocked; /* thread has blocked preemption (t_preempt) */
1580 int kpc_notonproc; /* thread is surrendering processor */
1581 int kpc_inswtch; /* thread has ratified scheduling decision */
1582 int kpc_prilevel; /* processor interrupt level is too high */
1583 int kpc_apreempt; /* asynchronous preemption */
1584 int kpc_spreempt; /* synchronous preemption */
1585 } kpreempt_cnts;
1586
1587 /*
1588 * kernel preemption: forced rescheduling, preempt the running kernel thread.
1589 * the argument is old PIL for an interrupt,
1590 * or the distingished value KPREEMPT_SYNC.
1591 */
1592 void
1593 kpreempt(int asyncspl)
1594 {
1595 kthread_t *ct = curthread;
1596
1597 if (IGNORE_KERNEL_PREEMPTION) {
1598 aston(CPU->cpu_dispthread);
1599 return;
1600 }
1601
1602 /*
1603 * Check that conditions are right for kernel preemption
1604 */
1605 do {
1606 if (ct->t_preempt) {
1607 /*
1608 * either a privileged thread (idle, panic, interrupt)
1609 * or will check when t_preempt is lowered
1610 * We need to specifically handle the case where
1611 * the thread is in the middle of swtch (resume has
1612 * been called) and has its t_preempt set
1613 * [idle thread and a thread which is in kpreempt
1614 * already] and then a high priority thread is
1615 * available in the local dispatch queue.
1616 * In this case the resumed thread needs to take a
1617 * trap so that it can call kpreempt. We achieve
1618 * this by using siron().
1619 * How do we detect this condition:
1620 * idle thread is running and is in the midst of
1621 * resume: curthread->t_pri == -1 && CPU->dispthread
1622 * != CPU->thread
1623 * Need to ensure that this happens only at high pil
1624 * resume is called at high pil
1625 * Only in resume_from_idle is the pil changed.
1626 */
1627 if (ct->t_pri < 0) {
1628 kpreempt_cnts.kpc_idle++;
1629 if (CPU->cpu_dispthread != CPU->cpu_thread)
1630 siron();
1631 } else if (ct->t_flag & T_INTR_THREAD) {
1632 kpreempt_cnts.kpc_intr++;
1633 if (ct->t_pil == CLOCK_LEVEL)
1634 kpreempt_cnts.kpc_clock++;
1635 } else {
1636 kpreempt_cnts.kpc_blocked++;
1637 if (CPU->cpu_dispthread != CPU->cpu_thread)
1638 siron();
1639 }
1640 aston(CPU->cpu_dispthread);
1641 return;
1642 }
1643 if (ct->t_state != TS_ONPROC ||
1644 ct->t_disp_queue != CPU->cpu_disp) {
1645 /* this thread will be calling swtch() shortly */
1646 kpreempt_cnts.kpc_notonproc++;
1647 if (CPU->cpu_thread != CPU->cpu_dispthread) {
1648 /* already in swtch(), force another */
1649 kpreempt_cnts.kpc_inswtch++;
1650 siron();
1651 }
1652 return;
1653 }
1654 if (getpil() >= DISP_LEVEL) {
1655 /*
1656 * We can't preempt this thread if it is at
1657 * a PIL >= DISP_LEVEL since it may be holding
1658 * a spin lock (like sched_lock).
1659 */
1660 siron(); /* check back later */
1661 kpreempt_cnts.kpc_prilevel++;
1662 return;
1663 }
1664 if (!interrupts_enabled()) {
1665 /*
1666 * Can't preempt while running with ints disabled
1667 */
1668 kpreempt_cnts.kpc_prilevel++;
1669 return;
1670 }
1671 if (asyncspl != KPREEMPT_SYNC)
1672 kpreempt_cnts.kpc_apreempt++;
1673 else
1674 kpreempt_cnts.kpc_spreempt++;
1675
1676 ct->t_preempt++;
1677 preempt();
1678 ct->t_preempt--;
1679 } while (CPU->cpu_kprunrun);
1680 }
1681
1682 /*
1683 * Print out debugging info.
1684 */
1685 static void
1686 showregs(uint_t type, struct regs *rp, caddr_t addr)
1687 {
1688 int s;
1689
1690 s = spl7();
1691 type &= ~USER;
1692 if (PTOU(curproc)->u_comm[0])
1693 printf("%s: ", PTOU(curproc)->u_comm);
1694 if (type < TRAP_TYPES)
1695 printf("#%s %s\n", trap_type_mnemonic[type], trap_type[type]);
1696 else
1697 switch (type) {
1698 case T_SYSCALL:
1699 printf("Syscall Trap:\n");
1700 break;
1701 case T_AST:
1702 printf("AST\n");
1703 break;
1704 default:
1705 printf("Bad Trap = %d\n", type);
1706 break;
1707 }
1708 if (type == T_PGFLT) {
1709 printf("Bad %s fault at addr=0x%lx\n",
1710 USERMODE(rp->r_cs) ? "user": "kernel", (uintptr_t)addr);
1711 } else if (addr) {
1712 printf("addr=0x%lx\n", (uintptr_t)addr);
1713 }
1714
1715 printf("pid=%d, pc=0x%lx, sp=0x%lx, eflags=0x%lx\n",
1716 (ttoproc(curthread) && ttoproc(curthread)->p_pidp) ?
1717 ttoproc(curthread)->p_pid : 0, rp->r_pc, rp->r_sp, rp->r_ps);
1718
1719 printf("cr0: %b cr4: %b\n",
1720 (uint_t)getcr0(), FMT_CR0, (uint_t)getcr4(), FMT_CR4);
1721
1722 printf("cr2: %lx", getcr2());
1723 printf("cr3: %lx", getcr3());
1724 #if defined(__amd64)
1725 printf("cr8: %lx\n", getcr8());
1726 #endif
1727 printf("\n");
1728
1729 dumpregs(rp);
1730 splx(s);
1731 }
1732
1733 static void
1734 dumpregs(struct regs *rp)
1735 {
1736 #if defined(__amd64)
1737 const char fmt[] = "\t%3s: %16lx %3s: %16lx %3s: %16lx\n";
1738
1739 printf(fmt, "rdi", rp->r_rdi, "rsi", rp->r_rsi, "rdx", rp->r_rdx);
1740 printf(fmt, "rcx", rp->r_rcx, " r8", rp->r_r8, " r9", rp->r_r9);
1741 printf(fmt, "rax", rp->r_rax, "rbx", rp->r_rbx, "rbp", rp->r_rbp);
1742 printf(fmt, "r10", rp->r_r10, "r11", rp->r_r11, "r12", rp->r_r12);
1743 printf(fmt, "r13", rp->r_r13, "r14", rp->r_r14, "r15", rp->r_r15);
1744
1745 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE),
1746 " ds", rp->r_ds);
1747 printf(fmt, " es", rp->r_es, " fs", rp->r_fs, " gs", rp->r_gs);
1748
1749 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err, "rip", rp->r_rip);
1750 printf(fmt, " cs", rp->r_cs, "rfl", rp->r_rfl, "rsp", rp->r_rsp);
1751
1752 printf("\t%3s: %16lx\n", " ss", rp->r_ss);
1753
1754 #elif defined(__i386)
1755 const char fmt[] = "\t%3s: %8lx %3s: %8lx %3s: %8lx %3s: %8lx\n";
1756
1757 printf(fmt, " gs", rp->r_gs, " fs", rp->r_fs,
1758 " es", rp->r_es, " ds", rp->r_ds);
1759 printf(fmt, "edi", rp->r_edi, "esi", rp->r_esi,
1760 "ebp", rp->r_ebp, "esp", rp->r_esp);
1761 printf(fmt, "ebx", rp->r_ebx, "edx", rp->r_edx,
1762 "ecx", rp->r_ecx, "eax", rp->r_eax);
1763 printf(fmt, "trp", rp->r_trapno, "err", rp->r_err,
1764 "eip", rp->r_eip, " cs", rp->r_cs);
1765 printf("\t%3s: %8lx %3s: %8lx %3s: %8lx\n",
1766 "efl", rp->r_efl, "usp", rp->r_uesp, " ss", rp->r_ss);
1767
1768 #endif /* __i386 */
1769 }
1770
1771 /*
1772 * Test to see if the instruction is iret on i386 or iretq on amd64.
1773 *
1774 * On the hypervisor we can only test for nopop_sys_rtt_syscall. If true
1775 * then we are in the context of hypervisor's failsafe handler because it
1776 * tried to iret and failed due to a bad selector. See xen_failsafe_callback.
1777 */
1778 static int
1779 instr_is_iret(caddr_t pc)
1780 {
1781
1782
1783 #if defined(__amd64)
1784 static const uint8_t iret_insn[2] = { 0x48, 0xcf }; /* iretq */
1785
1786 #elif defined(__i386)
1787 static const uint8_t iret_insn[1] = { 0xcf }; /* iret */
1788 #endif /* __i386 */
1789 return (bcmp(pc, iret_insn, sizeof (iret_insn)) == 0);
1790
1791 }
1792
1793 #if defined(__i386)
1794
1795 /*
1796 * Test to see if the instruction is part of __SEGREGS_POP
1797 *
1798 * Note carefully the appallingly awful dependency between
1799 * the instruction sequence used in __SEGREGS_POP and these
1800 * instructions encoded here.
1801 */
1802 static int
1803 instr_is_segregs_pop(caddr_t pc)
1804 {
1805 static const uint8_t movw_0_esp_gs[4] = { 0x8e, 0x6c, 0x24, 0x0 };
1806 static const uint8_t movw_4_esp_fs[4] = { 0x8e, 0x64, 0x24, 0x4 };
1807 static const uint8_t movw_8_esp_es[4] = { 0x8e, 0x44, 0x24, 0x8 };
1808 static const uint8_t movw_c_esp_ds[4] = { 0x8e, 0x5c, 0x24, 0xc };
1809
1810 if (bcmp(pc, movw_0_esp_gs, sizeof (movw_0_esp_gs)) == 0 ||
1811 bcmp(pc, movw_4_esp_fs, sizeof (movw_4_esp_fs)) == 0 ||
1812 bcmp(pc, movw_8_esp_es, sizeof (movw_8_esp_es)) == 0 ||
1813 bcmp(pc, movw_c_esp_ds, sizeof (movw_c_esp_ds)) == 0)
1814 return (1);
1815
1816 return (0);
1817 }
1818
1819 #endif /* __i386 */
1820
1821 /*
1822 * Test to see if the instruction is part of _sys_rtt.
1823 *
1824 * Again on the hypervisor if we try to IRET to user land with a bad code
1825 * or stack selector we will get vectored through xen_failsafe_callback.
1826 * In which case we assume we got here via _sys_rtt since we only allow
1827 * IRET to user land to take place in _sys_rtt.
1828 */
1829 static int
1830 instr_is_sys_rtt(caddr_t pc)
1831 {
1832 extern void _sys_rtt(), _sys_rtt_end();
1833
1834 if ((uintptr_t)pc < (uintptr_t)_sys_rtt ||
1835 (uintptr_t)pc > (uintptr_t)_sys_rtt_end)
1836 return (0);
1837
1838 return (1);
1839 }
1840
1841 /*
1842 * Handle #gp faults in kernel mode.
1843 *
1844 * One legitimate way this can happen is if we attempt to update segment
1845 * registers to naughty values on the way out of the kernel.
1846 *
1847 * This can happen in a couple of ways: someone - either accidentally or
1848 * on purpose - creates (setcontext(2), lwp_create(2)) or modifies
1849 * (signal(2)) a ucontext that contains silly segment register values.
1850 * Or someone - either accidentally or on purpose - modifies the prgregset_t
1851 * of a subject process via /proc to contain silly segment register values.
1852 *
1853 * (The unfortunate part is that we can end up discovering the bad segment
1854 * register value in the middle of an 'iret' after we've popped most of the
1855 * stack. So it becomes quite difficult to associate an accurate ucontext
1856 * with the lwp, because the act of taking the #gp trap overwrites most of
1857 * what we were going to send the lwp.)
1858 *
1859 * OTOH if it turns out that's -not- the problem, and we're -not- an lwp
1860 * trying to return to user mode and we get a #gp fault, then we need
1861 * to die() -- which will happen if we return non-zero from this routine.
1862 */
1863 static int
1864 kern_gpfault(struct regs *rp)
1865 {
1866 kthread_t *t = curthread;
1867 proc_t *p = ttoproc(t);
1868 klwp_t *lwp = ttolwp(t);
1869 struct regs tmpregs, *trp = NULL;
1870 caddr_t pc = (caddr_t)rp->r_pc;
1871 int v;
1872 uint32_t auditing = AU_AUDITING();
1873
1874 /*
1875 * if we're not an lwp, or in the case of running native the
1876 * pc range is outside _sys_rtt, then we should immediately
1877 * be die()ing horribly.
1878 */
1879 if (lwp == NULL || !instr_is_sys_rtt(pc))
1880 return (1);
1881
1882 /*
1883 * So at least we're in the right part of the kernel.
1884 *
1885 * Disassemble the instruction at the faulting pc.
1886 * Once we know what it is, we carefully reconstruct the stack
1887 * based on the order in which the stack is deconstructed in
1888 * _sys_rtt. Ew.
1889 */
1890 if (instr_is_iret(pc)) {
1891 /*
1892 * We took the #gp while trying to perform the IRET.
1893 * This means that either %cs or %ss are bad.
1894 * All we know for sure is that most of the general
1895 * registers have been restored, including the
1896 * segment registers, and all we have left on the
1897 * topmost part of the lwp's stack are the
1898 * registers that the iretq was unable to consume.
1899 *
1900 * All the rest of the state was crushed by the #gp
1901 * which pushed -its- registers atop our old save area
1902 * (because we had to decrement the stack pointer, sigh) so
1903 * all that we can try and do is to reconstruct the
1904 * crushed frame from the #gp trap frame itself.
1905 */
1906 trp = &tmpregs;
1907 trp->r_ss = lwptoregs(lwp)->r_ss;
1908 trp->r_sp = lwptoregs(lwp)->r_sp;
1909 trp->r_ps = lwptoregs(lwp)->r_ps;
1910 trp->r_cs = lwptoregs(lwp)->r_cs;
1911 trp->r_pc = lwptoregs(lwp)->r_pc;
1912 bcopy(rp, trp, offsetof(struct regs, r_pc));
1913
1914 /*
1915 * Validate simple math
1916 */
1917 ASSERT(trp->r_pc == lwptoregs(lwp)->r_pc);
1918 ASSERT(trp->r_err == rp->r_err);
1919
1920
1921
1922 }
1923
1924 #if defined(__amd64)
1925 if (trp == NULL && lwp->lwp_pcb.pcb_rupdate != 0) {
1926
1927 /*
1928 * This is the common case -- we're trying to load
1929 * a bad segment register value in the only section
1930 * of kernel code that ever loads segment registers.
1931 *
1932 * We don't need to do anything at this point because
1933 * the pcb contains all the pending segment register
1934 * state, and the regs are still intact because we
1935 * didn't adjust the stack pointer yet. Given the fidelity
1936 * of all this, we could conceivably send a signal
1937 * to the lwp, rather than core-ing.
1938 */
1939 trp = lwptoregs(lwp);
1940 ASSERT((caddr_t)trp == (caddr_t)rp->r_sp);
1941 }
1942
1943 #elif defined(__i386)
1944
1945 if (trp == NULL && instr_is_segregs_pop(pc))
1946 trp = lwptoregs(lwp);
1947
1948 #endif /* __i386 */
1949
1950 if (trp == NULL)
1951 return (1);
1952
1953 /*
1954 * If we get to here, we're reasonably confident that we've
1955 * correctly decoded what happened on the way out of the kernel.
1956 * Rewrite the lwp's registers so that we can create a core dump
1957 * the (at least vaguely) represents the mcontext we were
1958 * being asked to restore when things went so terribly wrong.
1959 */
1960
1961 /*
1962 * Make sure that we have a meaningful %trapno and %err.
1963 */
1964 trp->r_trapno = rp->r_trapno;
1965 trp->r_err = rp->r_err;
1966
1967 if ((caddr_t)trp != (caddr_t)lwptoregs(lwp))
1968 bcopy(trp, lwptoregs(lwp), sizeof (*trp));
1969
1970
1971 mutex_enter(&p->p_lock);
1972 lwp->lwp_cursig = SIGSEGV;
1973 mutex_exit(&p->p_lock);
1974
1975 /*
1976 * Terminate all LWPs but don't discard them. If another lwp beat
1977 * us to the punch by calling exit(), evaporate now.
1978 */
1979 proc_is_exiting(p);
1980 if (exitlwps(1) != 0) {
1981 mutex_enter(&p->p_lock);
1982 lwp_exit();
1983 }
1984
1985 if (auditing) /* audit core dump */
1986 audit_core_start(SIGSEGV);
1987 v = core(SIGSEGV, B_FALSE);
1988 if (auditing) /* audit core dump */
1989 audit_core_finish(v ? CLD_KILLED : CLD_DUMPED);
1990 exit(v ? CLD_KILLED : CLD_DUMPED, SIGSEGV);
1991 return (0);
1992 }
1993
1994 /*
1995 * dump_tss() - Display the TSS structure
1996 */
1997
1998 #if defined(__amd64)
1999
2000 static void
2001 dump_tss(void)
2002 {
2003 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */
2004 tss_t *tss = CPU->cpu_tss;
2005
2006 printf(tss_fmt, "tss_rsp0", (void *)tss->tss_rsp0);
2007 printf(tss_fmt, "tss_rsp1", (void *)tss->tss_rsp1);
2008 printf(tss_fmt, "tss_rsp2", (void *)tss->tss_rsp2);
2009
2010 printf(tss_fmt, "tss_ist1", (void *)tss->tss_ist1);
2011 printf(tss_fmt, "tss_ist2", (void *)tss->tss_ist2);
2012 printf(tss_fmt, "tss_ist3", (void *)tss->tss_ist3);
2013 printf(tss_fmt, "tss_ist4", (void *)tss->tss_ist4);
2014 printf(tss_fmt, "tss_ist5", (void *)tss->tss_ist5);
2015 printf(tss_fmt, "tss_ist6", (void *)tss->tss_ist6);
2016 printf(tss_fmt, "tss_ist7", (void *)tss->tss_ist7);
2017 }
2018
2019 #elif defined(__i386)
2020
2021 static void
2022 dump_tss(void)
2023 {
2024 const char tss_fmt[] = "tss.%s:\t0x%p\n"; /* Format string */
2025 tss_t *tss = CPU->cpu_tss;
2026
2027 printf(tss_fmt, "tss_link", (void *)(uintptr_t)tss->tss_link);
2028 printf(tss_fmt, "tss_esp0", (void *)(uintptr_t)tss->tss_esp0);
2029 printf(tss_fmt, "tss_ss0", (void *)(uintptr_t)tss->tss_ss0);
2030 printf(tss_fmt, "tss_esp1", (void *)(uintptr_t)tss->tss_esp1);
2031 printf(tss_fmt, "tss_ss1", (void *)(uintptr_t)tss->tss_ss1);
2032 printf(tss_fmt, "tss_esp2", (void *)(uintptr_t)tss->tss_esp2);
2033 printf(tss_fmt, "tss_ss2", (void *)(uintptr_t)tss->tss_ss2);
2034 printf(tss_fmt, "tss_cr3", (void *)(uintptr_t)tss->tss_cr3);
2035 printf(tss_fmt, "tss_eip", (void *)(uintptr_t)tss->tss_eip);
2036 printf(tss_fmt, "tss_eflags", (void *)(uintptr_t)tss->tss_eflags);
2037 printf(tss_fmt, "tss_eax", (void *)(uintptr_t)tss->tss_eax);
2038 printf(tss_fmt, "tss_ebx", (void *)(uintptr_t)tss->tss_ebx);
2039 printf(tss_fmt, "tss_ecx", (void *)(uintptr_t)tss->tss_ecx);
2040 printf(tss_fmt, "tss_edx", (void *)(uintptr_t)tss->tss_edx);
2041 printf(tss_fmt, "tss_esp", (void *)(uintptr_t)tss->tss_esp);
2042 }
2043
2044 #endif /* __amd64 */
2045
2046 #if defined(TRAPTRACE)
2047
2048 int ttrace_nrec = 10; /* number of records to dump out */
2049 int ttrace_dump_nregs = 0; /* dump out this many records with regs too */
2050
2051 /*
2052 * Dump out the last ttrace_nrec traptrace records on each CPU
2053 */
2054 static void
2055 dump_ttrace(void)
2056 {
2057 trap_trace_ctl_t *ttc;
2058 trap_trace_rec_t *rec;
2059 uintptr_t current;
2060 int i, j, k;
2061 int n = NCPU;
2062 #if defined(__amd64)
2063 const char banner[] =
2064 "CPU ADDRESS TIMESTAMP TYPE VC HANDLER PC\n";
2065 /* Define format for the CPU, ADDRESS, and TIMESTAMP fields */
2066 const char fmt1[] = "%3d %016lx %12llx";
2067 char data1[34]; /* length of string formatted by fmt1 + 1 */
2068 #elif defined(__i386)
2069 const char banner[] =
2070 "CPU ADDRESS TIMESTAMP TYPE VC HANDLER PC\n";
2071 /* Define format for the CPU, ADDRESS, and TIMESTAMP fields */
2072 const char fmt1[] = "%3d %08lx %12llx";
2073 char data1[26]; /* length of string formatted by fmt1 + 1 */
2074 #endif
2075 /* Define format for the TYPE and VC fields */
2076 const char fmt2[] = "%4s %3x";
2077 char data2[9]; /* length of string formatted by fmt2 + 1 */
2078 /*
2079 * Define format for the HANDLER field. Width is arbitrary, but should
2080 * be enough for common handler's names, and leave enough space for
2081 * the PC field, especially when we are in kmdb.
2082 */
2083 const char fmt3h[] = "#%-15s";
2084 const char fmt3p[] = "%-16p";
2085 const char fmt3s[] = "%-16s";
2086 char data3[17]; /* length of string formatted by fmt3* + 1 */
2087
2088 if (ttrace_nrec == 0)
2089 return;
2090
2091 printf("\n");
2092 printf(banner);
2093
2094 for (i = 0; i < n; i++) {
2095 ttc = &trap_trace_ctl[i];
2096 if (ttc->ttc_first == (uintptr_t)NULL)
2097 continue;
2098
2099 current = ttc->ttc_next - sizeof (trap_trace_rec_t);
2100 for (j = 0; j < ttrace_nrec; j++) {
2101 struct sysent *sys;
2102 struct autovec *vec;
2103 extern struct av_head autovect[];
2104 int type;
2105 ulong_t off;
2106 char *sym, *stype;
2107
2108 if (current < ttc->ttc_first)
2109 current =
2110 ttc->ttc_limit - sizeof (trap_trace_rec_t);
2111
2112 if (current == (uintptr_t)NULL)
2113 continue;
2114
2115 rec = (trap_trace_rec_t *)current;
2116
2117 if (rec->ttr_stamp == 0)
2118 break;
2119
2120 (void) snprintf(data1, sizeof (data1), fmt1, i,
2121 (uintptr_t)rec, rec->ttr_stamp);
2122
2123 switch (rec->ttr_marker) {
2124 case TT_SYSCALL:
2125 case TT_SYSENTER:
2126 case TT_SYSC:
2127 case TT_SYSC64:
2128 #if defined(__amd64)
2129 sys = &sysent32[rec->ttr_sysnum];
2130 switch (rec->ttr_marker) {
2131 case TT_SYSC64:
2132 sys = &sysent[rec->ttr_sysnum];
2133 /*FALLTHROUGH*/
2134 #elif defined(__i386)
2135 sys = &sysent[rec->ttr_sysnum];
2136 switch (rec->ttr_marker) {
2137 case TT_SYSC64:
2138 #endif
2139 case TT_SYSC:
2140 stype = "sysc"; /* syscall */
2141 break;
2142 case TT_SYSCALL:
2143 stype = "lcal"; /* lcall */
2144 break;
2145 case TT_SYSENTER:
2146 stype = "syse"; /* sysenter */
2147 break;
2148 default:
2149 break;
2150 }
2151 (void) snprintf(data2, sizeof (data2), fmt2,
2152 stype, rec->ttr_sysnum);
2153 if (sys != NULL) {
2154 sym = kobj_getsymname(
2155 (uintptr_t)sys->sy_callc,
2156 &off);
2157 if (sym != NULL) {
2158 (void) snprintf(data3,
2159 sizeof (data3), fmt3s, sym);
2160 } else {
2161 (void) snprintf(data3,
2162 sizeof (data3), fmt3p,
2163 sys->sy_callc);
2164 }
2165 } else {
2166 (void) snprintf(data3, sizeof (data3),
2167 fmt3s, "unknown");
2168 }
2169 break;
2170
2171 case TT_INTERRUPT:
2172 (void) snprintf(data2, sizeof (data2), fmt2,
2173 "intr", rec->ttr_vector);
2174 if (get_intr_handler != NULL)
2175 vec = (struct autovec *)
2176 (*get_intr_handler)
2177 (rec->ttr_cpuid, rec->ttr_vector);
2178 else
2179 vec =
2180 autovect[rec->ttr_vector].avh_link;
2181
2182 if (vec != NULL) {
2183 sym = kobj_getsymname(
2184 (uintptr_t)vec->av_vector, &off);
2185 if (sym != NULL) {
2186 (void) snprintf(data3,
2187 sizeof (data3), fmt3s, sym);
2188 } else {
2189 (void) snprintf(data3,
2190 sizeof (data3), fmt3p,
2191 vec->av_vector);
2192 }
2193 } else {
2194 (void) snprintf(data3, sizeof (data3),
2195 fmt3s, "unknown");
2196 }
2197 break;
2198
2199 case TT_TRAP:
2200 case TT_EVENT:
2201 type = rec->ttr_regs.r_trapno;
2202 (void) snprintf(data2, sizeof (data2), fmt2,
2203 "trap", type);
2204 if (type < TRAP_TYPES) {
2205 (void) snprintf(data3, sizeof (data3),
2206 fmt3h, trap_type_mnemonic[type]);
2207 } else {
2208 switch (type) {
2209 case T_AST:
2210 (void) snprintf(data3,
2211 sizeof (data3), fmt3s,
2212 "ast");
2213 break;
2214 default:
2215 (void) snprintf(data3,
2216 sizeof (data3), fmt3s, "");
2217 break;
2218 }
2219 }
2220 break;
2221
2222 default:
2223 break;
2224 }
2225
2226 sym = kobj_getsymname(rec->ttr_regs.r_pc, &off);
2227 if (sym != NULL) {
2228 printf("%s %s %s %s+%lx\n", data1, data2, data3,
2229 sym, off);
2230 } else {
2231 printf("%s %s %s %lx\n", data1, data2, data3,
2232 rec->ttr_regs.r_pc);
2233 }
2234
2235 if (ttrace_dump_nregs-- > 0) {
2236 int s;
2237
2238 if (rec->ttr_marker == TT_INTERRUPT)
2239 printf(
2240 "\t\tipl %x spl %x pri %x\n",
2241 rec->ttr_ipl,
2242 rec->ttr_spl,
2243 rec->ttr_pri);
2244
2245 dumpregs(&rec->ttr_regs);
2246
2247 printf("\t%3s: %p\n\n", " ct",
2248 (void *)rec->ttr_curthread);
2249
2250 /*
2251 * print out the pc stack that we recorded
2252 * at trap time (if any)
2253 */
2254 for (s = 0; s < rec->ttr_sdepth; s++) {
2255 uintptr_t fullpc;
2256
2257 if (s >= TTR_STACK_DEPTH) {
2258 printf("ttr_sdepth corrupt\n");
2259 break;
2260 }
2261
2262 fullpc = (uintptr_t)rec->ttr_stack[s];
2263
2264 sym = kobj_getsymname(fullpc, &off);
2265 if (sym != NULL)
2266 printf("-> %s+0x%lx()\n",
2267 sym, off);
2268 else
2269 printf("-> 0x%lx()\n", fullpc);
2270 }
2271 printf("\n");
2272 }
2273 current -= sizeof (trap_trace_rec_t);
2274 }
2275 }
2276 }
2277
2278 #endif /* TRAPTRACE */
2279
2280 void
2281 panic_showtrap(struct panic_trap_info *tip)
2282 {
2283 showregs(tip->trap_type, tip->trap_regs, tip->trap_addr);
2284
2285 #if defined(TRAPTRACE)
2286 dump_ttrace();
2287 #endif
2288
2289 if (tip->trap_type == T_DBLFLT)
2290 dump_tss();
2291 }
2292
2293 void
2294 panic_savetrap(panic_data_t *pdp, struct panic_trap_info *tip)
2295 {
2296 panic_saveregs(pdp, tip->trap_regs);
2297 }
Unleashed OS