5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
26 * Copyright (c) 2009-2010, Intel Corporation.
27 * All rights reserved.
31 #include <sys/smp_impldefs.h>
33 #include <sys/psm_modctl.h>
35 #include <sys/cmn_err.h>
36 #include <sys/strlog.h>
37 #include <sys/clock.h>
38 #include <sys/debug.h>
40 #include <sys/x86_archext.h>
41 #include <sys/cpupart.h>
42 #include <sys/cpuvar.h>
43 #include <sys/cpu_event.h>
47 #include <sys/archsystm.h>
48 #include <sys/machsystm.h>
49 #include <sys/sysmacros.h>
50 #include <sys/memlist.h>
51 #include <sys/param.h>
52 #include <sys/promif.h>
53 #include <sys/cpu_pm.h>
54 #include <sys/mach_intr.h>
55 #include <vm/hat_i86.h>
56 #include <sys/kdi_machimpl.h>
59 #include <sys/sunddi.h>
60 #include <sys/sunndi.h>
61 #include <sys/cpc_pcbe.h>
63 #define OFFSETOF(s, m) (size_t)(&(((s *)0)->m))
66 * Local function prototypes
68 static int mp_disable_intr(processorid_t cpun
);
69 static void mp_enable_intr(processorid_t cpun
);
70 static void mach_init();
71 static void mach_picinit();
72 static int machhztomhz(uint64_t cpu_freq_hz
);
73 static uint64_t mach_getcpufreq(void);
74 static void mach_fixcpufreq(void);
75 static int mach_clkinit(int, int *);
76 static void mach_smpinit(void);
77 static int mach_softlvl_to_vect(int ipl
);
78 static void mach_get_platform(int owner
);
79 static void mach_construct_info();
80 static int mach_translate_irq(dev_info_t
*dip
, int irqno
);
81 static int mach_intr_ops(dev_info_t
*, ddi_intr_handle_impl_t
*,
82 psm_intr_op_t
, int *);
83 static void mach_notify_error(int level
, char *errmsg
);
84 static hrtime_t
dummy_hrtime(void);
85 static void dummy_scalehrtime(hrtime_t
*);
86 static uint64_t dummy_unscalehrtime(hrtime_t
);
88 static void cpu_wakeup(cpu_t
*, int);
89 void cpu_idle_mwait(void);
90 static void cpu_wakeup_mwait(cpu_t
*, int);
91 static int mach_cpu_create_devinfo(cpu_t
*cp
, dev_info_t
**dipp
);
94 * External reference functions
96 extern void return_instr();
97 extern uint64_t freq_tsc(uint32_t *);
99 extern uint64_t freq_notsc(uint32_t *);
101 extern void pc_gethrestime(timestruc_t
*);
102 extern int cpuid_get_coreid(cpu_t
*);
103 extern int cpuid_get_chipid(cpu_t
*);
106 * PSM functions initialization
108 void (*psm_shutdownf
)(int, int) = (void (*)(int, int))return_instr
;
109 void (*psm_preshutdownf
)(int, int) = (void (*)(int, int))return_instr
;
110 void (*psm_notifyf
)(int) = (void (*)(int))return_instr
;
111 void (*psm_set_idle_cpuf
)(int) = (void (*)(int))return_instr
;
112 void (*psm_unset_idle_cpuf
)(int) = (void (*)(int))return_instr
;
113 void (*psminitf
)() = mach_init
;
114 void (*picinitf
)() = return_instr
;
115 int (*clkinitf
)(int, int *) = (int (*)(int, int *))return_instr
;
116 int (*ap_mlsetup
)() = (int (*)(void))return_instr
;
117 void (*send_dirintf
)() = return_instr
;
118 void (*setspl
)(int) = (void (*)(int))return_instr
;
119 int (*addspl
)(int, int, int, int) = (int (*)(int, int, int, int))return_instr
;
120 int (*delspl
)(int, int, int, int) = (int (*)(int, int, int, int))return_instr
;
121 int (*get_pending_spl
)(void) = (int (*)(void))return_instr
;
122 int (*addintr
)(void *, int, avfunc
, char *, int, caddr_t
, caddr_t
,
123 uint64_t *, dev_info_t
*) = NULL
;
124 void (*remintr
)(void *, int, avfunc
, int) = NULL
;
125 void (*kdisetsoftint
)(int, struct av_softinfo
*)=
126 (void (*)(int, struct av_softinfo
*))return_instr
;
127 void (*setsoftint
)(int, struct av_softinfo
*)=
128 (void (*)(int, struct av_softinfo
*))return_instr
;
129 int (*slvltovect
)(int) = (int (*)(int))return_instr
;
130 int (*setlvl
)(int, int *) = (int (*)(int, int *))return_instr
;
131 void (*setlvlx
)(int, int) = (void (*)(int, int))return_instr
;
132 int (*psm_disable_intr
)(int) = mp_disable_intr
;
133 void (*psm_enable_intr
)(int) = mp_enable_intr
;
134 hrtime_t (*gethrtimef
)(void) = dummy_hrtime
;
135 hrtime_t (*gethrtimeunscaledf
)(void) = dummy_hrtime
;
136 void (*scalehrtimef
)(hrtime_t
*) = dummy_scalehrtime
;
137 uint64_t (*unscalehrtimef
)(hrtime_t
) = dummy_unscalehrtime
;
138 int (*psm_translate_irq
)(dev_info_t
*, int) = mach_translate_irq
;
139 void (*gethrestimef
)(timestruc_t
*) = pc_gethrestime
;
140 void (*psm_notify_error
)(int, char *) = (void (*)(int, char *))NULL
;
141 int (*psm_get_clockirq
)(int) = NULL
;
142 int (*psm_get_ipivect
)(int, int) = NULL
;
143 uchar_t (*psm_get_ioapicid
)(uchar_t
) = NULL
;
144 uint32_t (*psm_get_localapicid
)(uint32_t) = NULL
;
145 uchar_t (*psm_xlate_vector_by_irq
)(uchar_t
) = NULL
;
147 int (*psm_clkinit
)(int) = NULL
;
148 void (*psm_timer_reprogram
)(hrtime_t
) = NULL
;
149 void (*psm_timer_enable
)(void) = NULL
;
150 void (*psm_timer_disable
)(void) = NULL
;
151 void (*psm_post_cyclic_setup
)(void *arg
) = NULL
;
152 int (*psm_intr_ops
)(dev_info_t
*, ddi_intr_handle_impl_t
*, psm_intr_op_t
,
153 int *) = mach_intr_ops
;
154 int (*psm_state
)(psm_state_request_t
*) = (int (*)(psm_state_request_t
*))
157 void (*notify_error
)(int, char *) = (void (*)(int, char *))return_instr
;
158 void (*hrtime_tick
)(void) = return_instr
;
160 int (*psm_cpu_create_devinfo
)(cpu_t
*, dev_info_t
**) = mach_cpu_create_devinfo
;
161 int (*psm_cpu_get_devinfo
)(cpu_t
*, dev_info_t
**) = NULL
;
163 /* global IRM pool for APIX (PSM) module */
164 ddi_irm_pool_t
*apix_irm_pool_p
= NULL
;
167 * True if the generic TSC code is our source of hrtime, rather than whatever
168 * the PSM can provide.
170 int tsc_gethrtime_enable
= 1;
171 int tsc_gethrtime_initted
= 0;
174 * True if the hrtime implementation is "hires"; namely, better than microdata.
176 int gethrtime_hires
= 0;
181 static struct psm_ops mach_ops
;
182 static struct psm_ops
*mach_set
[4] = {&mach_ops
, NULL
, NULL
, NULL
};
183 static ushort_t mach_ver
[4] = {0, 0, 0, 0};
186 * virtualization support for psm
188 void *psm_vt_ops
= NULL
;
190 * If non-zero, idle cpus will become "halted" when there's
193 int idle_cpu_use_hlt
= 1;
196 * If non-zero, idle cpus will use mwait if available to halt instead of hlt.
198 int idle_cpu_prefer_mwait
= 1;
200 * Set to 0 to avoid MONITOR+CLFLUSH assertion.
202 int idle_cpu_assert_cflush_monitor
= 1;
205 * If non-zero, idle cpus will not use power saving Deep C-States idle loop.
207 int idle_cpu_no_deep_c
= 0;
209 * Non-power saving idle loop and wakeup pointers.
210 * Allows user to toggle Deep Idle power saving feature on/off.
212 void (*non_deep_idle_cpu
)() = cpu_idle
;
213 void (*non_deep_idle_disp_enq_thread
)(cpu_t
*, int);
216 * Object for the kernel to access the HPET.
221 uint_t cp_haltset_fanout
= 0;
225 pg_plat_hw_shared(cpu_t
*cp
, pghw_type_t hw
)
229 if (is_x86_feature(x86_featureset
, X86FSET_HTT
)) {
231 * Hyper-threading is SMT
238 if (cpuid_get_cores_per_compunit(cp
) > 1)
243 if (cpuid_get_procnodes_per_pkg(cp
) > 1)
248 if (is_x86_feature(x86_featureset
, X86FSET_CMP
) ||
249 is_x86_feature(x86_featureset
, X86FSET_HTT
))
254 if (cpuid_get_ncpu_sharing_last_cache(cp
) > 1)
258 case PGHW_POW_ACTIVE
:
259 if (cpupm_domain_id(cp
, CPUPM_DTYPE_ACTIVE
) != (id_t
)-1)
264 if (cpupm_domain_id(cp
, CPUPM_DTYPE_IDLE
) != (id_t
)-1)
274 * Compare two CPUs and see if they have a pghw_type_t sharing relationship
275 * If pghw_type_t is an unsupported hardware type, then return -1
278 pg_plat_cpus_share(cpu_t
*cpu_a
, cpu_t
*cpu_b
, pghw_type_t hw
)
282 pgp_a
= pg_plat_hw_instance_id(cpu_a
, hw
);
283 pgp_b
= pg_plat_hw_instance_id(cpu_b
, hw
);
285 if (pgp_a
== -1 || pgp_b
== -1)
288 return (pgp_a
== pgp_b
);
292 * Return a physical instance identifier for known hardware sharing
296 pg_plat_hw_instance_id(cpu_t
*cpu
, pghw_type_t hw
)
300 return (cpuid_get_coreid(cpu
));
302 return (cpuid_get_last_lvl_cacheid(cpu
));
304 return (cpuid_get_compunitid(cpu
));
306 return (cpuid_get_procnodeid(cpu
));
308 return (cpuid_get_chipid(cpu
));
309 case PGHW_POW_ACTIVE
:
310 return (cpupm_domain_id(cpu
, CPUPM_DTYPE_ACTIVE
));
312 return (cpupm_domain_id(cpu
, CPUPM_DTYPE_IDLE
));
319 * Express preference for optimizing for sharing relationship
323 pg_plat_hw_rank(pghw_type_t hw1
, pghw_type_t hw2
)
327 static pghw_type_t hw_hier
[] = {
338 for (i
= 0; hw_hier
[i
] != PGHW_NUM_COMPONENTS
; i
++) {
339 if (hw_hier
[i
] == hw1
)
341 if (hw_hier
[i
] == hw2
)
352 * Override the default CMT dispatcher policy for the specified
353 * hardware sharing relationship
356 pg_plat_cmt_policy(pghw_type_t hw
)
359 * For shared caches, also load balance across them to
360 * maximize aggregate cache capacity
362 * On AMD family 0x15 CPUs, cores come in pairs called
363 * compute units, sharing the FPU and the I$ and L2
364 * caches. Use balancing and cache affinity.
369 return (CMT_BALANCE
|CMT_AFFINITY
);
371 return (CMT_NO_POLICY
);
376 pg_plat_get_core_id(cpu_t
*cpu
)
378 return ((id_t
)cpuid_get_coreid(cpu
));
382 cmp_set_nosteal_interval(void)
384 /* Set the nosteal interval (used by disp_getbest()) to 100us */
385 nosteal_nsec
= 100000UL;
389 * Routine to ensure initial callers to hrtime gets 0 as return
399 dummy_scalehrtime(hrtime_t
*ticks
)
403 dummy_unscalehrtime(hrtime_t nsecs
)
405 return ((uint64_t)nsecs
);
409 * Supports Deep C-State power saving idle loop.
412 cpu_idle_adaptive(void)
414 (*CPU
->cpu_m
.mcpu_idle_cpu
)();
418 * Function called by CPU idle notification framework to check whether CPU
419 * has been awakened. It will be called with interrupt disabled.
420 * If CPU has been awakened, call cpu_idle_exit() to notify CPU idle
421 * notification framework.
425 cpu_idle_check_wakeup(void *arg
)
428 * Toggle interrupt flag to detect pending interrupts.
429 * If interrupt happened, do_interrupt() will notify CPU idle
430 * notification framework so no need to call cpu_idle_exit() here.
438 * Idle the present CPU until wakened via an interrupt
444 processorid_t cpu_sid
= cpup
->cpu_seqid
;
445 cpupart_t
*cp
= cpup
->cpu_part
;
449 * If this CPU is online, and there's multiple CPUs
450 * in the system, then we should notate our halting
451 * by adding ourselves to the partition's halted CPU
452 * bitmap. This allows other CPUs to find/awaken us when
453 * work becomes available.
455 if (cpup
->cpu_flags
& CPU_OFFLINE
|| ncpus
== 1)
459 * Add ourselves to the partition's halted CPUs bitmap
460 * and set our HALTED flag, if necessary.
462 * When a thread becomes runnable, it is placed on the queue
463 * and then the halted CPU bitmap is checked to determine who
464 * (if anyone) should be awakened. We therefore need to first
465 * add ourselves to the bitmap, and and then check if there
466 * is any work available. The order is important to prevent a race
467 * that can lead to work languishing on a run queue somewhere while
468 * this CPU remains halted.
470 * Either the producing CPU will see we're halted and will awaken us,
471 * or this CPU will see the work available in disp_anywork().
473 * Note that memory barriers after updating the HALTED flag
474 * are not necessary since an atomic operation (updating the bitset)
475 * immediately follows. On x86 the atomic operation acts as a
476 * memory barrier for the update of cpu_disp_flags.
479 cpup
->cpu_disp_flags
|= CPU_DISP_HALTED
;
480 bitset_atomic_add(&cp
->cp_haltset
, cpu_sid
);
484 * Check to make sure there's really nothing to do.
485 * Work destined for this CPU may become available after
486 * this check. We'll be notified through the clearing of our
487 * bit in the halted CPU bitmap, and a poke.
489 if (disp_anywork()) {
491 cpup
->cpu_disp_flags
&= ~CPU_DISP_HALTED
;
492 bitset_atomic_del(&cp
->cp_haltset
, cpu_sid
);
498 * We're on our way to being halted.
500 * Disable interrupts now, so that we'll awaken immediately
501 * after halting if someone tries to poke us between now and
502 * the time we actually halt.
504 * We check for the presence of our bit after disabling interrupts.
505 * If it's cleared, we'll return. If the bit is cleared after
506 * we check then the poke will pop us out of the halted state.
508 * This means that the ordering of the poke and the clearing
509 * of the bit by cpu_wakeup is important.
510 * cpu_wakeup() must clear, then poke.
511 * cpu_idle() must disable interrupts, then check for the bit.
515 if (hset_update
&& bitset_in_set(&cp
->cp_haltset
, cpu_sid
) == 0) {
516 cpup
->cpu_disp_flags
&= ~CPU_DISP_HALTED
;
522 * The check for anything locally runnable is here for performance
523 * and isn't needed for correctness. disp_nrunnable ought to be
524 * in our cache still, so it's inexpensive to check, and if there
525 * is anything runnable we won't have to wait for the poke.
527 if (cpup
->cpu_disp
->disp_nrunnable
!= 0) {
529 cpup
->cpu_disp_flags
&= ~CPU_DISP_HALTED
;
530 bitset_atomic_del(&cp
->cp_haltset
, cpu_sid
);
536 if (cpu_idle_enter(IDLE_STATE_C1
, 0,
537 cpu_idle_check_wakeup
, NULL
) == 0) {
539 cpu_idle_exit(CPU_IDLE_CB_FLAG_IDLE
);
543 * We're no longer halted
546 cpup
->cpu_disp_flags
&= ~CPU_DISP_HALTED
;
547 bitset_atomic_del(&cp
->cp_haltset
, cpu_sid
);
553 * If "cpu" is halted, then wake it up clearing its halted bit in advance.
554 * Otherwise, see if other CPUs in the cpu partition are halted and need to
555 * be woken up so that they can steal the thread we placed on this CPU.
556 * This function is only used on MP systems.
559 cpu_wakeup(cpu_t
*cpu
, int bound
)
562 processorid_t cpu_sid
;
566 cpu_sid
= cpu
->cpu_seqid
;
567 if (bitset_in_set(&cp
->cp_haltset
, cpu_sid
)) {
569 * Clear the halted bit for that CPU since it will be
572 bitset_atomic_del(&cp
->cp_haltset
, cpu_sid
);
574 * We may find the current CPU present in the halted cpuset
575 * if we're in the context of an interrupt that occurred
576 * before we had a chance to clear our bit in cpu_idle().
577 * Poking ourself is obviously unnecessary, since if
578 * we're here, we're not halted.
581 poke_cpu(cpu
->cpu_id
);
585 * This cpu isn't halted, but it's idle or undergoing a
586 * context switch. No need to awaken anyone else.
588 if (cpu
->cpu_thread
== cpu
->cpu_idle_thread
||
589 cpu
->cpu_disp_flags
& CPU_DISP_DONTSTEAL
)
594 * No need to wake up other CPUs if this is for a bound thread.
600 * The CPU specified for wakeup isn't currently halted, so check
601 * to see if there are any other halted CPUs in the partition,
602 * and if there are then awaken one.
605 cpu_found
= bitset_find(&cp
->cp_haltset
);
606 if (cpu_found
== (uint_t
)-1)
608 } while (bitset_atomic_test_and_del(&cp
->cp_haltset
, cpu_found
) < 0);
610 if (cpu_found
!= CPU
->cpu_seqid
) {
611 poke_cpu(cpu_seq
[cpu_found
]->cpu_id
);
616 * Function called by CPU idle notification framework to check whether CPU
617 * has been awakened. It will be called with interrupt disabled.
618 * If CPU has been awakened, call cpu_idle_exit() to notify CPU idle
619 * notification framework.
622 cpu_idle_mwait_check_wakeup(void *arg
)
624 volatile uint32_t *mcpu_mwait
= (volatile uint32_t *)arg
;
627 if (*mcpu_mwait
!= MWAIT_HALTED
) {
629 * CPU has been awakened, notify CPU idle notification system.
631 cpu_idle_exit(CPU_IDLE_CB_FLAG_IDLE
);
634 * Toggle interrupt flag to detect pending interrupts.
635 * If interrupt happened, do_interrupt() will notify CPU idle
636 * notification framework so no need to call cpu_idle_exit()
646 * Idle the present CPU until awakened via touching its monitored line
651 volatile uint32_t *mcpu_mwait
= CPU
->cpu_m
.mcpu_mwait
;
653 processorid_t cpu_sid
= cpup
->cpu_seqid
;
654 cpupart_t
*cp
= cpup
->cpu_part
;
658 * Set our mcpu_mwait here, so we can tell if anyone tries to
659 * wake us between now and when we call mwait. No other cpu will
660 * attempt to set our mcpu_mwait until we add ourself to the halted
663 *mcpu_mwait
= MWAIT_HALTED
;
666 * If this CPU is online, and there's multiple CPUs
667 * in the system, then we should note our halting
668 * by adding ourselves to the partition's halted CPU
669 * bitmap. This allows other CPUs to find/awaken us when
670 * work becomes available.
672 if (cpup
->cpu_flags
& CPU_OFFLINE
|| ncpus
== 1)
676 * Add ourselves to the partition's halted CPUs bitmap
677 * and set our HALTED flag, if necessary.
679 * When a thread becomes runnable, it is placed on the queue
680 * and then the halted CPU bitmap is checked to determine who
681 * (if anyone) should be awakened. We therefore need to first
682 * add ourselves to the bitmap, and and then check if there
683 * is any work available.
685 * Note that memory barriers after updating the HALTED flag
686 * are not necessary since an atomic operation (updating the bitmap)
687 * immediately follows. On x86 the atomic operation acts as a
688 * memory barrier for the update of cpu_disp_flags.
691 cpup
->cpu_disp_flags
|= CPU_DISP_HALTED
;
692 bitset_atomic_add(&cp
->cp_haltset
, cpu_sid
);
696 * Check to make sure there's really nothing to do.
697 * Work destined for this CPU may become available after
698 * this check. We'll be notified through the clearing of our
699 * bit in the halted CPU bitmap, and a write to our mcpu_mwait.
701 * disp_anywork() checks disp_nrunnable, so we do not have to later.
703 if (disp_anywork()) {
705 cpup
->cpu_disp_flags
&= ~CPU_DISP_HALTED
;
706 bitset_atomic_del(&cp
->cp_haltset
, cpu_sid
);
712 * We're on our way to being halted.
713 * To avoid a lost wakeup, arm the monitor before checking if another
714 * cpu wrote to mcpu_mwait to wake us up.
716 i86_monitor(mcpu_mwait
, 0, 0);
717 if (*mcpu_mwait
== MWAIT_HALTED
) {
718 if (cpu_idle_enter(IDLE_STATE_C1
, 0,
719 cpu_idle_mwait_check_wakeup
, (void *)mcpu_mwait
) == 0) {
720 if (*mcpu_mwait
== MWAIT_HALTED
) {
723 cpu_idle_exit(CPU_IDLE_CB_FLAG_IDLE
);
728 * We're no longer halted
731 cpup
->cpu_disp_flags
&= ~CPU_DISP_HALTED
;
732 bitset_atomic_del(&cp
->cp_haltset
, cpu_sid
);
737 * If "cpu" is halted in mwait, then wake it up clearing its halted bit in
738 * advance. Otherwise, see if other CPUs in the cpu partition are halted and
739 * need to be woken up so that they can steal the thread we placed on this CPU.
740 * This function is only used on MP systems.
743 cpu_wakeup_mwait(cpu_t
*cp
, int bound
)
747 processorid_t cpu_sid
;
749 cpu_part
= cp
->cpu_part
;
750 cpu_sid
= cp
->cpu_seqid
;
753 * Clear the halted bit for that CPU since it will be woken up
756 if (bitset_in_set(&cpu_part
->cp_haltset
, cpu_sid
)) {
758 * Clear the halted bit for that CPU since it will be
761 bitset_atomic_del(&cpu_part
->cp_haltset
, cpu_sid
);
763 * We may find the current CPU present in the halted cpuset
764 * if we're in the context of an interrupt that occurred
765 * before we had a chance to clear our bit in cpu_idle().
766 * Waking ourself is obviously unnecessary, since if
767 * we're here, we're not halted.
769 * monitor/mwait wakeup via writing to our cache line is
770 * harmless and less expensive than always checking if we
771 * are waking ourself which is an uncommon case.
773 MWAIT_WAKEUP(cp
); /* write to monitored line */
777 * This cpu isn't halted, but it's idle or undergoing a
778 * context switch. No need to awaken anyone else.
780 if (cp
->cpu_thread
== cp
->cpu_idle_thread
||
781 cp
->cpu_disp_flags
& CPU_DISP_DONTSTEAL
)
786 * No need to wake up other CPUs if the thread we just enqueued
789 if (bound
|| ncpus
== 1)
793 * See if there's any other halted CPUs. If there are, then
794 * select one, and awaken it.
795 * It's possible that after we find a CPU, somebody else
796 * will awaken it before we get the chance.
797 * In that case, look again.
800 cpu_found
= bitset_find(&cpu_part
->cp_haltset
);
801 if (cpu_found
== (uint_t
)-1)
803 } while (bitset_atomic_test_and_del(&cpu_part
->cp_haltset
,
807 * Do not check if cpu_found is ourself as monitor/mwait
810 MWAIT_WAKEUP(cpu_seq
[cpu_found
]); /* write to monitored line */
814 void (*cpu_pause_handler
)(volatile char *) = NULL
;
817 mp_disable_intr(int cpun
)
820 * switch to the offline cpu
824 * raise ipl to just below cross call
826 splx(XC_SYS_PIL
- 1);
828 * set base spl to prevent the next swtch to idle from
829 * lowering back to ipl 0
831 CPU
->cpu_intr_actv
|= (1 << (XC_SYS_PIL
- 1));
834 return (DDI_SUCCESS
);
838 mp_enable_intr(int cpun
)
841 * switch to the online cpu
845 * clear the interrupt active mask
847 CPU
->cpu_intr_actv
&= ~(1 << (XC_SYS_PIL
- 1));
854 mach_get_platform(int owner
)
862 srv_opsp
= (void **)mach_set
[0];
863 clt_opsp
= (void **)mach_set
[owner
];
864 if (mach_ver
[owner
] == (ushort_t
)PSM_INFO_VER01
)
865 total_ops
= sizeof (struct psm_ops_ver01
) /
866 sizeof (void (*)(void));
867 else if (mach_ver
[owner
] == (ushort_t
)PSM_INFO_VER01_1
)
868 /* no psm_notify_func */
869 total_ops
= OFFSETOF(struct psm_ops
, psm_notify_func
) /
870 sizeof (void (*)(void));
871 else if (mach_ver
[owner
] == (ushort_t
)PSM_INFO_VER01_2
)
872 /* no psm_timer funcs */
873 total_ops
= OFFSETOF(struct psm_ops
, psm_timer_reprogram
) /
874 sizeof (void (*)(void));
875 else if (mach_ver
[owner
] == (ushort_t
)PSM_INFO_VER01_3
)
876 /* no psm_preshutdown function */
877 total_ops
= OFFSETOF(struct psm_ops
, psm_preshutdown
) /
878 sizeof (void (*)(void));
879 else if (mach_ver
[owner
] == (ushort_t
)PSM_INFO_VER01_4
)
880 /* no psm_intr_ops function */
881 total_ops
= OFFSETOF(struct psm_ops
, psm_intr_ops
) /
882 sizeof (void (*)(void));
883 else if (mach_ver
[owner
] == (ushort_t
)PSM_INFO_VER01_5
)
884 /* no psm_state function */
885 total_ops
= OFFSETOF(struct psm_ops
, psm_state
) /
886 sizeof (void (*)(void));
887 else if (mach_ver
[owner
] == (ushort_t
)PSM_INFO_VER01_6
)
888 /* no psm_cpu_ops function */
889 total_ops
= OFFSETOF(struct psm_ops
, psm_cpu_ops
) /
890 sizeof (void (*)(void));
892 total_ops
= sizeof (struct psm_ops
) / sizeof (void (*)(void));
895 * Save the version of the PSM module, in case we need to
896 * behave differently based on version.
898 mach_ver
[0] = mach_ver
[owner
];
900 for (i
= 0; i
< total_ops
; i
++)
901 if (clt_opsp
[i
] != NULL
)
902 srv_opsp
[i
] = clt_opsp
[i
];
906 mach_construct_info()
909 int mach_cnt
[PSM_OWN_OVERRIDE
+1] = {0};
910 int conflict_owner
= 0;
912 if (psmsw
->psw_forw
== psmsw
)
913 panic("No valid PSM modules found");
914 mutex_enter(&psmsw_lock
);
915 for (swp
= psmsw
->psw_forw
; swp
!= psmsw
; swp
= swp
->psw_forw
) {
916 if (!(swp
->psw_flag
& PSM_MOD_IDENTIFY
))
918 mach_set
[swp
->psw_infop
->p_owner
] = swp
->psw_infop
->p_ops
;
919 mach_ver
[swp
->psw_infop
->p_owner
] = swp
->psw_infop
->p_version
;
920 mach_cnt
[swp
->psw_infop
->p_owner
]++;
922 mutex_exit(&psmsw_lock
);
924 mach_get_platform(PSM_OWN_SYS_DEFAULT
);
926 /* check to see are there any conflicts */
927 if (mach_cnt
[PSM_OWN_EXCLUSIVE
] > 1)
928 conflict_owner
= PSM_OWN_EXCLUSIVE
;
929 if (mach_cnt
[PSM_OWN_OVERRIDE
] > 1)
930 conflict_owner
= PSM_OWN_OVERRIDE
;
931 if (conflict_owner
) {
932 /* remove all psm modules except uppc */
934 "Conflicts detected on the following PSM modules:");
935 mutex_enter(&psmsw_lock
);
936 for (swp
= psmsw
->psw_forw
; swp
!= psmsw
; swp
= swp
->psw_forw
) {
937 if (swp
->psw_infop
->p_owner
== conflict_owner
)
938 cmn_err(CE_WARN
, "%s ",
939 swp
->psw_infop
->p_mach_idstring
);
941 mutex_exit(&psmsw_lock
);
943 "Setting the system back to SINGLE processor mode!");
945 "Please edit /etc/mach to remove the invalid PSM module.");
949 if (mach_set
[PSM_OWN_EXCLUSIVE
])
950 mach_get_platform(PSM_OWN_EXCLUSIVE
);
952 if (mach_set
[PSM_OWN_OVERRIDE
])
953 mach_get_platform(PSM_OWN_OVERRIDE
);
959 struct psm_ops
*pops
;
961 mach_construct_info();
965 /* register the interrupt and clock initialization rotuines */
966 picinitf
= mach_picinit
;
967 clkinitf
= mach_clkinit
;
968 psm_get_clockirq
= pops
->psm_get_clockirq
;
970 /* register the interrupt setup code */
971 slvltovect
= mach_softlvl_to_vect
;
972 addspl
= pops
->psm_addspl
;
973 delspl
= pops
->psm_delspl
;
975 if (pops
->psm_translate_irq
)
976 psm_translate_irq
= pops
->psm_translate_irq
;
977 if (pops
->psm_intr_ops
)
978 psm_intr_ops
= pops
->psm_intr_ops
;
980 #if defined(PSMI_1_2) || defined(PSMI_1_3) || defined(PSMI_1_4)
982 * Time-of-day functionality now handled in TOD modules.
983 * (Warn about PSM modules that think that we're going to use
984 * their ops vectors.)
986 if (pops
->psm_tod_get
)
987 cmn_err(CE_WARN
, "obsolete psm_tod_get op %p",
988 (void *)pops
->psm_tod_get
);
990 if (pops
->psm_tod_set
)
991 cmn_err(CE_WARN
, "obsolete psm_tod_set op %p",
992 (void *)pops
->psm_tod_set
);
995 if (pops
->psm_notify_error
) {
996 psm_notify_error
= mach_notify_error
;
997 notify_error
= pops
->psm_notify_error
;
1000 (*pops
->psm_softinit
)();
1003 * Initialize the dispatcher's function hooks to enable CPU halting
1004 * when idle. Set both the deep-idle and non-deep-idle hooks.
1006 * Assume we can use power saving deep-idle loop cpu_idle_adaptive.
1007 * Platform deep-idle driver will reset our idle loop to
1008 * non_deep_idle_cpu if power saving deep-idle feature is not available.
1010 * Do not use monitor/mwait if idle_cpu_use_hlt is not set(spin idle)
1011 * or idle_cpu_prefer_mwait is not set.
1012 * Allocate monitor/mwait buffer for cpu0.
1014 non_deep_idle_disp_enq_thread
= disp_enq_thread
;
1015 if (idle_cpu_use_hlt
) {
1016 idle_cpu
= cpu_idle_adaptive
;
1017 CPU
->cpu_m
.mcpu_idle_cpu
= cpu_idle
;
1018 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) &&
1019 idle_cpu_prefer_mwait
) {
1020 if (cpuid_mwait_alloc(CPU
) != 0) {
1022 cmn_err(CE_NOTE
, "Using hlt idle. Cannot "
1023 "handle cpu 0 mwait size.");
1025 idle_cpu_prefer_mwait
= 0;
1026 CPU
->cpu_m
.mcpu_idle_cpu
= cpu_idle
;
1028 CPU
->cpu_m
.mcpu_idle_cpu
= cpu_idle_mwait
;
1031 CPU
->cpu_m
.mcpu_idle_cpu
= cpu_idle
;
1033 non_deep_idle_cpu
= CPU
->cpu_m
.mcpu_idle_cpu
;
1036 * Disable power saving deep idle loop?
1038 if (idle_cpu_no_deep_c
) {
1039 idle_cpu
= non_deep_idle_cpu
;
1049 struct psm_ops
*pops
;
1050 processorid_t cpu_id
;
1055 CPUSET_ZERO(cpumask
);
1058 cpu_id
= (*pops
->psm_get_next_processorid
)(cpu_id
);
1060 * Only add boot_ncpus CPUs to mp_cpus. Other CPUs will be handled
1061 * by CPU DR driver at runtime.
1063 for (cnt
= 0; cpu_id
!= -1 && cnt
< boot_ncpus
; cnt
++) {
1064 CPUSET_ADD(cpumask
, cpu_id
);
1065 cpu_id
= (*pops
->psm_get_next_processorid
)(cpu_id
);
1070 /* MP related routines */
1071 ap_mlsetup
= pops
->psm_post_cpu_start
;
1072 send_dirintf
= pops
->psm_send_ipi
;
1074 /* optional MP related routines */
1075 if (pops
->psm_shutdown
)
1076 psm_shutdownf
= pops
->psm_shutdown
;
1077 if (pops
->psm_preshutdown
)
1078 psm_preshutdownf
= pops
->psm_preshutdown
;
1079 if (pops
->psm_notify_func
)
1080 psm_notifyf
= pops
->psm_notify_func
;
1081 if (pops
->psm_set_idlecpu
)
1082 psm_set_idle_cpuf
= pops
->psm_set_idlecpu
;
1083 if (pops
->psm_unset_idlecpu
)
1084 psm_unset_idle_cpuf
= pops
->psm_unset_idlecpu
;
1086 psm_clkinit
= pops
->psm_clkinit
;
1088 if (pops
->psm_timer_reprogram
)
1089 psm_timer_reprogram
= pops
->psm_timer_reprogram
;
1091 if (pops
->psm_timer_enable
)
1092 psm_timer_enable
= pops
->psm_timer_enable
;
1094 if (pops
->psm_timer_disable
)
1095 psm_timer_disable
= pops
->psm_timer_disable
;
1097 if (pops
->psm_post_cyclic_setup
)
1098 psm_post_cyclic_setup
= pops
->psm_post_cyclic_setup
;
1100 if (pops
->psm_state
)
1101 psm_state
= pops
->psm_state
;
1104 * Set these vectors here so they can be used by Suspend/Resume
1107 if (pops
->psm_disable_intr
)
1108 psm_disable_intr
= pops
->psm_disable_intr
;
1109 if (pops
->psm_enable_intr
)
1110 psm_enable_intr
= pops
->psm_enable_intr
;
1112 /* check for multiple CPUs */
1113 if (cnt
< 2 && plat_dr_support_cpu() == B_FALSE
)
1116 /* check for MP platforms */
1117 if (pops
->psm_cpu_start
== NULL
)
1121 * Set the dispatcher hook to enable cpu "wake up"
1122 * when a thread becomes runnable.
1124 if (idle_cpu_use_hlt
) {
1125 disp_enq_thread
= cpu_wakeup
;
1126 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) &&
1127 idle_cpu_prefer_mwait
)
1128 disp_enq_thread
= cpu_wakeup_mwait
;
1129 non_deep_idle_disp_enq_thread
= disp_enq_thread
;
1132 psm_get_ipivect
= pops
->psm_get_ipivect
;
1134 (void) add_avintr(NULL
, XC_HI_PIL
, xc_serv
, "xc_intr",
1135 (*pops
->psm_get_ipivect
)(XC_HI_PIL
, PSM_INTR_IPI_HI
),
1136 NULL
, NULL
, NULL
, NULL
);
1138 (void) (*pops
->psm_get_ipivect
)(XC_CPUPOKE_PIL
, PSM_INTR_POKE
);
1144 struct psm_ops
*pops
;
1148 /* register the interrupt handlers */
1149 setlvl
= pops
->psm_intr_enter
;
1150 setlvlx
= pops
->psm_intr_exit
;
1152 /* initialize the interrupt hardware */
1153 (*pops
->psm_picinit
)();
1155 /* set interrupt mask for current ipl */
1156 setspl
= pops
->psm_setspl
;
1158 setspl(CPU
->cpu_pri
);
1161 uint_t cpu_freq
; /* MHz */
1162 uint64_t cpu_freq_hz
; /* measured (in hertz) */
1164 #define MEGA_HZ 1000000
1168 mach_calchz(uint32_t pit_counter
, uint64_t *processor_clks
)
1172 if ((pit_counter
== 0) || (*processor_clks
== 0) ||
1173 (*processor_clks
> (((uint64_t)-1) / PIT_HZ
)))
1176 cpu_hz
= ((uint64_t)PIT_HZ
* *processor_clks
) / pit_counter
;
1183 mach_getcpufreq(void)
1185 uint32_t pit_counter
;
1186 uint64_t processor_clks
;
1188 if (is_x86_feature(x86_featureset
, X86FSET_TSC
)) {
1190 * We have a TSC. freq_tsc() knows how to measure the number
1191 * of clock cycles sampled against the PIT.
1193 ulong_t flags
= clear_int_flag();
1194 processor_clks
= freq_tsc(&pit_counter
);
1195 restore_int_flag(flags
);
1196 return (mach_calchz(pit_counter
, &processor_clks
));
1197 } else if (x86_vendor
== X86_VENDOR_Cyrix
|| x86_type
== X86_TYPE_P5
) {
1198 #if defined(__amd64)
1199 panic("mach_getcpufreq: no TSC!");
1200 #elif defined(__i386)
1202 * We are a Cyrix based on a 6x86 core or an Intel Pentium
1203 * for which freq_notsc() knows how to measure the number of
1204 * elapsed clock cycles sampled against the PIT
1206 ulong_t flags
= clear_int_flag();
1207 processor_clks
= freq_notsc(&pit_counter
);
1208 restore_int_flag(flags
);
1209 return (mach_calchz(pit_counter
, &processor_clks
));
1213 /* We do not know how to calculate cpu frequency for this cpu. */
1218 * If the clock speed of a cpu is found to be reported incorrectly, do not add
1219 * to this array, instead improve the accuracy of the algorithm that determines
1220 * the clock speed of the processor or extend the implementation to support the
1221 * vendor as appropriate. This is here only to support adjusting the speed on
1222 * older slower processors that mach_fixcpufreq() would not be able to account
1225 static int x86_cpu_freq
[] = { 60, 75, 80, 90, 120, 160, 166, 175, 180, 233 };
1228 * On fast processors the clock frequency that is measured may be off by
1229 * a few MHz from the value printed on the part. This is a combination of
1230 * the factors that for such fast parts being off by this much is within
1231 * the tolerances for manufacture and because of the difficulties in the
1232 * measurement that can lead to small error. This function uses some
1233 * heuristics in order to tweak the value that was measured to match what
1234 * is most likely printed on the part.
1237 * AMD Athlon 1000 mhz measured as 998 mhz
1238 * Intel Pentium III Xeon 733 mhz measured as 731 mhz
1239 * Intel Pentium IV 1500 mhz measured as 1495mhz
1241 * If in the future this function is no longer sufficient to correct
1242 * for the error in the measurement, then the algorithm used to perform
1243 * the measurement will have to be improved in order to increase accuracy
1244 * rather than adding horrible and questionable kludges here.
1246 * This is called after the cyclics subsystem because of the potential
1247 * that the heuristics within may give a worse estimate of the clock
1248 * frequency than the value that was measured.
1251 mach_fixcpufreq(void)
1253 uint32_t freq
, mul
, near66
, delta66
, near50
, delta50
, fixed
, delta
, i
;
1255 freq
= (uint32_t)cpu_freq
;
1258 * Find the nearest integer multiple of 200/3 (about 66) MHz to the
1259 * measured speed taking into account that the 667 MHz parts were
1260 * the first to round-up.
1262 mul
= (uint32_t)((3 * (uint64_t)freq
+ 100) / 200);
1263 near66
= (uint32_t)((200 * (uint64_t)mul
+ ((mul
>= 10) ? 1 : 0)) / 3);
1264 delta66
= (near66
> freq
) ? (near66
- freq
) : (freq
- near66
);
1266 /* Find the nearest integer multiple of 50 MHz to the measured speed */
1267 mul
= (freq
+ 25) / 50;
1269 delta50
= (near50
> freq
) ? (near50
- freq
) : (freq
- near50
);
1271 /* Find the closer of the two */
1272 if (delta66
< delta50
) {
1280 if (fixed
> INT_MAX
)
1284 * Some older parts have a core clock frequency that is not an
1285 * integral multiple of 50 or 66 MHz. Check if one of the old
1286 * clock frequencies is closer to the measured value than any
1287 * of the integral multiples of 50 an 66, and if so set fixed
1288 * and delta appropriately to represent the closest value.
1290 i
= sizeof (x86_cpu_freq
) / sizeof (int);
1294 if (x86_cpu_freq
[i
] <= freq
) {
1295 mul
= freq
- x86_cpu_freq
[i
];
1298 fixed
= x86_cpu_freq
[i
];
1305 mul
= x86_cpu_freq
[i
] - freq
;
1308 fixed
= x86_cpu_freq
[i
];
1314 * Set a reasonable maximum for how much to correct the measured
1315 * result by. This check is here to prevent the adjustment made
1316 * by this function from being more harm than good. It is entirely
1317 * possible that in the future parts will be made that are not
1318 * integral multiples of 66 or 50 in clock frequency or that
1319 * someone may overclock a part to some odd frequency. If the
1320 * measured value is farther from the corrected value than
1321 * allowed, then assume the corrected value is in error and use
1322 * the measured value.
1327 cpu_freq
= (int)fixed
;
1332 machhztomhz(uint64_t cpu_freq_hz
)
1336 /* Round to nearest MHZ */
1337 cpu_mhz
= (cpu_freq_hz
+ (MEGA_HZ
/ 2)) / MEGA_HZ
;
1339 if (cpu_mhz
> INT_MAX
)
1342 return ((int)cpu_mhz
);
1348 mach_clkinit(int preferred_mode
, int *set_mode
)
1350 struct psm_ops
*pops
;
1355 cpu_freq_hz
= mach_getcpufreq();
1357 cpu_freq
= machhztomhz(cpu_freq_hz
);
1359 if (!is_x86_feature(x86_featureset
, X86FSET_TSC
) || (cpu_freq
== 0))
1360 tsc_gethrtime_enable
= 0;
1362 if (tsc_gethrtime_enable
) {
1363 tsc_hrtimeinit(cpu_freq_hz
);
1366 if (pops
->psm_hrtimeinit
)
1367 (*pops
->psm_hrtimeinit
)();
1368 gethrtimef
= pops
->psm_gethrtime
;
1369 gethrtimeunscaledf
= gethrtimef
;
1370 /* scalehrtimef will remain dummy */
1375 if (mach_ver
[0] >= PSM_INFO_VER01_3
) {
1376 if (preferred_mode
== TIMER_ONESHOT
) {
1378 resolution
= (*pops
->psm_clkinit
)(0);
1379 if (resolution
!= 0) {
1380 *set_mode
= TIMER_ONESHOT
;
1381 return (resolution
);
1386 * either periodic mode was requested or could not set to
1389 resolution
= (*pops
->psm_clkinit
)(hz
);
1391 * psm should be able to do periodic, so we do not check
1392 * for return value of psm_clkinit here.
1394 *set_mode
= TIMER_PERIODIC
;
1395 return (resolution
);
1398 * PSMI interface prior to PSMI_3 does not define a return
1399 * value for psm_clkinit, so the return value is ignored.
1401 (void) (*pops
->psm_clkinit
)(hz
);
1402 *set_mode
= TIMER_PERIODIC
;
1403 return (nsec_per_tick
);
1410 mach_softlvl_to_vect(int ipl
)
1412 setsoftint
= av_set_softint_pending
;
1413 kdisetsoftint
= kdi_av_set_softint_pending
;
1415 return (PSM_SV_SOFTWARE
);
1420 * This is here to allow us to simulate cpus that refuse to start.
1422 cpuset_t cpufailset
;
1426 mach_cpu_start(struct cpu
*cp
, void *ctx
)
1428 struct psm_ops
*pops
= mach_set
[0];
1429 processorid_t id
= cp
->cpu_id
;
1432 if (CPU_IN_SET(cpufailset
, id
))
1435 return ((*pops
->psm_cpu_start
)(id
, ctx
));
1439 mach_cpuid_start(processorid_t id
, void *ctx
)
1441 struct psm_ops
*pops
= mach_set
[0];
1444 if (CPU_IN_SET(cpufailset
, id
))
1447 return ((*pops
->psm_cpu_start
)(id
, ctx
));
1451 mach_cpu_stop(cpu_t
*cp
, void *ctx
)
1453 struct psm_ops
*pops
= mach_set
[0];
1454 psm_cpu_request_t request
;
1456 if (pops
->psm_cpu_ops
== NULL
) {
1460 ASSERT(cp
->cpu_id
!= -1);
1461 request
.pcr_cmd
= PSM_CPU_STOP
;
1462 request
.req
.cpu_stop
.cpuid
= cp
->cpu_id
;
1463 request
.req
.cpu_stop
.ctx
= ctx
;
1465 return ((*pops
->psm_cpu_ops
)(&request
));
1469 mach_cpu_add(mach_cpu_add_arg_t
*argp
, processorid_t
*cpuidp
)
1472 struct psm_ops
*pops
= mach_set
[0];
1473 psm_cpu_request_t request
;
1475 if (pops
->psm_cpu_ops
== NULL
) {
1479 request
.pcr_cmd
= PSM_CPU_ADD
;
1480 request
.req
.cpu_add
.argp
= argp
;
1481 request
.req
.cpu_add
.cpuid
= -1;
1482 rc
= (*pops
->psm_cpu_ops
)(&request
);
1484 ASSERT(request
.req
.cpu_add
.cpuid
!= -1);
1485 *cpuidp
= request
.req
.cpu_add
.cpuid
;
1492 mach_cpu_remove(processorid_t cpuid
)
1494 struct psm_ops
*pops
= mach_set
[0];
1495 psm_cpu_request_t request
;
1497 if (pops
->psm_cpu_ops
== NULL
) {
1501 request
.pcr_cmd
= PSM_CPU_REMOVE
;
1502 request
.req
.cpu_remove
.cpuid
= cpuid
;
1504 return ((*pops
->psm_cpu_ops
)(&request
));
1508 * Default handler to create device node for CPU.
1509 * One reference count will be held on created device node.
1512 mach_cpu_create_devinfo(cpu_t
*cp
, dev_info_t
**dipp
)
1516 static kmutex_t cpu_node_lock
;
1517 static dev_info_t
*cpu_nex_devi
= NULL
;
1520 ASSERT(dipp
!= NULL
);
1523 if (cpu_nex_devi
== NULL
) {
1524 mutex_enter(&cpu_node_lock
);
1525 /* First check whether cpus exists. */
1526 cpu_nex_devi
= ddi_find_devinfo("cpus", -1, 0);
1527 /* Create cpus if it doesn't exist. */
1528 if (cpu_nex_devi
== NULL
) {
1529 ndi_devi_enter(ddi_root_node(), &circ
);
1530 rv
= ndi_devi_alloc(ddi_root_node(), "cpus",
1531 (pnode_t
)DEVI_SID_NODEID
, &dip
);
1532 if (rv
!= NDI_SUCCESS
) {
1533 mutex_exit(&cpu_node_lock
);
1535 "?failed to create cpu nexus device.\n");
1536 return (PSM_FAILURE
);
1538 ASSERT(dip
!= NULL
);
1539 (void) ndi_devi_online(dip
, 0);
1540 ndi_devi_exit(ddi_root_node(), circ
);
1543 mutex_exit(&cpu_node_lock
);
1547 * create a child node for cpu identified as 'cpu_id'
1549 ndi_devi_enter(cpu_nex_devi
, &circ
);
1550 dip
= ddi_add_child(cpu_nex_devi
, "cpu", DEVI_SID_NODEID
, -1);
1553 "?failed to create device node for cpu%d.\n", cp
->cpu_id
);
1557 (void) ndi_hold_devi(dip
);
1560 ndi_devi_exit(cpu_nex_devi
, circ
);
1566 * Create cpu device node in device tree and online it.
1567 * Return created dip with reference count held if requested.
1570 mach_cpu_create_device_node(struct cpu
*cp
, dev_info_t
**dipp
)
1573 dev_info_t
*dip
= NULL
;
1575 ASSERT(psm_cpu_create_devinfo
!= NULL
);
1576 rv
= psm_cpu_create_devinfo(cp
, &dip
);
1577 if (rv
== PSM_SUCCESS
) {
1578 cpuid_set_cpu_properties(dip
, cp
->cpu_id
, cp
->cpu_m
.mcpu_cpi
);
1579 /* Recursively attach driver for parent nexus device. */
1580 if (i_ddi_attach_node_hierarchy(ddi_get_parent(dip
)) ==
1582 /* Configure cpu itself and descendants. */
1583 (void) ndi_devi_online(dip
,
1584 NDI_ONLINE_ATTACH
| NDI_CONFIG
);
1589 (void) ndi_rele_devi(dip
);
1597 * The dipp contains one of following values on return:
1598 * - NULL if no device node found
1599 * - pointer to device node if found
1602 mach_cpu_get_device_node(struct cpu
*cp
, dev_info_t
**dipp
)
1605 if (psm_cpu_get_devinfo
!= NULL
) {
1606 if (psm_cpu_get_devinfo(cp
, dipp
) == PSM_SUCCESS
) {
1607 return (PSM_SUCCESS
);
1611 return (PSM_FAILURE
);
1616 mach_translate_irq(dev_info_t
*dip
, int irqno
)
1618 return (irqno
); /* default to NO translation */
1622 mach_notify_error(int level
, char *errmsg
)
1625 * SL_FATAL is pass in once panicstr is set, deliver it
1626 * as CE_PANIC. Also, translate SL_ codes back to CE_
1627 * codes for the psmi handler
1629 if (level
& SL_FATAL
)
1630 (*notify_error
)(CE_PANIC
, errmsg
);
1631 else if (level
& SL_WARN
)
1632 (*notify_error
)(CE_WARN
, errmsg
);
1633 else if (level
& SL_NOTE
)
1634 (*notify_error
)(CE_NOTE
, errmsg
);
1635 else if (level
& SL_CONSOLE
)
1636 (*notify_error
)(CE_CONT
, errmsg
);
1640 * It provides the default basic intr_ops interface for the new DDI
1641 * interrupt framework if the PSM doesn't have one.
1644 * dip - pointer to the dev_info structure of the requested device
1645 * hdlp - pointer to the internal interrupt handle structure for the
1646 * requested interrupt
1647 * intr_op - opcode for this call
1648 * result - pointer to the integer that will hold the result to be
1649 * passed back if return value is PSM_SUCCESS
1652 * return value is either PSM_SUCCESS or PSM_FAILURE
1655 mach_intr_ops(dev_info_t
*dip
, ddi_intr_handle_impl_t
*hdlp
,
1656 psm_intr_op_t intr_op
, int *result
)
1658 struct intrspec
*ispec
;
1661 case PSM_INTR_OP_CHECK_MSI
:
1662 *result
= hdlp
->ih_type
& ~(DDI_INTR_TYPE_MSI
|
1663 DDI_INTR_TYPE_MSIX
);
1665 case PSM_INTR_OP_ALLOC_VECTORS
:
1666 if (hdlp
->ih_type
== DDI_INTR_TYPE_FIXED
)
1671 case PSM_INTR_OP_FREE_VECTORS
:
1673 case PSM_INTR_OP_NAVAIL_VECTORS
:
1674 if (hdlp
->ih_type
== DDI_INTR_TYPE_FIXED
)
1679 case PSM_INTR_OP_XLATE_VECTOR
:
1680 ispec
= ((ihdl_plat_t
*)hdlp
->ih_private
)->ip_ispecp
;
1681 *result
= psm_translate_irq(dip
, ispec
->intrspec_vec
);
1683 case PSM_INTR_OP_GET_CAP
:
1686 case PSM_INTR_OP_GET_PENDING
:
1687 case PSM_INTR_OP_CLEAR_MASK
:
1688 case PSM_INTR_OP_SET_MASK
:
1689 case PSM_INTR_OP_GET_SHARED
:
1690 case PSM_INTR_OP_SET_PRI
:
1691 case PSM_INTR_OP_SET_CAP
:
1692 case PSM_INTR_OP_SET_CPU
:
1693 case PSM_INTR_OP_GET_INTR
:
1695 return (PSM_FAILURE
);
1697 return (PSM_SUCCESS
);
1700 * Return 1 if CMT load balancing policies should be
1701 * implemented across instances of the specified hardware
1702 * sharing relationship.
1705 pg_cmt_load_bal_hw(pghw_type_t hw
)
1707 if (hw
== PGHW_IPIPE
||
1709 hw
== PGHW_PROCNODE
||
1716 * Return 1 if thread affinity polices should be implemented
1717 * for instances of the specifed hardware sharing relationship.
1720 pg_cmt_affinity_hw(pghw_type_t hw
)
1722 if (hw
== PGHW_CACHE
)
1729 * Return number of counter events requested to measure hardware capacity and
1730 * utilization and setup CPC requests for specified CPU as needed
1732 * May return 0 when platform or processor specific code knows that no CPC
1733 * events should be programmed on this CPU or -1 when platform or processor
1734 * specific code doesn't know which counter events are best to use and common
1735 * code should decide for itself
1738 /* LINTED E_FUNC_ARG_UNUSED */
1739 cu_plat_cpc_init(cpu_t
*cp
, kcpc_request_list_t
*reqs
, int nreqs
)
1741 const char *impl_name
;
1744 * Return error if pcbe_ops not set
1746 if (pcbe_ops
== NULL
)
1750 * Return that no CPC events should be programmed on hyperthreaded
1751 * Pentium 4 and return error for all other x86 processors to tell
1752 * common code to decide what counter events to program on those CPUs
1753 * for measuring hardware capacity and utilization
1755 impl_name
= pcbe_ops
->pcbe_impl_name();
1756 if (impl_name
!= NULL
&& strcmp(impl_name
, PCBE_IMPL_NAME_P4HT
) == 0)