include/sys/dma_i8237A.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #ifndef _SYS_DMA_I8237A_H
  28 #define _SYS_DMA_I8237A_H
  29
  30 #pragma ident   "%Z%%M% %I%     %E% SMI"
  31
  32 #ifdef  __cplusplus
  33 extern "C" {
  34 #endif
  35
  36 /*      Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
  37 /*      Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T   */
  38 /*      All Rights Reserved     */
  39
  40 #define D37A_MAX_CHAN   8
  41 #define D37A_DFR_ALIGN  0xf
  42 #define D37A_MIN_CHAN   0x0
  43
  44 /*
  45  * Defines for PC AT DMA controllers.
  46  */
  47
  48 /*
  49  * The PC/AT has two Intel 8237A-5 DMA controllers that provide 8 channels
  50  */
  51 #define DMA_0WCNT       0x01    /* Channel  word count */
  52 #define DMA_1WCNT       0x03    /* Channel  word count */
  53 #define DMA_2WCNT       0x05    /* Channel  word count */
  54 #define DMA_3WCNT       0x07    /* Channel  word count */
  55 #define DMA_4WCNT       0xC2    /* (RESERVED) Channel  word count */
  56 #define DMA_5WCNT       0xC6    /* Channel  word count */
  57 #define DMA_6WCNT       0xCA    /* Channel  word count */
  58 #define DMA_7WCNT       0xCE    /* Channel  word count */
  59
  60 #define DMA_0ADR        0x00    /* Channel  address register */
  61 #define DMA_1ADR        0x02    /* Channel  address register */
  62 #define DMA_2ADR        0x04    /* Channel  address register */
  63 #define DMA_3ADR        0x06    /* Channel  address register */
  64 #define DMA_4ADR        0xC0    /* (RESERVED) Channel  address register */
  65 #define DMA_5ADR        0xC4    /* Channel  address register */
  66 #define DMA_6ADR        0xC8    /* Channel  address register */
  67 #define DMA_7ADR        0xCC    /* Channel  address register */
  68
  69 /*
  70  * The Intel DMA controllers are augmented with 8-bit page registers
  71  * for each channel, allowing access to a 16MB address space.
  72  */
  73 #define DMA_0PAGE       0x87    /* Channel 0 address extension reg */
  74 #define DMA_1PAGE       0x83    /* Channel 1 address extension reg */
  75 #define DMA_2PAGE       0x81    /* Channel 2 address extension reg */
  76 #define DMA_3PAGE       0x82    /* Channel 3 address extension reg */
  77 #define DMA_4PAGE       0       /* dummy address for dma chan. 4 page reg. */
  78 #define DMA_5PAGE       0x8B    /* Channel 5 address extension reg */
  79 #define DMA_6PAGE       0x89    /* Channel 6 address extension reg */
  80 #define DMA_7PAGE       0x8A    /* Channel 7 address extension reg */
  81
  82 /*
  83  * The EISA has an 8-bit high-page register for each channel
  84  * for access to a 32-bit address space.
  85  */
  86 #define DMA_0HPG        0x487   /* port address for dma channel 0 */
  87                                 /* high page reg */
  88 #define DMA_1HPG        0x483   /* port address for dma channel 1 */
  89                                 /* high page reg */
  90 #define DMA_2HPG        0x481   /* port address for dma channel 2 */
  91                                 /* high page reg */
  92 #define DMA_3HPG        0x482   /* port address for dma channel 3 */
  93                                 /* high page reg */
  94 #define DMA_4HPG        0       /* dummy address for dma channel 4 */
  95                                 /* high page reg */
  96 #define DMA_5HPG        0x48B   /* port address for dma channel 5 */
  97                                 /* high page reg */
  98 #define DMA_6HPG        0x489   /* port address for dma channel 6 */
  99                                 /* high page reg */
 100 #define DMA_7HPG        0x48A   /* port address for dma channel 7 */
 101                                 /* high page reg */
 102
 103 /*
 104  * The EISA has an 8-bit high-count register for each channel
 105  * for xfer sizes up to 16MB.
 106  */
 107 #define DMA_0XCNT       0x401   /* chan. 0 base and current count high */
 108 #define DMA_1XCNT       0x403   /* chan. 1 base and current count high */
 109 #define DMA_2XCNT       0x405   /* chan. 2 base and current count high */
 110 #define DMA_3XCNT       0x407   /* chan. 3 base and current count high */
 111 #define DMA_4XCNT       0       /* dummy chan. 4 base and current count high */
 112 #define DMA_5XCNT       0x4C6   /* chan. 5 base and current count high */
 113 #define DMA_6XCNT       0x4CA   /* chan. 6 base and current count high */
 114 #define DMA_7XCNT       0x4CE   /* chan. 7 base and current count high */
 115
 116 /*
 117  * I/O port addresses for controller 1
 118  */
 119 #define DMAC1_CMD       0x08    /* Command reg */
 120 #define DMAC1_REQ       0x09    /* request reg */
 121 #define DMAC1_STAT      0x08    /* Status reg */
 122 #define DMAC1_MASK      0x0A    /* Mask set/reset register */
 123 #define DMAC1_MODE      0x0B    /* Mode reg */
 124 #define DMAC1_CLFF      0x0C    /* Clear byte pointer first/last flip-flop */
 125 #define DMA1RTRWMC      0x0D    /* read temp reg/write master clear */
 126 #define DMA1CMR         0x0E    /* clear mask register */
 127 #define DMAC1_ALLMASK   0x0F    /* Mask all registers */
 128 #define DMAC1_SCM       0x40A   /* set chain mode */
 129 #define DMAC1_EWM       0x40B   /* extended write mode */
 130
 131 /*
 132  * I/O port addresses for controller 2
 133  */
 134 #define DMAC2_CMD       0xD0    /* Command reg */
 135 #define DMAC2_STAT      0xD0    /* Status reg */
 136 #define DMAC2_REQ       0xD2    /* request reg */
 137 #define DMAC2_MASK      0xD4    /* Mask set/reset register */
 138 #define DMAC2_MODE      0xD6    /* Mode reg */
 139 #define DMAC2_CLFF      0xD8    /* Clear byte pointer first/last flip-flop */
 140 #define DMA2RTRWMC      0xDA    /* read temp reg/write master clear */
 141 #define DMA2CMR         0xDC    /* clear mask register */
 142 #define DMAC2_ALLMASK   0xDE    /* Mask all registers */
 143 #define DMAC2_SCM       0x4D4   /* set chain mode */
 144 #define DMAC2_EWM       0x4D6   /* extended write mode */
 145
 146 /*
 147  * Write-only Command register definitions.
 148  */
 149 #define DMACMD_MEM_TO_MEM       0x01    /* memory-to-memory copy (1=enable) */
 150 #define DMACMD_CHAN_HOLD        0x02    /* Channel 0 address hold (1=enable) */
 151 #define DMACMD_CTLR_ENABLE      0x04    /* Controller disable (0=enabled) */
 152 #define DMACMD_TIMING           0x08    /* normal/compressed timing (0=nrml) */
 153 #define DMACMD_FIX_PRIO         0x10    /* fixed/rotating priority (0=fixed) */
 154 #define DMACMD_WRT_SELECT       0x20    /* late/ext write selection (1=ext) */
 155 #define DMACMD_DREQ_LEVEL       0x40    /* DREQ sense active (0=actv. high) */
 156 #define DMACMD_DACK_LEVEL       0x80    /* DACK sense active (0=actv. low) */
 157
 158 /*
 159  * Initialization value for DMA controller.
 160  */
 161 #define DMA_CTLR_INIT   ~(DMACMD_MEM_TO_MEM | DMACMD_CHAN_HOLD | \
 162                         DMACMD_CTLR_ENABLE | DMACMD_TIMING | \
 163                         DMACMD_FIX_PRIO | DMACMD_WRT_SELECT | \
 164                         DMACMD_DREQ_LEVEL | DMACMD_DACK_LEVEL)
 165
 166 /*
 167  * Write-only Mode register.  There is actually a 6-bit Mode register
 168  * associated with each channel.  These are written one at a time, with
 169  * the channel number indicated by the low-order 2 bits.
 170  */
 171
 172 #define DMAMODE_CHAN    0x03    /* Mask for the "channel select" bits. */
 173                                 /* These indicate channel 0-3 */
 174 #define DMAMODE_VERF    0x00    /* Verify Transfer */
 175 #define DMAMODE_READ    0x04    /* Read Transfer */
 176 #define DMAMODE_WRITE   0x08    /* Write Transfer */
 177                                 /* Note: Above settings for bits 2-3 are */
 178                                 /* "don't care" if bits 6-7 indicate */
 179                                 /* cascade mode */
 180 #define DMAMODE_AUTO    0x10    /* enable Autoinitialization on completion */
 181 #define DMAMODE_DECR    0x20    /* Address Decrement.  If 0, address incr */
 182 #define DMAMODE_DEMAND  0x00    /* Select Demand mode */
 183                                 /* Each DREQ causes transfers at full speed */
 184                                 /* until DREQ goes inactive (after which it */
 185                                 /* can be resumed) or either terminal-count */
 186                                 /* happens or EOP is asserted */
 187 #define DMAMODE_SINGLE  0x40    /* Select Single mode */
 188                                 /* Each DREQ causes a single byte/word xfer */
 189 #define DMAMODE_BLOCK   0x80    /* Select Block mode */
 190                                 /* Each DREQ causes transfers at full speed */
 191                                 /* until terminal count or EOP */
 192 #define DMAMODE_CASC    0xC0    /* Select Cascade mode.  On the PC-AT, this */
 193                                 /* should be set for DMA 2 channel 0 ONLY */
 194
 195
 196 #define EISA_DMAIS      0x40a   /* interrupt status register */
 197
 198 #define DMA_MSK         0x0A    /* Mask, enable disk, disable others */
 199 #define DMA_CLEAR       0x1A    /* Master clear */
 200 #define IOCR            0x56    /* IO controller */
 201
 202 /*
 203  * DMA Channels. d_chan field of dmareq.
 204  */
 205
 206 /* 8 bit channels */
 207 #define DMAE_CH0        0       /* Channel 0 */
 208 #define DMAE_CH1        1       /* Channel 1 */
 209 #define DMAE_CH2        2       /* Channel 2 */
 210 #define DMAE_CH3        3       /* Channel 3 */
 211 #define DMAE_CH4        4       /* Channel 4 */
 212 /* 16 bit channels */
 213 #define DMAE_CH5        5       /* Channel 5 */
 214 #define DMAE_CH6        6       /* Channel 6 */
 215 #define DMAE_CH7        7       /* Channel 7 */
 216
 217 /*
 218  * DMA Masks.
 219  */
 220 #define DMA_SETMSK      4       /* Set mask bit */
 221 #define DMA_CLRMSK      0       /* Clear mask bit */
 222
 223 /* dma_alloc modes */
 224 #define DMA_BLOCK       0       /* blocking task time allocation */
 225 #define DMA_NBLOCK      1       /* non-blocking task time allocation */
 226
 227 #define EISA_DMA_8      0       /* 8-bit data path */
 228 #define EISA_DMA_16     1<<2    /* 16-bit data path, word count */
 229 #define EISA_DMA_32     2<<2    /* 32-bit data path */
 230 #define EISA_DMA_16B    3<<2    /* 16-bit data path, byte count */
 231
 232 #define EISA_ENCM       4       /* enable chaining mode */
 233 #define EISA_CMOK       8       /* chaining mode completed (OK) */
 234
 235
 236 /*
 237  * Channel Address Array - makes life much easier
 238  */
 239 struct d37A_chan_reg_addr {
 240         uchar_t addr_reg;       /* address register */
 241         uchar_t cnt_reg;        /* count register */
 242         uchar_t page_reg;       /* page register */
 243         uchar_t ff_reg;         /* first-last flipflop */
 244         uchar_t cmd_reg;        /* command register */
 245         uchar_t mode_reg;       /* mode register */
 246         uchar_t mask_reg;       /* mask register */
 247         uchar_t stat_reg;       /* status register */
 248         uchar_t reqt_reg;       /* request register */
 249         ushort_t hpage_reg;     /* high page register */
 250         ushort_t hcnt_reg;      /* high count register */
 251         ushort_t emode_reg;     /* extended mode register */
 252         ushort_t scm_reg;       /* set chaining mode register */
 253 };
 254
 255 /*
 256  * macro to initialize array of d37A_chan_reg_addr structures
 257  */
 258 #define D37A_BASE_REGS_VALUES \
 259         {DMA_0ADR, DMA_0WCNT, DMA_0PAGE, DMAC1_CLFF, \
 260             DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
 261             DMA_0HPG, DMA_0XCNT, DMAC1_EWM, DMAC1_SCM}, \
 262         {DMA_1ADR, DMA_1WCNT, DMA_1PAGE, DMAC1_CLFF, \
 263             DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
 264             DMA_1HPG, DMA_1XCNT, DMAC1_EWM, DMAC1_SCM}, \
 265         {DMA_2ADR, DMA_2WCNT, DMA_2PAGE, DMAC1_CLFF, \
 266             DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
 267             DMA_2HPG, DMA_2XCNT, DMAC1_EWM, DMAC1_SCM}, \
 268         {DMA_3ADR, DMA_3WCNT, DMA_3PAGE, DMAC1_CLFF, \
 269             DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
 270             DMA_3HPG, DMA_3XCNT, DMAC1_EWM, DMAC1_SCM}, \
 271         {DMA_4ADR, DMA_4WCNT, DMA_4PAGE, DMAC2_CLFF, \
 272             DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
 273             DMA_4HPG, DMA_4XCNT, DMAC2_EWM, DMAC2_SCM}, \
 274         {DMA_5ADR, DMA_5WCNT, DMA_5PAGE, DMAC2_CLFF, \
 275             DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
 276             DMA_5HPG, DMA_5XCNT, DMAC2_EWM, DMAC2_SCM}, \
 277         {DMA_6ADR, DMA_6WCNT, DMA_6PAGE, DMAC2_CLFF, \
 278             DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
 279             DMA_6HPG, DMA_6XCNT, DMAC2_EWM, DMAC2_SCM}, \
 280         {DMA_7ADR, DMA_7WCNT, DMA_7PAGE, DMAC2_CLFF, \
 281             DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
 282             DMA_7HPG, DMA_7XCNT, DMAC2_EWM, DMAC2_SCM}
 283
 284 extern int d37A_init(dev_info_t *);
 285 extern void d37A_dma_disable(int);
 286 extern void d37A_dma_enable(int);
 287 extern void d37A_dma_swstart(int);
 288 extern void d37A_dma_stop(int);
 289 extern void d37A_get_chan_stat(int, ulong_t *, int *);
 290 extern int d37A_dma_valid(int);
 291 extern void d37A_dma_release(int);
 292
 293 /* The following 3 routines are intel specific : man page ddi_dmae_req(9S) */
 294 #if defined(__i386) || defined(__amd64)
 295 extern uchar_t d37A_get_best_mode(struct ddi_dmae_req *);
 296 extern int d37A_prog_chan(struct ddi_dmae_req *, ddi_dma_cookie_t *, int);
 297 extern int d37A_dma_swsetup(struct ddi_dmae_req *, ddi_dma_cookie_t *, int);
 298 #endif
 299
 300 #ifdef  __cplusplus
 301 }
 302 #endif
 303
 304 #endif /* _SYS_DMA_I8237A_H */