lib/libcrypto/armv4cpuid.S

   1 #include "arm_arch.h"
   2
   3 .text
   4 .code   32
   5
   6 .align  5
   7 #if __ARM_ARCH__>=7
   8 .global _armv7_neon_probe
   9 .type   _armv7_neon_probe,%function
  10 _armv7_neon_probe:
  11         .word   0xf26ee1fe      @ vorr  q15,q15,q15
  12         .word   0xe12fff1e      @ bx    lr
  13 .size   _armv7_neon_probe,.-_armv7_neon_probe
  14 #endif
  15
  16 .global OPENSSL_atomic_add
  17 .type   OPENSSL_atomic_add,%function
  18 OPENSSL_atomic_add:
  19 #if __ARM_ARCH__>=6
  20 .Ladd:  ldrex   r2,[r0]
  21         add     r3,r2,r1
  22         strex   r2,r3,[r0]
  23         cmp     r2,#0
  24         bne     .Ladd
  25         mov     r0,r3
  26         .word   0xe12fff1e      @ bx    lr
  27 #else
  28         stmdb   sp!,{r4-r6,lr}
  29         ldr     r2,.Lspinlock
  30         adr     r3,.Lspinlock
  31         mov     r4,r0
  32         mov     r5,r1
  33         add     r6,r3,r2        @ &spinlock
  34         b       .+8
  35 .Lspin: bl      sched_yield
  36         mov     r0,#-1
  37         swp     r0,r0,[r6]
  38         cmp     r0,#0
  39         bne     .Lspin
  40
  41         ldr     r2,[r4]
  42         add     r2,r2,r5
  43         str     r2,[r4]
  44         str     r0,[r6]         @ release spinlock
  45         ldmia   sp!,{r4-r6,lr}
  46         tst     lr,#1
  47         moveq   pc,lr
  48         .word   0xe12fff1e      @ bx    lr
  49 #endif
  50 .size   OPENSSL_atomic_add,.-OPENSSL_atomic_add
  51
  52 .global OPENSSL_wipe_cpu
  53 .type   OPENSSL_wipe_cpu,%function
  54 OPENSSL_wipe_cpu:
  55         ldr     r0,.LOPENSSL_armcap
  56         adr     r1,.LOPENSSL_armcap
  57         ldr     r0,[r1,r0]
  58         eor     r2,r2,r2
  59         eor     r3,r3,r3
  60         eor     ip,ip,ip
  61         tst     r0,#1
  62         beq     .Lwipe_done
  63         .word   0xf3000150      @ veor    q0, q0, q0
  64         .word   0xf3022152      @ veor    q1, q1, q1
  65         .word   0xf3044154      @ veor    q2, q2, q2
  66         .word   0xf3066156      @ veor    q3, q3, q3
  67         .word   0xf34001f0      @ veor    q8, q8, q8
  68         .word   0xf34221f2      @ veor    q9, q9, q9
  69         .word   0xf34441f4      @ veor    q10, q10, q10
  70         .word   0xf34661f6      @ veor    q11, q11, q11
  71         .word   0xf34881f8      @ veor    q12, q12, q12
  72         .word   0xf34aa1fa      @ veor    q13, q13, q13
  73         .word   0xf34cc1fc      @ veor    q14, q14, q14
  74         .word   0xf34ee1fe      @ veor    q15, q15, q15
  75 .Lwipe_done:
  76         mov     r0,sp
  77         tst     lr,#1
  78         moveq   pc,lr
  79         .word   0xe12fff1e      @ bx    lr
  80 .size   OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
  81
  82 .align  5
  83 .LOPENSSL_armcap:
  84 .word   OPENSSL_armcap_P-.LOPENSSL_armcap
  85 #if __ARM_ARCH__>=6
  86 .align  5
  87 #else
  88 .Lspinlock:
  89 .word   atomic_add_spinlock-.Lspinlock
  90 .align  5
  91
  92 .data
  93 .align  2
  94 atomic_add_spinlock:
  95 .word   0
  96 #endif
  97
  98 .comm   OPENSSL_armcap_P,4,4
  99 .hidden OPENSSL_armcap_P