usr/src/uts/common/io/ntxn/nx_hw_pci_regs.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2008 NetXen, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #ifndef _NX_HW_REGS_H_
  28 #define _NX_HW_REGS_H_
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /*
  35  *              PCI related defines.
  36  */
  37
  38 /*
  39  * Interrupt related defines.
  40  */
  41 #define PCIX_TARGET_STATUS      (0x10118)
  42 #define PCIX_TARGET_STATUS_F1   (0x10160)
  43 #define PCIX_TARGET_STATUS_F2   (0x10164)
  44 #define PCIX_TARGET_STATUS_F3   (0x10168)
  45 #define PCIX_TARGET_STATUS_F4   (0x10360)
  46 #define PCIX_TARGET_STATUS_F5   (0x10364)
  47 #define PCIX_TARGET_STATUS_F6   (0x10368)
  48 #define PCIX_TARGET_STATUS_F7   (0x1036c)
  49
  50 #define PCIX_TARGET_MASK        (0x10128)
  51 #define PCIX_TARGET_MASK_F1     (0x10170)
  52 #define PCIX_TARGET_MASK_F2     (0x10174)
  53 #define PCIX_TARGET_MASK_F3     (0x10178)
  54 #define PCIX_TARGET_MASK_F4     (0x10370)
  55 #define PCIX_TARGET_MASK_F5     (0x10374)
  56 #define PCIX_TARGET_MASK_F6     (0x10378)
  57 #define PCIX_TARGET_MASK_F7     (0x1037c)
  58
  59 /*
  60  * Message Signaled Interrupts
  61  */
  62 #define PCIX_MSI_F0             (0x13000)
  63 #define PCIX_MSI_F1             (0x13004)
  64 #define PCIX_MSI_F2             (0x13008)
  65 #define PCIX_MSI_F3             (0x1300c)
  66 #define PCIX_MSI_F4             (0x13010)
  67 #define PCIX_MSI_F5             (0x13014)
  68 #define PCIX_MSI_F6             (0x13018)
  69 #define PCIX_MSI_F7             (0x1301c)
  70 #define PCIX_MSI_F(FUNC)        (0x13000 +((FUNC) * 4))
  71
  72 /*
  73  *
  74  */
  75 #define PCIX_INT_VECTOR         (0x10100)
  76 #define PCIX_INT_MASK           (0x10104)
  77
  78 /*
  79  * Interrupt state machine and other bits.
  80  */
  81 #define PCIE_MISCCFG_RC         (0x1206c)
  82
  83
  84 #define ISR_INT_TARGET_STATUS     (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS))
  85 #define ISR_INT_TARGET_STATUS_F1  (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
  86 #define ISR_INT_TARGET_STATUS_F2  (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
  87 #define ISR_INT_TARGET_STATUS_F3  (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
  88 #define ISR_INT_TARGET_STATUS_F4  (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
  89 #define ISR_INT_TARGET_STATUS_F5  (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
  90 #define ISR_INT_TARGET_STATUS_F6  (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
  91 #define ISR_INT_TARGET_STATUS_F7  (UNM_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
  92
  93 #define ISR_INT_TARGET_MASK       (UNM_PCIX_PS_REG(PCIX_TARGET_MASK))
  94 #define ISR_INT_TARGET_MASK_F1    (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
  95 #define ISR_INT_TARGET_MASK_F2    (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
  96 #define ISR_INT_TARGET_MASK_F3    (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
  97 #define ISR_INT_TARGET_MASK_F4    (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
  98 #define ISR_INT_TARGET_MASK_F5    (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
  99 #define ISR_INT_TARGET_MASK_F6    (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
 100 #define ISR_INT_TARGET_MASK_F7    (UNM_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
 101
 102 #define ISR_INT_VECTOR            (UNM_PCIX_PS_REG(PCIX_INT_VECTOR))
 103 #define ISR_INT_MASK              (UNM_PCIX_PS_REG(PCIX_INT_MASK))
 104 #define ISR_INT_STATE_REG         (UNM_PCIX_PS_REG(PCIE_MISCCFG_RC))
 105
 106 #define ISR_MSI_INT_TRIGGER(FUNC) (UNM_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
 107
 108
 109 #define ISR_IS_LEGACY_INTR_IDLE(VAL)            (((VAL) & 0x300) == 0)
 110 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL)       (((VAL) & 0x300) == 0x200)
 111
 112 /*
 113  * PCI Interrupt Vector Values.
 114  */
 115 #define PCIX_INT_VECTOR_BIT_F0  0x0080
 116 #define PCIX_INT_VECTOR_BIT_F1  0x0100
 117 #define PCIX_INT_VECTOR_BIT_F2  0x0200
 118 #define PCIX_INT_VECTOR_BIT_F3  0x0400
 119 #define PCIX_INT_VECTOR_BIT_F4  0x0800
 120 #define PCIX_INT_VECTOR_BIT_F5  0x1000
 121 #define PCIX_INT_VECTOR_BIT_F6  0x2000
 122 #define PCIX_INT_VECTOR_BIT_F7  0x4000
 123
 124 struct nx_legacy_intr_set {
 125         __uint32_t      int_vec_bit;
 126         __uint32_t      tgt_status_reg;
 127         __uint32_t      tgt_mask_reg;
 128         __uint32_t      pci_int_reg;
 129 };
 130
 131 #define NX_LEGACY_INTR_CONFIG                   \
 132 {                                               \
 133         {       PCIX_INT_VECTOR_BIT_F0,         \
 134                 ISR_INT_TARGET_STATUS,          \
 135                 ISR_INT_TARGET_MASK,            \
 136                 ISR_MSI_INT_TRIGGER(0) },       \
 137                                                 \
 138         {       PCIX_INT_VECTOR_BIT_F1,         \
 139                 ISR_INT_TARGET_STATUS_F1,       \
 140                 ISR_INT_TARGET_MASK_F1,         \
 141                 ISR_MSI_INT_TRIGGER(1) },       \
 142                                                 \
 143         {       PCIX_INT_VECTOR_BIT_F2,         \
 144                 ISR_INT_TARGET_STATUS_F2,       \
 145                 ISR_INT_TARGET_MASK_F2,         \
 146                 ISR_MSI_INT_TRIGGER(2) },       \
 147                                                 \
 148         {       PCIX_INT_VECTOR_BIT_F3,         \
 149                 ISR_INT_TARGET_STATUS_F3,       \
 150                 ISR_INT_TARGET_MASK_F3,         \
 151                 ISR_MSI_INT_TRIGGER(3) },       \
 152                                                 \
 153         {       PCIX_INT_VECTOR_BIT_F4,         \
 154                 ISR_INT_TARGET_STATUS_F4,       \
 155                 ISR_INT_TARGET_MASK_F4,         \
 156                 ISR_MSI_INT_TRIGGER(4) },       \
 157                                                 \
 158         {       PCIX_INT_VECTOR_BIT_F5,         \
 159                 ISR_INT_TARGET_STATUS_F5,       \
 160                 ISR_INT_TARGET_MASK_F5,         \
 161                 ISR_MSI_INT_TRIGGER(5) },       \
 162                                                 \
 163         {       PCIX_INT_VECTOR_BIT_F6,         \
 164                 ISR_INT_TARGET_STATUS_F6,       \
 165                 ISR_INT_TARGET_MASK_F6,         \
 166                 ISR_MSI_INT_TRIGGER(6) },       \
 167                                                 \
 168         {       PCIX_INT_VECTOR_BIT_F7,         \
 169                 ISR_INT_TARGET_STATUS_F7,       \
 170                 ISR_INT_TARGET_MASK_F7,         \
 171                 ISR_MSI_INT_TRIGGER(7) },       \
 172 }
 173
 174 #ifdef __cplusplus
 175 }
 176 #endif
 177
 178 #endif /* !_NX_HW_REGS_H_ */