4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright (c) 2013 Saso Kiselkov. All rights reserved.
29 * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
30 * Copyright (c) 2017, Joyent, Inc.
40 #include <sys/types.h>
42 #include <sys/debug.h>
43 #include <sys/stropts.h>
44 #include <sys/stream.h>
45 #include <sys/strsun.h>
46 #include <sys/strlog.h>
49 #include <sys/kstat.h>
50 #include <sys/modctl.h>
51 #include <sys/errno.h>
53 #include <sys/mac_provider.h>
54 #include <sys/mac_ether.h>
57 #include <sys/sunddi.h>
61 #include <sys/ethernet.h>
62 #include <sys/pattr.h>
63 #include <sys/strsubr.h>
64 #include <sys/netlb.h>
65 #include <sys/random.h>
66 #include <inet/common.h>
71 #include <sys/bitmap.h>
72 #include <sys/ddifm.h>
73 #include <sys/fm/protocol.h>
74 #include <sys/fm/util.h>
76 #include <sys/fm/io/ddi.h>
77 #include "ixgbe_api.h"
79 #define MODULE_NAME "ixgbe" /* module name */
81 #define IXGBE_FAILURE DDI_FAILURE
83 #define IXGBE_UNKNOWN 0x00
84 #define IXGBE_INITIALIZED 0x01
85 #define IXGBE_STARTED 0x02
86 #define IXGBE_SUSPENDED 0x04
87 #define IXGBE_STALL 0x08
88 #define IXGBE_OVERTEMP 0x20
89 #define IXGBE_INTR_ADJUST 0x40
90 #define IXGBE_ERROR 0x80
92 #define MAX_NUM_UNICAST_ADDRESSES 0x80
93 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000
94 #define IXGBE_INTR_NONE 0
95 #define IXGBE_INTR_MSIX 1
96 #define IXGBE_INTR_MSI 2
97 #define IXGBE_INTR_LEGACY 3
99 #define IXGBE_POLL_NULL -1
101 #define MAX_COOKIE 18
102 #define MIN_NUM_TX_DESC 2
104 #define IXGBE_TX_DESC_LIMIT 32 /* tx desc limitation */
106 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */
108 #define IXGBE_RX_STOPPED 0x1
110 #define IXGBE_PKG_BUF_16k 16384
113 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
114 * supported silicon types.
116 #define MAX_TX_QUEUE_NUM 128
117 #define MAX_RX_QUEUE_NUM 128
118 #define MAX_INTR_VECTOR 64
121 * Maximum values for user configurable parameters
123 #define MAX_TX_RING_SIZE 4096
124 #define MAX_RX_RING_SIZE 4096
126 #define MAX_RX_LIMIT_PER_INTR 4096
128 #define MAX_RX_COPY_THRESHOLD 9216
129 #define MAX_TX_COPY_THRESHOLD 9216
130 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE
131 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE
132 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE
135 * Minimum values for user configurable parameters
137 #define MIN_TX_RING_SIZE 64
138 #define MIN_RX_RING_SIZE 64
140 #define MIN_MTU ETHERMIN
141 #define MIN_RX_LIMIT_PER_INTR 16
142 #define MIN_TX_COPY_THRESHOLD 0
143 #define MIN_RX_COPY_THRESHOLD 0
144 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC
145 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
146 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC
149 * Default values for user configurable parameters
151 #define DEFAULT_TX_RING_SIZE 1024
152 #define DEFAULT_RX_RING_SIZE 1024
154 #define DEFAULT_MTU ETHERMTU
155 #define DEFAULT_RX_LIMIT_PER_INTR 256
156 #define DEFAULT_RX_COPY_THRESHOLD 128
157 #define DEFAULT_TX_COPY_THRESHOLD 512
158 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1)
159 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC
160 #define DEFAULT_TX_RESCHED_THRESHOLD 128
161 #define DEFAULT_FCRTH 0x20000
162 #define DEFAULT_FCRTL 0x10000
163 #define DEFAULT_FCPAUSE 0xFFFF
165 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE
166 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE
167 #define DEFAULT_LSO_ENABLE B_TRUE
168 #define DEFAULT_LRO_ENABLE B_FALSE
169 #define DEFAULT_MR_ENABLE B_TRUE
170 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE
171 #define DEFAULT_RELAX_ORDER_ENABLE B_TRUE
172 #define DEFAULT_ALLOW_UNSUPPORTED_SFP B_FALSE
174 #define IXGBE_LSO_MAXLEN 65535
176 #define TX_DRAIN_TIME 200
177 #define RX_DRAIN_TIME 200
179 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */
180 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */
182 #define IXGBE_CYCLIC_PERIOD (1000000000) /* 1s */
185 * Extra register bit masks for 82598
187 #define IXGBE_PCS1GANA_FDC 0x20
188 #define IXGBE_PCS1GANLP_LPFD 0x20
189 #define IXGBE_PCS1GANLP_LPHD 0x40
192 * Defined for IP header alignment.
194 #define IPHDR_ALIGN_ROOM 2
197 * Bit flags for attach_progress
199 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
200 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
201 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
202 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
203 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
204 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
205 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
206 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
207 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */
208 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */
209 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
210 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
211 #define ATTACH_PROGRESS_SFP_TASKQ 0x4000 /* SFP taskq created */
212 #define ATTACH_PROGRESS_LINK_TIMER 0x8000 /* link check timer */
213 #define ATTACH_PROGRESS_OVERTEMP_TASKQ 0x10000 /* Over-temp taskq created */
214 #define ATTACH_PROGRESS_PHY_TASKQ 0x20000 /* Ext. PHY taskq created */
216 #define PROP_DEFAULT_MTU "default_mtu"
217 #define PROP_FLOW_CONTROL "flow_control"
218 #define PROP_TX_QUEUE_NUM "tx_queue_number"
219 #define PROP_TX_RING_SIZE "tx_ring_size"
220 #define PROP_RX_QUEUE_NUM "rx_queue_number"
221 #define PROP_RX_RING_SIZE "rx_ring_size"
222 #define PROP_RX_GROUP_NUM "rx_group_number"
224 #define PROP_INTR_FORCE "intr_force"
225 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable"
226 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable"
227 #define PROP_LSO_ENABLE "lso_enable"
228 #define PROP_LRO_ENABLE "lro_enable"
229 #define PROP_MR_ENABLE "mr_enable"
230 #define PROP_RELAX_ORDER_ENABLE "relax_order_enable"
231 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable"
232 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold"
233 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold"
234 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
235 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold"
236 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold"
237 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr"
238 #define PROP_INTR_THROTTLING "intr_throttling"
239 #define PROP_FM_CAPABLE "fm_capable"
240 #define PROP_ALLOW_UNSUPPORTED_SFP "allow_unsupported_sfp"
242 #define IXGBE_LB_NONE 0
243 #define IXGBE_LB_EXTERNAL 1
244 #define IXGBE_LB_INTERNAL_MAC 2
245 #define IXGBE_LB_INTERNAL_PHY 3
246 #define IXGBE_LB_INTERNAL_SERDES 4
249 * capability/feature flags
250 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
251 * Separately, the flag named _ENABLED is set when the feature is enabled.
253 #define IXGBE_FLAG_DCA_ENABLED (u32)(1)
254 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1)
255 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2)
256 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4)
257 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4)
258 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5)
259 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6)
260 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
261 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8)
262 #define IXGBE_FLAG_RSC_CAPABLE (u32)(1 << 9)
263 #define IXGBE_FLAG_SFP_PLUG_CAPABLE (u32)(1 << 10)
264 #define IXGBE_FLAG_TEMP_SENSOR_CAPABLE (u32)(1 << 11)
267 * Classification mode
269 #define IXGBE_CLASSIFY_NONE 0
270 #define IXGBE_CLASSIFY_RSS 1
271 #define IXGBE_CLASSIFY_VMDQ 2
272 #define IXGBE_CLASSIFY_VMDQ_RSS 3
274 /* adapter-specific info for each supported device type */
275 typedef struct adapter_info
{
276 uint32_t max_rx_que_num
; /* maximum number of rx queues */
277 uint32_t min_rx_que_num
; /* minimum number of rx queues */
278 uint32_t def_rx_que_num
; /* default number of rx queues */
279 uint32_t max_rx_grp_num
; /* maximum number of rx groups */
280 uint32_t min_rx_grp_num
; /* minimum number of rx groups */
281 uint32_t def_rx_grp_num
; /* default number of rx groups */
282 uint32_t max_tx_que_num
; /* maximum number of tx queues */
283 uint32_t min_tx_que_num
; /* minimum number of tx queues */
284 uint32_t def_tx_que_num
; /* default number of tx queues */
285 uint32_t max_mtu
; /* maximum MTU size */
287 * Interrupt throttling is in unit of 256 nsec
289 uint32_t max_intr_throttle
; /* maximum interrupt throttle */
290 uint32_t min_intr_throttle
; /* minimum interrupt throttle */
291 uint32_t def_intr_throttle
; /* default interrupt throttle */
293 uint32_t max_msix_vect
; /* maximum total msix vectors */
294 uint32_t max_ring_vect
; /* maximum number of ring vectors */
295 uint32_t max_other_vect
; /* maximum number of other vectors */
296 uint32_t other_intr
; /* "other" interrupt types handled */
297 uint32_t other_gpie
; /* "other" interrupt types enabling */
298 uint32_t flags
; /* capability flags */
301 /* bits representing all interrupt types other than tx & rx */
302 #define IXGBE_OTHER_INTR 0x3ff00000
303 #define IXGBE_82599_OTHER_INTR 0x86100000
306 IOC_INVAL
= -1, /* bad, NAK with EINVAL */
307 IOC_DONE
, /* OK, reply sent */
308 IOC_ACK
, /* OK, just send ACK */
309 IOC_REPLY
/* OK, just send reply */
312 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
316 * Defined for ring index operations
317 * ASSERT(index < limit)
318 * ASSERT(step < limit)
319 * ASSERT(index1 < limit)
320 * ASSERT(index2 < limit)
322 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
323 (index) + (step) : (index) + (step) - (limit))
324 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
325 (index) - (step) : (index) + (limit) - (step))
326 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
327 (index2) - (index1) : (index2) + (limit) - (index1))
329 #define LINK_LIST_INIT(_LH) \
330 (_LH)->head = (_LH)->tail = NULL
332 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
334 #define LIST_POP_HEAD(_LH) \
335 (single_link_t *)(_LH)->head; \
337 if ((_LH)->head != NULL) { \
338 (_LH)->head = (_LH)->head->link; \
339 if ((_LH)->head == NULL) \
340 (_LH)->tail = NULL; \
344 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
346 #define LIST_PUSH_TAIL(_LH, _E) \
347 if ((_LH)->tail != NULL) { \
348 (_LH)->tail->link = (single_link_t *)(_E); \
349 (_LH)->tail = (single_link_t *)(_E); \
351 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
355 #define LIST_GET_NEXT(_LH, _E) \
356 (((_LH)->tail == (single_link_t *)(_E)) ? \
357 NULL : ((single_link_t *)(_E))->link)
360 typedef struct single_link
{
361 struct single_link
*link
;
364 typedef struct link_list
{
372 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
373 DDI_PROP_DONTPASS, (n))
374 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
375 DDI_PROP_DONTPASS, (n), -1)
378 typedef union ixgbe_ether_addr
{
386 uint8_t addr
[ETHERADDRL
];
388 } ixgbe_ether_addr_t
;
396 typedef struct ixgbe_tx_context
{
397 uint32_t hcksum_flags
;
399 uint32_t mac_hdr_len
;
404 } ixgbe_tx_context_t
;
407 * Hold address/length of each DMA segment
409 typedef struct sw_desc
{
415 * Handles and addresses of DMA buffer
417 typedef struct dma_buffer
{
418 caddr_t address
; /* Virtual address */
419 uint64_t dma_address
; /* DMA (Hardware) address */
420 ddi_acc_handle_t acc_handle
; /* Data access handle */
421 ddi_dma_handle_t dma_handle
; /* DMA handle */
422 size_t size
; /* Buffer size */
423 size_t len
; /* Data length in the buffer */
429 typedef struct tx_control_block
{
431 uint32_t last_index
; /* last descriptor of the pkt */
436 ddi_dma_handle_t tx_dma_handle
;
438 sw_desc_t desc
[MAX_COOKIE
];
439 } tx_control_block_t
;
444 typedef struct rx_control_block
{
449 struct ixgbe_rx_data
*rx_data
;
450 int lro_next
; /* Index of next rcb */
451 int lro_prev
; /* Index of previous rcb */
452 bool lro_pkt
; /* Flag for LRO rcb */
453 } rx_control_block_t
;
456 * Software Data Structure for Tx Ring
458 typedef struct ixgbe_tx_ring
{
459 uint32_t index
; /* Ring index */
460 uint32_t intr_vector
; /* Interrupt vector index */
461 uint32_t vect_bit
; /* vector's bit in register */
467 kmutex_t recycle_lock
;
468 kmutex_t tcb_head_lock
;
469 kmutex_t tcb_tail_lock
;
472 * Tx descriptor ring definitions
474 dma_buffer_t tbd_area
;
475 union ixgbe_adv_tx_desc
*tbd_ring
;
476 uint32_t tbd_head
; /* Index of next tbd to recycle */
477 uint32_t tbd_tail
; /* Index of next tbd to transmit */
478 uint32_t tbd_free
; /* Number of free tbd */
481 * Tx control block list definitions
483 tx_control_block_t
*tcb_area
;
484 tx_control_block_t
**work_list
;
485 tx_control_block_t
**free_list
;
486 uint32_t tcb_head
; /* Head index of free list */
487 uint32_t tcb_tail
; /* Tail index of free list */
488 uint32_t tcb_free
; /* Number of free tcb in free list */
490 uint32_t *tbd_head_wb
; /* Head write-back */
491 uint32_t (*tx_recycle
)(struct ixgbe_tx_ring
*);
494 * s/w context structure for TCP/UDP checksum offload
497 ixgbe_tx_context_t tx_context
;
500 * Tx ring settings and status
502 uint32_t ring_size
; /* Tx descriptor ring size */
503 uint32_t free_list_size
; /* Tx free list size */
506 uint32_t recycle_fail
;
507 uint32_t stall_watchdog
;
509 uint32_t stat_overload
;
510 uint32_t stat_fail_no_tbd
;
511 uint32_t stat_fail_no_tcb
;
512 uint32_t stat_fail_dma_bind
;
513 uint32_t stat_reschedule
;
514 uint32_t stat_break_tbd_limit
;
515 uint32_t stat_lso_header_fail
;
517 uint64_t stat_obytes
;
518 uint64_t stat_opackets
;
520 mac_ring_handle_t ring_handle
;
523 * Pointer to the ixgbe struct
529 * Software Receive Ring
531 typedef struct ixgbe_rx_data
{
532 kmutex_t recycle_lock
; /* Recycle lock, for rcb_tail */
535 * Rx descriptor ring definitions
537 dma_buffer_t rbd_area
; /* DMA buffer of rx desc ring */
538 union ixgbe_adv_rx_desc
*rbd_ring
; /* Rx desc ring */
539 uint32_t rbd_next
; /* Index of next rx desc */
542 * Rx control block list definitions
544 rx_control_block_t
*rcb_area
;
545 rx_control_block_t
**work_list
; /* Work list of rcbs */
546 rx_control_block_t
**free_list
; /* Free list of rcbs */
547 uint32_t rcb_head
; /* Index of next free rcb */
548 uint32_t rcb_tail
; /* Index to put recycled rcb */
549 uint32_t rcb_free
; /* Number of free rcbs */
552 * Rx sw ring settings and status
554 uint32_t ring_size
; /* Rx descriptor ring size */
555 uint32_t free_list_size
; /* Rx free list size */
557 uint32_t rcb_pending
;
560 uint32_t lro_num
; /* Number of rcbs of one LRO */
561 uint32_t lro_first
; /* Index of first LRO rcb */
563 struct ixgbe_rx_ring
*rx_ring
; /* Pointer to rx ring */
567 * Software Data Structure for Rx Ring
569 typedef struct ixgbe_rx_ring
{
570 uint32_t index
; /* Ring index */
571 uint32_t group_index
; /* Group index */
572 uint32_t hw_index
; /* h/w ring index */
573 uint32_t intr_vector
; /* Interrupt vector index */
574 uint32_t vect_bit
; /* vector's bit in register */
576 ixgbe_rx_data_t
*rx_data
; /* Rx software ring */
578 kmutex_t rx_lock
; /* Rx access lock */
580 uint32_t stat_frame_error
;
581 uint32_t stat_cksum_error
;
582 uint32_t stat_exceed_pkt
;
584 uint64_t stat_rbytes
;
585 uint64_t stat_ipackets
;
587 mac_ring_handle_t ring_handle
;
588 uint64_t ring_gen_num
;
590 struct ixgbe
*ixgbe
; /* Pointer to ixgbe struct */
593 * Software Receive Ring Group
595 typedef struct ixgbe_rx_group
{
596 uint32_t index
; /* Group index */
597 mac_group_handle_t group_handle
; /* call back group handle */
598 struct ixgbe
*ixgbe
; /* Pointer to ixgbe struct */
602 * structure to map interrupt cleanup to msi-x vector
604 typedef struct ixgbe_intr_vector
{
605 struct ixgbe
*ixgbe
; /* point to my adapter */
606 ulong_t rx_map
[BT_BITOUL(MAX_RX_QUEUE_NUM
)]; /* bitmap of rx rings */
607 int rxr_cnt
; /* count rx rings */
608 ulong_t tx_map
[BT_BITOUL(MAX_TX_QUEUE_NUM
)]; /* bitmap of tx rings */
609 int txr_cnt
; /* count tx rings */
610 ulong_t other_map
[BT_BITOUL(2)]; /* bitmap of other */
611 int other_cnt
; /* count other interrupt */
612 } ixgbe_intr_vector_t
;
615 * Software adapter state
617 typedef struct ixgbe
{
619 mac_handle_t mac_hdl
;
622 struct ixgbe_osdep osdep
;
624 adapter_info_t
*capab
; /* adapter hardware capabilities */
625 ddi_taskq_t
*sfp_taskq
; /* sfp-change taskq */
626 ddi_taskq_t
*overtemp_taskq
; /* overtemp taskq */
627 ddi_taskq_t
*phy_taskq
; /* external PHY taskq */
628 uint32_t eims
; /* interrupt mask setting */
629 uint32_t eimc
; /* interrupt mask clear */
630 uint32_t eicr
; /* interrupt cause reg */
632 uint32_t ixgbe_state
;
633 link_state_t link_state
;
635 uint32_t link_duplex
;
637 uint32_t reset_count
;
638 uint32_t attach_progress
;
639 uint32_t loopback_mode
;
640 uint32_t default_mtu
;
641 uint32_t max_frame_size
;
642 ixgbe_link_speed speeds_supported
;
644 uint32_t rcb_pending
;
647 * Each msi-x vector: map vector to interrupt cleanup
649 ixgbe_intr_vector_t vect_map
[MAX_INTR_VECTOR
];
654 ixgbe_rx_ring_t
*rx_rings
; /* Array of rx rings */
655 uint32_t num_rx_rings
; /* Number of rx rings in use */
656 uint32_t rx_ring_size
; /* Rx descriptor ring size */
657 uint32_t rx_buf_size
; /* Rx buffer size */
658 bool lro_enable
; /* Large Receive Offload */
659 uint64_t lro_pkt_count
; /* LRO packet count */
663 ixgbe_rx_group_t
*rx_groups
; /* Array of rx groups */
664 uint32_t num_rx_groups
; /* Number of rx groups in use */
669 ixgbe_tx_ring_t
*tx_rings
; /* Array of tx rings */
670 uint32_t num_tx_rings
; /* Number of tx rings in use */
671 uint32_t tx_ring_size
; /* Tx descriptor ring size */
672 uint32_t tx_buf_size
; /* Tx buffer size */
675 bool tx_head_wb_enable
; /* Tx head wrtie-back */
676 bool tx_hcksum_enable
; /* Tx h/w cksum offload */
677 bool lso_enable
; /* Large Segment Offload */
678 bool mr_enable
; /* Multiple Tx and Rx Ring */
679 bool relax_order_enable
; /* Relax Order */
680 uint32_t classify_mode
; /* Classification mode */
681 uint32_t tx_copy_thresh
; /* Tx copy threshold */
682 uint32_t tx_recycle_thresh
; /* Tx recycle threshold */
683 uint32_t tx_overload_thresh
; /* Tx overload threshold */
684 uint32_t tx_resched_thresh
; /* Tx reschedule threshold */
685 bool rx_hcksum_enable
; /* Rx h/w cksum offload */
686 uint32_t rx_copy_thresh
; /* Rx copy threshold */
687 uint32_t rx_limit_per_intr
; /* Rx pkts per interrupt */
688 uint32_t intr_throttling
[MAX_INTR_VECTOR
];
690 int fm_capabilities
; /* FMA capabilities */
694 uint32_t intr_cnt_max
;
695 uint32_t intr_cnt_min
;
699 ddi_intr_handle_t
*htable
;
701 ddi_cb_handle_t cb_hdl
; /* Interrupt callback handle */
703 kmutex_t gen_lock
; /* General lock for device access */
704 kmutex_t watchdog_lock
;
705 kmutex_t rx_pending_lock
;
707 bool watchdog_enable
;
709 timeout_id_t watchdog_tid
;
712 uint32_t unicst_avail
;
713 uint32_t unicst_total
;
714 ixgbe_ether_addr_t unicst_addr
[MAX_NUM_UNICAST_ADDRESSES
];
715 uint32_t mcast_count
;
716 struct ether_addr mcast_table
[MAX_NUM_MULTICAST_ADDRESSES
];
718 ulong_t sys_page_size
;
720 bool link_check_complete
;
721 hrtime_t link_check_hrtime
;
722 ddi_periodic_t periodic_id
; /* for link check timer func */
729 uint32_t param_en_10000fdx_cap
:1,
730 param_en_5000fdx_cap
:1,
731 param_en_2500fdx_cap
:1,
732 param_en_1000fdx_cap
:1,
733 param_en_100fdx_cap
:1,
734 param_adv_10000fdx_cap
:1,
735 param_adv_5000fdx_cap
:1,
736 param_adv_2500fdx_cap
:1,
737 param_adv_1000fdx_cap
:1,
738 param_adv_100fdx_cap
:1,
740 param_asym_pause_cap
:1,
742 param_adv_autoneg_cap
:1,
743 param_adv_pause_cap
:1,
744 param_adv_asym_pause_cap
:1,
745 param_adv_rem_fault
:1,
746 param_lp_10000fdx_cap
:1,
747 param_lp_5000fdx_cap
:1,
748 param_lp_2500fdx_cap
:1,
749 param_lp_1000fdx_cap
:1,
750 param_lp_100fdx_cap
:1,
751 param_lp_autoneg_cap
:1,
752 param_lp_pause_cap
:1,
753 param_lp_asym_pause_cap
:1,
754 param_lp_rem_fault
:1,
758 typedef struct ixgbe_stat
{
759 kstat_named_t link_speed
; /* Link Speed */
761 kstat_named_t reset_count
; /* Reset Count */
763 kstat_named_t rx_frame_error
; /* Rx Error in Packet */
764 kstat_named_t rx_cksum_error
; /* Rx Checksum Error */
765 kstat_named_t rx_exceed_pkt
; /* Rx Exceed Max Pkt Count */
767 kstat_named_t tx_overload
; /* Tx Desc Ring Overload */
768 kstat_named_t tx_fail_no_tcb
; /* Tx Fail Freelist Empty */
769 kstat_named_t tx_fail_no_tbd
; /* Tx Fail Desc Ring Empty */
770 kstat_named_t tx_fail_dma_bind
; /* Tx Fail DMA bind */
771 kstat_named_t tx_reschedule
; /* Tx Reschedule */
772 kstat_named_t tx_break_tbd_limit
; /* Reached single xmit desc limit */
773 kstat_named_t tx_lso_header_fail
; /* New mblk for last LSO hdr frag */
775 kstat_named_t gprc
; /* Good Packets Received Count */
776 kstat_named_t gptc
; /* Good Packets Xmitted Count */
777 kstat_named_t gor
; /* Good Octets Received Count */
778 kstat_named_t got
; /* Good Octets Xmitd Count */
779 kstat_named_t prc64
; /* Packets Received - 64b */
780 kstat_named_t prc127
; /* Packets Received - 65-127b */
781 kstat_named_t prc255
; /* Packets Received - 127-255b */
782 kstat_named_t prc511
; /* Packets Received - 256-511b */
783 kstat_named_t prc1023
; /* Packets Received - 511-1023b */
784 kstat_named_t prc1522
; /* Packets Received - 1024-1522b */
785 kstat_named_t ptc64
; /* Packets Xmitted (64b) */
786 kstat_named_t ptc127
; /* Packets Xmitted (64-127b) */
787 kstat_named_t ptc255
; /* Packets Xmitted (128-255b) */
788 kstat_named_t ptc511
; /* Packets Xmitted (255-511b) */
789 kstat_named_t ptc1023
; /* Packets Xmitted (512-1023b) */
790 kstat_named_t ptc1522
; /* Packets Xmitted (1024-1522b */
791 kstat_named_t qprc
[16]; /* Queue Packets Received Count */
792 kstat_named_t qptc
[16]; /* Queue Packets Transmitted Count */
793 kstat_named_t qbrc
[16]; /* Queue Bytes Received Count */
794 kstat_named_t qbtc
[16]; /* Queue Bytes Transmitted Count */
796 kstat_named_t crcerrs
; /* CRC Error Count */
797 kstat_named_t illerrc
; /* Illegal Byte Error Count */
798 kstat_named_t errbc
; /* Error Byte Count */
799 kstat_named_t mspdc
; /* MAC Short Packet Discard Count */
800 kstat_named_t mpc
; /* Missed Packets Count */
801 kstat_named_t mlfc
; /* MAC Local Fault Count */
802 kstat_named_t mrfc
; /* MAC Remote Fault Count */
803 kstat_named_t rlec
; /* Receive Length Error Count */
804 kstat_named_t lxontxc
; /* Link XON Transmitted Count */
805 kstat_named_t lxonrxc
; /* Link XON Received Count */
806 kstat_named_t lxofftxc
; /* Link XOFF Transmitted Count */
807 kstat_named_t lxoffrxc
; /* Link XOFF Received Count */
808 kstat_named_t bprc
; /* Broadcasts Pkts Received Count */
809 kstat_named_t mprc
; /* Multicast Pkts Received Count */
810 kstat_named_t rnbc
; /* Receive No Buffers Count */
811 kstat_named_t ruc
; /* Receive Undersize Count */
812 kstat_named_t rfc
; /* Receive Frag Count */
813 kstat_named_t roc
; /* Receive Oversize Count */
814 kstat_named_t rjc
; /* Receive Jabber Count */
815 kstat_named_t tor
; /* Total Octets Recvd Count */
816 kstat_named_t tot
; /* Total Octets Xmitted Count */
817 kstat_named_t tpr
; /* Total Packets Received */
818 kstat_named_t tpt
; /* Total Packets Xmitted */
819 kstat_named_t mptc
; /* Multicast Packets Xmited Count */
820 kstat_named_t bptc
; /* Broadcast Packets Xmited Count */
821 kstat_named_t lroc
; /* LRO Packets Received Count */
822 kstat_named_t dev_gone
; /* Number of device gone events encountered */
826 * Function prototypes in ixgbe_buf.c
828 int ixgbe_alloc_dma(ixgbe_t
*);
829 void ixgbe_free_dma(ixgbe_t
*);
830 void ixgbe_set_fma_flags(int);
831 void ixgbe_free_dma_buffer(dma_buffer_t
*);
832 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t
*rx_ring
);
833 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t
*rx_data
);
836 * Function prototypes in ixgbe_main.c
838 int ixgbe_start(ixgbe_t
*, bool);
839 void ixgbe_stop(ixgbe_t
*, bool);
840 int ixgbe_driver_setup_link(ixgbe_t
*, bool);
841 int ixgbe_multicst_add(ixgbe_t
*, const uint8_t *);
842 int ixgbe_multicst_remove(ixgbe_t
*, const uint8_t *);
843 enum ioc_reply
ixgbe_loopback_ioctl(ixgbe_t
*, struct iocblk
*, mblk_t
*);
845 void ixgbe_enable_watchdog_timer(ixgbe_t
*);
846 void ixgbe_disable_watchdog_timer(ixgbe_t
*);
847 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
849 int ixgbe_check_acc_handle(ddi_acc_handle_t handle
);
850 int ixgbe_check_dma_handle(ddi_dma_handle_t handle
);
851 void ixgbe_fm_ereport(ixgbe_t
*, char *);
853 void ixgbe_fill_ring(void *, mac_ring_type_t
, const int, const int,
854 mac_ring_info_t
*, mac_ring_handle_t
);
855 void ixgbe_fill_group(void *arg
, mac_ring_type_t
, const int,
856 mac_group_info_t
*, mac_group_handle_t
);
857 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t
);
858 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t
);
861 * Function prototypes in ixgbe_gld.c
863 int ixgbe_m_start(void *);
864 void ixgbe_m_stop(void *);
865 int ixgbe_m_promisc(void *, boolean_t
);
866 int ixgbe_m_multicst(void *, boolean_t
, const uint8_t *);
867 void ixgbe_m_resources(void *);
868 void ixgbe_m_ioctl(void *, queue_t
*, mblk_t
*);
869 boolean_t
ixgbe_m_getcapab(void *, mac_capab_t
, void *);
870 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t
, uint_t
, const void *);
871 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t
, uint_t
, void *);
872 void ixgbe_m_propinfo(void *, const char *, mac_prop_id_t
,
873 mac_prop_info_handle_t
);
874 int ixgbe_set_priv_prop(ixgbe_t
*, const char *, uint_t
, const void *);
875 int ixgbe_get_priv_prop(ixgbe_t
*, const char *, uint_t
, void *);
876 bool ixgbe_param_locked(mac_prop_id_t
);
879 * Function prototypes in ixgbe_rx.c
881 mblk_t
*ixgbe_ring_rx(ixgbe_rx_ring_t
*, int);
882 void ixgbe_rx_recycle(caddr_t arg
);
883 mblk_t
*ixgbe_ring_rx_poll(void *, int);
886 * Function prototypes in ixgbe_tx.c
888 mblk_t
*ixgbe_ring_tx(void *, mblk_t
*);
889 void ixgbe_free_tcb(tx_control_block_t
*);
890 void ixgbe_put_free_list(ixgbe_tx_ring_t
*, link_list_t
*);
891 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t
*);
892 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t
*);
895 * Function prototypes in ixgbe_log.c
897 void ixgbe_notice(void *, const char *, ...);
898 void ixgbe_log(void *, const char *, ...);
899 void ixgbe_error(void *, const char *, ...);
902 * Function prototypes in ixgbe_stat.c
904 int ixgbe_init_stats(ixgbe_t
*);
905 int ixgbe_m_stat(void *, uint_t
, uint64_t *);
906 int ixgbe_rx_ring_stat(mac_ring_driver_t
, uint_t
, uint64_t *);
907 int ixgbe_tx_ring_stat(mac_ring_driver_t
, uint_t
, uint64_t *);
913 #endif /* _IXGBE_SW_H */