4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright 2014 QLogic Corporation
24 * The contents of this file are subject to the terms of the
25 * QLogic End User License (the "License").
26 * You may not use this file except in compliance with the License.
28 * You can obtain a copy of the License at
29 * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
30 * QLogic_End_User_Software_License.txt
31 * See the License for the specific language governing permissions
32 * and limitations under the License.
36 * Copyright (c) 2002, 2011, Oracle and/or its affiliates. All rights reserved.
42 #include <sys/types.h>
43 #include <sys/stream.h>
44 #include <sys/stropts.h>
45 #include <sys/errno.h>
48 #include <sys/modctl.h>
50 #include <sys/mac_provider.h>
53 #include <sys/sunddi.h>
54 #include <sys/sunndi.h>
55 #include <sys/ddifm.h>
56 #include <sys/fm/protocol.h>
57 #include <sys/fm/util.h>
58 #include <sys/fm/io/ddi.h>
59 #include <sys/pattr.h>
60 #include <sys/sysmacros.h>
61 #include <sys/ethernet.h>
62 //#include <sys/vlan.h>
63 #include <sys/strsun.h>
64 #include <sys/ksynch.h>
65 #include <sys/kstat.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #include <netinet/udp.h>
69 #include <netinet/tcp.h>
70 #include <inet/common.h>
72 #include <inet/ip_if.h>
73 #include <sys/strsubr.h>
78 * This really ticks me off! We use 'u' for naming unions
79 * within structures. Why is 'u' a reserved word!?!?!?
80 * http://bugs.opensolaris.org/view_bug.do?bug_id=4340073
81 * This undef has been moved to bnxe_debug.h.
93 #if !defined(__SunOS_MDB)
96 #include "bnxe_binding.h"
97 #if !defined(DBG) && !defined(__SunOS_MDB)
98 #include "bnxe_debug.h" /* wasn't included by debug.h */
106 #define RSS_ID_NONE -1
108 #define USER_OPTION_CKSUM_NONE 0x0
109 #define USER_OPTION_CKSUM_L3 0x1
110 #define USER_OPTION_CKSUM_L3_L4 0x2
111 #define USER_OPTION_CKSUM_DEFAULT USER_OPTION_CKSUM_L3_L4
113 #define USER_OPTION_MTU_MIN 60
114 #define USER_OPTION_MTU_MAX 9216
115 #define USER_OPTION_MTU_DEFAULT 1500
117 #define USER_OPTION_NUM_RINGS_MIN 0
118 #define USER_OPTION_NUM_RINGS_MAX MAX_RSS_CHAINS
119 #define USER_OPTION_NUM_RINGS_DEFAULT_MF 1
120 #define USER_OPTION_NUM_RINGS_DEFAULT_SF 4
121 #define USER_OPTION_NUM_RINGS_DEFAULT 0
123 #define USER_OPTION_RX_RING_GROUPS_MIN 1
124 #define USER_OPTION_RX_RING_GROUPS_MAX 1
125 #define USER_OPTION_RX_RING_GROUPS_DEFAULT 1
127 #define USER_OPTION_BDS_MIN 1
128 #define USER_OPTION_BDS_MAX 32767
129 #define USER_OPTION_RX_BDS_DEFAULT 1024
130 #define USER_OPTION_TX_BDS_DEFAULT 1024
131 #define USER_OPTION_MF_BDS_DIVISOR 4
133 #define USER_OPTION_INTR_COALESCE_MIN 10 /* usecs */
134 #define USER_OPTION_INTR_COALESCE_MAX 1000
135 #define USER_OPTION_INTR_COALESCE_RX_DEFAULT 20
136 #define USER_OPTION_INTR_COALESCE_TX_DEFAULT 40
138 #define USER_OPTION_TX_MAX_FREE_DEFAULT 32
139 #define USER_OPTION_RX_MAX_FREE_DEFAULT 32
141 //#define USER_OPTION_RX_DCOPY_THRESH_DEFAULT 0xffffffff
142 #define USER_OPTION_RX_DCOPY_THRESH_DEFAULT 128
144 //#define USER_OPTION_TX_DCOPY_THRESH_DEFAULT 0
145 #define USER_OPTION_TX_DCOPY_THRESH_DEFAULT 512
147 //#define BNXE_IP_MAXLEN 65535
148 #define BNXE_IP_MAXLEN 32768 /* 32768 = PAGESIZE * (BNXE_MAX_DMA_FRAGS_PER_PKT - 2 ) */
149 #define BNXE_OPTION_LEN 80 /* room for IP/TCP options (max 40 bytes each) */
150 #define BNXE_PKTHDR_LEN (sizeof(struct ether_vlan_header) + sizeof(struct ip) + sizeof(struct tcphdr) + BNXE_OPTION_LEN)
151 #define BNXE_LSO_MAXLEN (BNXE_IP_MAXLEN + sizeof(struct ether_vlan_header) - BNXE_PKTHDR_LEN) /* maximum payload */
153 #define BNXE_MAGIC 0x0feedead
154 #define BNXE_MEM_CHECK_LEN 16
155 #define BNXE_STR_SIZE 32
157 #define BNXEF_NAME "bnxef"
159 #define BNXE_FCOE(dev) ((um_device_t *)(dev))->do_fcoe
162 #define BNXE_DMA_ALIGNMENT 0x2000UL
164 #define BNXE_DMA_ALIGNMENT 0x1000UL
168 * Adding a two byte offset to the receive buffer aligns the IP header on a
169 * 16 byte boundary and it would put the TCP payload (assuming a 20 byte IP
170 * header and 20 byte TCP header) on an 8 byte boundary.
172 #define BNXE_DMA_RX_OFFSET 2
175 * The following two defines are used for defining limits on Tx packets.
176 * BNXE_MAX_DMA_HANDLES_PER_PKT is the maximum number of DMA handles that are
177 * pre-allocated for every Tx buffer descriptor. These DMA handles are used
178 * for mapping each mblk in the chain when not double copying the packet data
179 * into the copy buffer. BNXE_MAX_DMA_FRAGS_PER_PKT is based on the hardware
180 * and represents the maximum number of fragments an outgoing packet can have.
181 * Note that a single DMA handle can be comprised of multiple fragments which
182 * is very likely with LSO.
184 * As seen below BNXE_MAX_DMA_FRAGS_PER_PKT is set to 10. The actual firmware
185 * limit is 13 but 10 is chosen specifically for the case of LSO packets that
186 * are broken up across a long mblk chain. The firmware utilizes a sliding
187 * window on a packet's assigned buffer descriptors for LSO. The window is 10
188 * bds and each window (i.e. bds 1-10, 2-11, 3-12, etc), except the window
189 * containing the last bd, must contains at least MSS bytes. There are 'rare'
190 * cases where a packet sent down by the stack will not satisfy this window
191 * size requirement. Therefore, setting the frag limit to 10 results in any
192 * long chained packet (i.e. greater than 10 mblks), the trailing mblks will
193 * get double copied into a single copy buffer and will be pointed to by the
194 * last bd. This simple change will ensure the sliding window requirement is
195 * always satisfied. Note, LSO packets with long mblk chains are a rare
196 * occurance (nicdrv test01 can trigger it).
198 #define BNXE_MAX_DMA_HANDLES_PER_PKT 11 /* go easy on DMA resources */
199 #define BNXE_MAX_DMA_FRAGS_PER_PKT 10 /* set BNXE_IP_MAXLEN above accordingly */
200 #define BNXE_MAX_DMA_SGLLEN 20 /* for partial dma mapping */
202 #define BNXE_PDWM_THRESHOLD 8
204 #define BNXE_TX_RESOURCES_NO_CREDIT 0x01
205 #define BNXE_TX_RESOURCES_NO_DESC 0x02
206 #define BNXE_TX_RESOURCES_NO_DRV_DMA_RES 0x04 /* Out of Tx DMA handles */
207 #define BNXE_TX_RESOURCES_NO_OS_DMA_RES 0x08 /* Unable to allocate DMA resources. (e.g. bind error) */
208 #define BNXE_TX_RESOURCES_TOO_MANY_FRAGS 0x10
210 #define BNXE_TX_GOODXMIT 0
211 #define BNXE_TX_LINKDOWN 1
212 #define BNXE_TX_DEFERPKT 2
213 #define BNXE_TX_HDWRFULL 3
214 #define BNXE_TX_PKTERROR 4
216 #define BNXE_ROUTE_RING_NONE 0
217 #define BNXE_ROUTE_RING_TCPUDP 1
218 #define BNXE_ROUTE_RING_DEST_MAC 2
219 #define BNXE_ROUTE_RING_MSG_PRIO 3
221 #undef BNXE_DEBUG_DMA_LIST
223 extern ddi_device_acc_attr_t bnxeAccessAttribBAR
;
224 extern ddi_device_acc_attr_t bnxeAccessAttribBUF
;
226 typedef struct _BnxeDevParams
230 u32_t mtu
[LM_CLI_IDX_MAX
];
232 u32_t routeTxRingPolicy
;
233 u32_t numRings
; /* number of rings */
234 u32_t numRxDesc
[LM_CLI_IDX_MAX
]; /* number of RX descriptors */
235 u32_t numTxDesc
[LM_CLI_IDX_MAX
]; /* number of TX descriptors */
236 u32_t maxRxFree
; /* max free allowed before posting back */
237 u32_t maxTxFree
; /* max free allowed before posting back */
239 boolean_t intrCoalesce
;
242 boolean_t disableMsix
;
244 boolean_t l2_fw_flow_ctrl
;
245 boolean_t autogreeenEnable
;
247 u32_t rxCopyThreshold
;
248 u32_t txCopyThreshold
;
250 lm_rx_mask_t rx_filter_mask
[LM_CLI_IDX_MAX
];
253 lm_offload_t enabled_oflds
;
259 boolean_t fcoeEnable
;
261 boolean_t linkRemoteFaultDetect
;
263 lm_status_t lastIndLink
;
264 lm_medium_t lastIndMedium
;
266 uint32_t debug_level
;
270 typedef struct _BnxeLinkCfg
272 boolean_t link_autoneg
;
273 boolean_t param_20000fdx
;
274 boolean_t param_10000fdx
;
275 boolean_t param_2500fdx
;
276 boolean_t param_1000fdx
;
277 boolean_t param_100fdx
;
278 boolean_t param_100hdx
;
279 boolean_t param_10fdx
;
280 boolean_t param_10hdx
;
281 boolean_t param_txpause
;
282 boolean_t param_rxpause
;
286 typedef struct _BnxePhyCfg
289 boolean_t flow_autoneg
;
290 u32_t supported
[ELINK_LINK_CONFIG_SIZE
];
295 typedef struct _BnxeProps
298 boolean_t link_duplex
;
299 boolean_t link_txpause
;
300 boolean_t link_rxpause
;
305 typedef struct _BnxeMemBlock
315 typedef struct _BnxeMemDma
320 ddi_dma_handle_t dmaHandle
;
321 ddi_acc_handle_t dmaAccHandle
;
322 lm_address_t physAddr
;
328 typedef struct _BnxeMemRegion
331 lm_address_t baseAddr
;
335 ddi_acc_handle_t regAccess
;
340 typedef struct _um_txpacket_t
342 lm_packet_t lm_pkt
; /* must be the first entry */
343 lm_pkt_tx_info_t tx_info
;
347 ddi_dma_handle_t cbDmaHandle
; /* cb = copy buffer */
348 ddi_acc_handle_t cbDmaAccHandle
;
350 lm_address_t cbPhysAddr
;
353 u32_t num_handles
; /* number of handles used for pkt */
354 ddi_dma_handle_t dmaHandles
[BNXE_MAX_DMA_HANDLES_PER_PKT
];
356 lm_frag_list_t frag_list
;
357 lm_frag_t frag_list_buffer
[BNXE_MAX_DMA_FRAGS_PER_PKT
];
361 typedef struct _TxQueue
363 void * pUM
; /* backpointer to um_device_t */
364 u32_t idx
; /* this ring's index */
366 mac_ring_handle_t ringHandle
;
368 u32_t desc_cnt
; /* number of Tx descriptors */
378 u32_t thresh_pdwm
; /* low resource water marks */
382 s_list_t sentTxQ
; /* bds that have been sent and are ready to be freed */
384 kmutex_t freeTxDescMutex
;
385 s_list_t freeTxDescQ
; /* bds that are free for use */
387 s_list_t waitTxDescQ
; /* bds that are setup and waiting for tx (lock w/ tx mutex) */
393 typedef struct _um_rxpacket_t
395 lm_packet_t lm_pkt
; /* must be first entry */
396 lm_pkt_rx_info_t rx_info
;
400 void * pUM
; /* backpointer to um_device_t for free routine */
401 int idx
; /* chain index used by the free routine */
405 ddi_dma_handle_t dmaHandle
;
406 ddi_acc_handle_t dmaAccHandle
;
410 typedef struct _RxQueue
412 void * pUM
; /* backpointer to um_device_t */
413 u32_t idx
; /* this ring's index */
415 mac_ring_handle_t ringHandle
;
416 uint64_t genNumber
; /* set by mac and passed up in mac_ring_rx */
418 volatile u32_t inPollMode
;
426 u32_t rxBufUpInStack
;
430 kmutex_t doneRxMutex
;
431 s_list_t doneRxQ
; /* free bds that are ready to be posted */
433 s_list_t waitRxQ
; /* packet waiting to be sent up */
437 typedef struct _RxQueueGroup
439 void * pUM
; /* backpointer to um_device_t */
440 u32_t idx
; /* this group's index */
441 mac_group_handle_t groupHandle
;
445 typedef struct _KstatRingMap
447 u32_t idx
; /* ring index */
448 void * pUM
; /* reference back to um_device_t */
452 typedef struct _BnxeFcoeState
454 lm_fcoe_state_t lm_fcoe
;
458 typedef struct _BnxeClientStats
464 u32_t offloadConnWqeTx
;
465 u32_t offloadConnWqeTxErr
;
466 u32_t offloadConnCqeRx
;
467 u32_t offloadConnCqeRxErr
;
468 u32_t enableConnWqeTx
;
469 u32_t enableConnWqeTxErr
;
470 u32_t enableConnCqeRx
;
471 u32_t enableConnCqeRxErr
;
472 u32_t disableConnWqeTx
;
473 u32_t disableConnWqeTxErr
;
474 u32_t disableConnCqeRx
;
475 u32_t disableConnCqeRxErr
;
476 u32_t destroyConnWqeTx
;
477 u32_t destroyConnWqeTxErr
;
478 u32_t destroyConnCqeRx
;
479 u32_t destroyConnCqeRxErr
;
481 u32_t destroyWqeTxErr
;
483 u32_t destroyCqeRxErr
;
484 u32_t compRequestCqeRx
;
485 u32_t compRequestCqeRxErr
;
493 typedef struct _BnxeFcoeData
497 BnxeClientStats stats
;
502 typedef struct _BnxeIntrBlock
507 u32_t intrHandleBlockSize
;
508 ddi_intr_handle_t
* pIntrHandleBlockAlloc
;
509 ddi_intr_handle_t
* pIntrHandleBlock
;
513 typedef struct _BnxeWorkQueueInstance
517 char taskqName
[BNXE_STR_SIZE
];
518 ddi_taskq_t
* pTaskq
;
519 kmutex_t workQueueMutex
;
522 u32_t workItemQueued
;
524 u32_t workItemComplete
;
526 } BnxeWorkQueueInstance
;
529 typedef struct _BnxeWorkQueues
531 BnxeWorkQueueInstance instq
; /* instant, single thread serialized */
532 BnxeWorkQueueInstance delayq
; /* delayed, multi thread not serialized */
536 /* the following are used against the clientState variable in um_device_t */
538 #define CLIENT_FLG_DEVI 0x001
539 #define CLIENT_FLG_BIND 0x002
540 #define CLIENT_FLG_HW 0x004
542 #define CLIENT_DEVI(pUM, client) \
543 ((pUM)->clientState[(client)] & CLIENT_FLG_DEVI)
545 #define CLIENT_HW(pUM, client) \
546 ((pUM)->clientState[(client)] & CLIENT_FLG_HW)
548 #define CLIENT_BOUND(pUM, client) \
549 (((client) == LM_CLI_IDX_NDIS) ? \
550 ((pUM)->clientState[(client)] & CLIENT_FLG_HW) : \
551 ((pUM)->clientState[(client)] & CLIENT_FLG_BIND))
553 #define CLIENT_DEVI_SET(pUM, client) \
554 ((pUM)->clientState[(client)] |= CLIENT_FLG_DEVI)
556 #define CLIENT_DEVI_RESET(pUM, client) \
557 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_DEVI)
559 #define CLIENT_BIND_SET(pUM, client) \
560 ((pUM)->clientState[(client)] |= CLIENT_FLG_BIND)
562 #define CLIENT_BIND_RESET(pUM, client) \
563 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_BIND)
565 #define CLIENT_HW_SET(pUM, client) \
566 ((pUM)->clientState[(client)] |= CLIENT_FLG_HW)
568 #define CLIENT_HW_RESET(pUM, client) \
569 ((pUM)->clientState[(client)] &= ~CLIENT_FLG_HW)
572 typedef struct _um_device
574 lm_device_t lm_dev
; /* must be the first element */
581 u32_t clientState
[LM_CLI_IDX_MAX
];
583 d_list_t memBlockList
;
585 d_list_t memRegionList
;
586 #ifdef BNXE_DEBUG_DMA_LIST
587 d_list_t memDmaListSaved
;
591 char devName
[BNXE_STR_SIZE
];
592 char version
[BNXE_STR_SIZE
];
593 char versionLM
[BNXE_STR_SIZE
];
594 char versionFW
[BNXE_STR_SIZE
];
595 char versionBC
[BNXE_STR_SIZE
];
596 char chipName
[BNXE_STR_SIZE
];
597 char chipID
[BNXE_STR_SIZE
];
598 char intrAlloc
[BNXE_STR_SIZE
];
599 char bus_dev_func
[BNXE_STR_SIZE
];
600 char vendor_device
[BNXE_STR_SIZE
];
602 volatile u32_t plumbed
;
604 ddi_acc_handle_t pPciCfg
;
606 kmutex_t intrMutex
[MAX_RSS_CHAINS
+ 1];
607 kmutex_t intrFlipMutex
[MAX_RSS_CHAINS
+ 1];
608 kmutex_t sbMutex
[MAX_RSS_CHAINS
+ 1];
609 kmutex_t ethConMutex
;
614 kmutex_t spqMutex
; /* slow path queue lock */
615 kmutex_t spReqMutex
; /* slow path request manager lock */
616 kmutex_t rrReqMutex
; /* ramrod request */
617 kmutex_t islesCtrlMutex
;
620 kmutex_t offloadMutex
;
621 kmutex_t hwInitMutex
;
623 krwlock_t gldTxMutex
;
626 volatile u32_t timerEnabled
;
627 timeout_id_t timerID
;
629 BnxeWorkQueues workqs
;
631 BnxeMemDma
* statusBlocks
[MAX_RSS_CHAINS
+ 1];
632 volatile u32_t intrEnabled
;
634 /* the arrays below = LM_SB_CNT() + 1 = 17 */
635 u64_t intrSbCnt
[MAX_RSS_CHAINS
+ 1];
636 u64_t intrSbNoChangeCnt
[MAX_RSS_CHAINS
+ 1];
637 u64_t intrSbPollCnt
[MAX_RSS_CHAINS
+ 1];
638 u64_t intrSbPollNoChangeCnt
[MAX_RSS_CHAINS
+ 1];
642 BnxeIntrBlock defIntr
;
643 BnxeIntrBlock rssIntr
;
644 BnxeIntrBlock fcoeIntr
;
646 BnxeDevParams devParams
;
648 mac_resource_handle_t macRxResourceHandles
[MAX_ETH_REG_CONS
];
649 u8_t gldMac
[ETHERNET_ADDRESS_SIZE
];
654 u32_t ucastTableLen
; /* number of ucast addrs in the table */
655 #ifndef LM_MAX_UC_TABLE_SIZE
656 #define LM_MAX_UC_TABLE_SIZE 1 /* for now, fix needed to support multiple ucast addr */
659 TxQueue txq
[MAX_ETH_CONS
];
660 RxQueue rxq
[MAX_ETH_CONS
];
661 RxQueueGroup rxqGroup
[USER_OPTION_RX_RING_GROUPS_MAX
];
662 u32_t rxBufSignature
[LM_CLI_IDX_MAX
];
666 BnxePhyCfg hwinit
; /* gathered by BnxeCfgInit */
667 BnxePhyCfg curcfg
; /* initialized from hwinit by BnxeCfgReset */
669 u32_t phyInitialized
;
672 kstat_t
* kstatsLink
;
673 kstat_t
* kstatsIntr
;
674 kstat_t
* kstatsL2Chip
;
675 kstat_t
* kstatsL2Driver
;
676 kstat_t
* kstatsL2Stats
;
677 kstat_t
* kstatsFcoe
;
678 kstat_t
* kstatsDcbx
;
679 kstat_t
* kstats_rxq
[MAX_ETH_CONS
];
680 KstatRingMap kstats_rxq_map
[MAX_ETH_CONS
];
681 kstat_t
* kstats_txq
[MAX_ETH_CONS
];
682 KstatRingMap kstats_txq_map
[MAX_ETH_CONS
];
685 int fmCapabilities
; /* FMA capabilities */
689 iscsi_info_block_hdr_t iscsiInfo
;
694 /* mioc[ack|nak] return values from ioctl subroutines */
697 IOC_INVAL
= -1, /* bad, NAK with EINVAL */
698 IOC_DONE
, /* OK, reply sent */
699 IOC_ACK
, /* OK, just send ACK */
700 IOC_REPLY
, /* OK, just send reply */
701 IOC_RESTART_ACK
, /* OK, restart & ACK */
702 IOC_RESTART_REPLY
/* OK, restart & reply */
706 #define BNXE_IOC_BASE ('X' << 8)
707 /* IOCTLs for get/set lldp and dcbx params */
708 #define GIOCBNXELLDP (BNXE_IOC_BASE + 0)
709 #define GIOCBNXEDCBX (BNXE_IOC_BASE + 1)
710 #define SIOCBNXEDCBX (BNXE_IOC_BASE + 2)
711 /* IOCTLs for edebug and firmware upgrade */
712 #define GIOCBNXEREG (BNXE_IOC_BASE + 3)
713 #define SIOCBNXEREG (BNXE_IOC_BASE + 4)
714 #define GIOCBNXENVRM (BNXE_IOC_BASE + 5)
715 #define SIOCBNXENVRM (BNXE_IOC_BASE + 6)
716 #define GIOCBNXEPCI (BNXE_IOC_BASE + 7)
717 #define GIOCBNXESTATS (BNXE_IOC_BASE + 8)
725 struct bnxe_nvram_data
729 u32_t value
[1]; /* variable */
734 void BnxeCfgInit(um_device_t
* pUM
);
735 void BnxeCfgReset(um_device_t
* pUM
);
738 void BnxeInitBdCnts(um_device_t
* pUM
,
742 boolean_t
BnxeGldInit(um_device_t
* pUM
);
743 boolean_t
BnxeGldFini(um_device_t
* pUM
);
744 void BnxeGldLink(um_device_t
* pUM
,
748 boolean_t
BnxeEstablishHwConn(um_device_t
* pUM
,
750 int BnxeHwStartFCOE(um_device_t
* pUM
);
751 int BnxeHwStartL2(um_device_t
* pUM
);
752 int BnxeHwStartCore(um_device_t
* pUM
);
753 void BnxeHwStopFCOE(um_device_t
* pUM
);
754 void BnxeHwStopL2(um_device_t
* pUM
);
755 void BnxeHwStopCore(um_device_t
* pUM
);
756 void BnxeUpdatePhy(um_device_t
* pUM
);
757 int BnxeMacAddress(um_device_t
* pUM
,
760 const uint8_t * pMacAddr
);
761 int BnxeMulticast(um_device_t
* pUM
,
764 const uint8_t * pMcastAddr
,
766 int BnxeRxMask(um_device_t
* pUM
,
769 int BnxeHwResume(um_device_t
* pUM
);
770 int BnxeHwSuspend(um_device_t
* pUM
);
772 int BnxeHwQuiesce(um_device_t
* pUM
);
776 void BnxeIntrIguSbEnable(um_device_t
* pUM
,
779 void BnxeIntrIguSbDisable(um_device_t
* pUM
,
782 void BnxePollRxRing(um_device_t
* pUM
,
784 boolean_t
* pPktsRxed
,
785 boolean_t
* pPktsTxed
);
786 void BnxePollRxRingFCOE(um_device_t
* pUM
);
787 int BnxeIntrEnable(um_device_t
* pUM
);
788 void BnxeIntrDisable(um_device_t
* pUM
);
789 boolean_t
BnxeIntrInit(um_device_t
* pUM
);
790 void BnxeIntrFini(um_device_t
* pUM
);
793 boolean_t
BnxeKstatInit(um_device_t
* pUM
);
794 void BnxeKstatFini(um_device_t
* pUM
);
797 int BnxeRouteTxRing(um_device_t
* pUM
,
801 boolean_t
BnxeWaitForPacketsFromClient(um_device_t
* pUM
,
803 mblk_t
* BnxeRxRingProcess(um_device_t
* pUM
,
807 void BnxeRxPktsAbort(um_device_t
* pUM
,
809 int BnxeRxPktsInitPostBuffers(um_device_t
* pUM
,
811 int BnxeRxPktsInit(um_device_t
* pUM
,
813 void BnxeRxPktsFini(um_device_t
* pUM
,
817 void BnxeTxPktsReclaim(um_device_t
* pUM
,
819 s_list_t
* pPktList
);
820 void BnxeTxRingProcess(um_device_t
* pUM
,
822 int BnxeTxSendMblk(um_device_t
* pUM
,
827 void BnxeTxPktsAbort(um_device_t
* pUM
,
829 int BnxeTxPktsInit(um_device_t
* pUM
,
831 void BnxeTxPktsFini(um_device_t
* pUM
,
835 void BnxeTimerStart(um_device_t
* pUM
);
836 void BnxeTimerStop(um_device_t
* pUM
);
839 boolean_t
BnxeWorkQueueInit(um_device_t
* pUM
);
840 void BnxeWorkQueueWaitAndDestroy(um_device_t
* pUM
);
841 void BnxeWorkQueueStartPending(um_device_t
* pUM
);
842 boolean_t
BnxeWorkQueueAdd(um_device_t
* pUM
,
843 void (*pWorkCbk
)(um_device_t
*, void *, u32_t
),
846 boolean_t
BnxeWorkQueueAddNoCopy(um_device_t
* pUM
,
847 void (*pWorkCbk
)(um_device_t
*, void *),
849 boolean_t
BnxeWorkQueueAddGeneric(um_device_t
* pUM
,
850 void (*pWorkCbkGeneric
)(um_device_t
*));
851 boolean_t
BnxeWorkQueueAddDelay(um_device_t
* pUM
,
852 void (*pWorkCbk
)(um_device_t
*, void *, u32_t
),
856 boolean_t
BnxeWorkQueueAddDelayNoCopy(um_device_t
* pUM
,
857 void (*pWorkCbk
)(um_device_t
*, void *),
860 boolean_t
BnxeWorkQueueAddDelayGeneric(um_device_t
* pUM
,
861 void (*pWorkCbkGeneric
)(um_device_t
*),
865 boolean_t
BnxeFcoeInitCqe(um_device_t
* pUM
,
866 struct fcoe_kcqe
* kcqe
);
867 boolean_t
BnxeFcoeOffloadConnCqe(um_device_t
* pUM
,
868 BnxeFcoeState
* pFcoeState
,
869 struct fcoe_kcqe
* kcqe
);
870 boolean_t
BnxeFcoeEnableConnCqe(um_device_t
* pUM
,
871 BnxeFcoeState
* pFcoeState
,
872 struct fcoe_kcqe
* kcqe
);
873 boolean_t
BnxeFcoeDisableConnCqe(um_device_t
* pUM
,
874 BnxeFcoeState
* pFcoeState
,
875 struct fcoe_kcqe
* kcqe
);
876 boolean_t
BnxeFcoeDestroyConnCqe(um_device_t
* pUM
,
877 BnxeFcoeState
* pFcoeState
,
878 struct fcoe_kcqe
* kcqe
);
879 boolean_t
BnxeFcoeDestroyCqe(um_device_t
* pUM
,
880 struct fcoe_kcqe
* kcqe
);
881 boolean_t
BnxeFcoeStatCqe(um_device_t
* pUM
,
882 struct fcoe_kcqe
* kcqe
);
883 boolean_t
BnxeFcoeCompRequestCqe(um_device_t
* pUM
,
884 struct fcoe_kcqe
* kcqes
,
886 boolean_t
BnxeFcoePrvCtl(dev_info_t
* pDev
,
890 mblk_t
* BnxeFcoePrvTx(dev_info_t
* pDev
,
894 boolean_t
BnxeFcoePrvPoll(dev_info_t
* pDev
);
895 boolean_t
BnxeFcoePrvSendWqes(dev_info_t
* pDev
,
898 boolean_t
BnxeFcoePrvMapMailboxq(dev_info_t
* pDev
,
901 ddi_acc_handle_t
* pAccHandle
);
902 boolean_t
BnxeFcoePrvUnmapMailboxq(dev_info_t
* pDev
,
905 ddi_acc_handle_t accHandle
);
906 int BnxeFcoeInit(um_device_t
* pUM
);
907 int BnxeFcoeFini(um_device_t
* pUM
);
908 void BnxeFcoeStartStop(um_device_t
* pUM
);
911 u8_t
BnxeInstance(void * pDev
);
912 char * BnxeDevName(void * pDev
);
913 boolean_t
BnxeProtoSupport(um_device_t
* pUM
, int proto
);
914 boolean_t
BnxeProtoFcoeAfex(um_device_t
* pUM
);
915 int BnxeCheckAccHandle(ddi_acc_handle_t handle
);
916 int BnxeCheckDmaHandle(ddi_dma_handle_t handle
);
917 void BnxeFmErrorReport(um_device_t
* pUM
, char * detail
);
920 extern boolean_t
bnxe_fill_transceiver(um_device_t
*, void *);
922 extern kmutex_t bnxeLoaderMutex
;
923 extern u32_t bnxeNumPlumbed
;
925 extern BnxeLinkCfg bnxeLinkCfg
;
927 /* undefine this to help with dtrace analysis */
928 #define BNXE_LOCKS_INLINE
930 #ifdef BNXE_LOCKS_INLINE
932 #define BNXE_LOCK_ENTER_INTR(pUM, idx) mutex_enter(&(pUM)->intrMutex[(idx)])
933 #define BNXE_LOCK_EXIT_INTR(pUM, idx) mutex_exit(&(pUM)->intrMutex[(idx)])
934 #define BNXE_LOCK_ENTER_INTR_FLIP(pUM, idx) mutex_enter(&(pUM)->intrFlipMutex[(idx)])
935 #define BNXE_LOCK_EXIT_INTR_FLIP(pUM, idx) mutex_exit(&(pUM)->intrFlipMutex[(idx)])
936 #define BNXE_LOCK_ENTER_TX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].txMutex)
937 #define BNXE_LOCK_EXIT_TX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].txMutex)
938 #define BNXE_LOCK_ENTER_FREETX(pUM, idx) mutex_enter(&(pUM)->txq[(idx)].freeTxDescMutex)
939 #define BNXE_LOCK_EXIT_FREETX(pUM, idx) mutex_exit(&(pUM)->txq[(idx)].freeTxDescMutex)
940 #define BNXE_LOCK_ENTER_RX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].rxMutex)
941 #define BNXE_LOCK_EXIT_RX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].rxMutex)
942 #define BNXE_LOCK_ENTER_DONERX(pUM, idx) mutex_enter(&(pUM)->rxq[(idx)].doneRxMutex)
943 #define BNXE_LOCK_EXIT_DONERX(pUM, idx) mutex_exit(&(pUM)->rxq[(idx)].doneRxMutex)
944 #define BNXE_LOCK_ENTER_SB(pUM, idx) mutex_enter(&(pUM)->sbMutex[(idx)])
945 #define BNXE_LOCK_EXIT_SB(pUM, idx) mutex_exit(&(pUM)->sbMutex[(idx)])
946 #define BNXE_LOCK_ENTER_ETH_CON(pUM) mutex_enter(&(pUM)->ethConMutex)
947 #define BNXE_LOCK_EXIT_ETH_CON(pUM) mutex_exit(&(pUM)->ethConMutex)
948 #define BNXE_LOCK_ENTER_MCP(pUM) mutex_enter(&(pUM)->mcpMutex)
949 #define BNXE_LOCK_EXIT_MCP(pUM) mutex_exit(&(pUM)->mcpMutex)
950 #define BNXE_LOCK_ENTER_PHY(pUM) mutex_enter(&(pUM)->phyMutex)
951 #define BNXE_LOCK_EXIT_PHY(pUM) mutex_exit(&(pUM)->phyMutex)
952 #define BNXE_LOCK_ENTER_IND(pUM) mutex_enter(&(pUM)->indMutex)
953 #define BNXE_LOCK_EXIT_IND(pUM) mutex_exit(&(pUM)->indMutex)
954 #define BNXE_LOCK_ENTER_CID(pUM) mutex_enter(&(pUM)->cidMutex)
955 #define BNXE_LOCK_EXIT_CID(pUM) mutex_exit(&(pUM)->cidMutex)
956 #define BNXE_LOCK_ENTER_SPQ(pUM) mutex_enter(&(pUM)->spqMutex)
957 #define BNXE_LOCK_EXIT_SPQ(pUM) mutex_exit(&(pUM)->spqMutex)
958 #define BNXE_LOCK_ENTER_SPREQ(pUM) mutex_enter(&(pUM)->spReqMutex)
959 #define BNXE_LOCK_EXIT_SPREQ(pUM) mutex_exit(&(pUM)->spReqMutex)
960 #define BNXE_LOCK_ENTER_RRREQ(pUM) mutex_enter(&(pUM)->rrReqMutex)
961 #define BNXE_LOCK_EXIT_RRREQ(pUM) mutex_exit(&(pUM)->rrReqMutex)
962 #define BNXE_LOCK_ENTER_ISLES_CONTROL(pUM) mutex_enter(&(pUM)->islesCtrlMutex)
963 #define BNXE_LOCK_EXIT_ISLES_CONTROL(pUM) mutex_exit(&(pUM)->islesCtrlMutex)
964 #define BNXE_LOCK_ENTER_TOE(pUM) mutex_enter(&(pUM)->toeMutex)
965 #define BNXE_LOCK_EXIT_TOE(pUM) mutex_exit(&(pUM)->toeMutex)
966 #define BNXE_LOCK_ENTER_MEM(pUM) mutex_enter(&(pUM)->memMutex)
967 #define BNXE_LOCK_EXIT_MEM(pUM) mutex_exit(&(pUM)->memMutex)
968 #define BNXE_LOCK_ENTER_OFFLOAD(pUM) mutex_enter(&(pUM)->offloadMutex)
969 #define BNXE_LOCK_EXIT_OFFLOAD(pUM) mutex_exit(&(pUM)->offloadMutex)
970 #define BNXE_LOCK_ENTER_HWINIT(pUM) mutex_enter(&(pUM)->hwInitMutex)
971 #define BNXE_LOCK_EXIT_HWINIT(pUM) mutex_exit(&(pUM)->hwInitMutex)
972 #define BNXE_LOCK_ENTER_GLD(pUM) mutex_enter(&(pUM)->gldMutex)
973 #define BNXE_LOCK_EXIT_GLD(pUM) mutex_exit(&(pUM)->gldMutex)
974 #define BNXE_LOCK_ENTER_GLDTX(pUM, rw) rw_enter(&(pUM)->gldTxMutex, (rw))
975 #define BNXE_LOCK_EXIT_GLDTX(pUM) rw_exit(&(pUM)->gldTxMutex)
976 #define BNXE_LOCK_ENTER_TIMER(pUM) mutex_enter(&(pUM)->timerMutex)
977 #define BNXE_LOCK_EXIT_TIMER(pUM) mutex_exit(&(pUM)->timerMutex)
978 #define BNXE_LOCK_ENTER_STATS(pUM) mutex_enter(&(pUM)->kstatMutex)
979 #define BNXE_LOCK_EXIT_STATS(pUM) mutex_exit(&(pUM)->kstatMutex)
981 #else /* not BNXE_LOCKS_INLINE */
983 void BNXE_LOCK_ENTER_INTR(um_device_t
* pUM
, int idx
);
984 void BNXE_LOCK_EXIT_INTR(um_device_t
* pUM
, int idx
);
985 void BNXE_LOCK_ENTER_INTR_FLIP(um_device_t
* pUM
, int idx
);
986 void BNXE_LOCK_EXIT_INTR_FLIP(um_device_t
* pUM
, int idx
);
987 void BNXE_LOCK_ENTER_TX(um_device_t
* pUM
, int idx
);
988 void BNXE_LOCK_EXIT_TX(um_device_t
* pUM
, int idx
);
989 void BNXE_LOCK_ENTER_FREETX(um_device_t
* pUM
, int idx
);
990 void BNXE_LOCK_EXIT_FREETX(um_device_t
* pUM
, int idx
);
991 void BNXE_LOCK_ENTER_RX(um_device_t
* pUM
, int idx
);
992 void BNXE_LOCK_EXIT_RX(um_device_t
* pUM
, int idx
);
993 void BNXE_LOCK_ENTER_DONERX(um_device_t
* pUM
, int idx
);
994 void BNXE_LOCK_EXIT_DONERX(um_device_t
* pUM
, int idx
);
995 void BNXE_LOCK_ENTER_SB(um_device_t
* pUM
, int idx
);
996 void BNXE_LOCK_EXIT_SB(um_device_t
* pUM
, int idx
);
997 void BNXE_LOCK_ENTER_ETH_CON(um_device_t
* pUM
);
998 void BNXE_LOCK_EXIT_ETH_CON(um_device_t
* pUM
);
999 void BNXE_LOCK_ENTER_MCP(um_device_t
* pUM
);
1000 void BNXE_LOCK_EXIT_MCP(um_device_t
* pUM
);
1001 void BNXE_LOCK_ENTER_PHY(um_device_t
* pUM
);
1002 void BNXE_LOCK_EXIT_PHY(um_device_t
* pUM
);
1003 void BNXE_LOCK_ENTER_IND(um_device_t
* pUM
);
1004 void BNXE_LOCK_EXIT_IND(um_device_t
* pUM
);
1005 void BNXE_LOCK_ENTER_CID(um_device_t
* pUM
);
1006 void BNXE_LOCK_EXIT_CID(um_device_t
* pUM
);
1007 void BNXE_LOCK_ENTER_SPQ(um_device_t
* pUM
);
1008 void BNXE_LOCK_EXIT_SPQ(um_device_t
* pUM
);
1009 void BNXE_LOCK_ENTER_SPREQ(um_device_t
* pUM
);
1010 void BNXE_LOCK_EXIT_SPREQ(um_device_t
* pUM
);
1011 void BNXE_LOCK_ENTER_RRREQ(um_device_t
* pUM
);
1012 void BNXE_LOCK_EXIT_RRREQ(um_device_t
* pUM
);
1013 void BNXE_LOCK_ENTER_ISLES_CONTROL(um_device_t
* pUM
);
1014 void BNXE_LOCK_EXIT_ISLES_CONTROL(um_device_t
* pUM
);
1015 void BNXE_LOCK_ENTER_MEM(um_device_t
* pUM
);
1016 void BNXE_LOCK_EXIT_MEM(um_device_t
* pUM
);
1017 void BNXE_LOCK_ENTER_GLD(um_device_t
* pUM
);
1018 void BNXE_LOCK_EXIT_GLD(um_device_t
* pUM
);
1019 void BNXE_LOCK_ENTER_GLDTX(um_device_t
* pUM
, krw_t rw
);
1020 void BNXE_LOCK_EXIT_GLDTX(um_device_t
* pUM
);
1021 void BNXE_LOCK_ENTER_TIMER(um_device_t
* pUM
);
1022 void BNXE_LOCK_EXIT_TIMER(um_device_t
* pUM
);
1023 void BNXE_LOCK_ENTER_STATS(um_device_t
* pUM
);
1024 void BNXE_LOCK_EXIT_STATS(um_device_t
* pUM
);
1026 #endif /* BNXE_LOCKS_INLINE */
1028 #define CATC_TRIGGER(lmdev, data) { \
1029 REG_WR((lmdev), 0x2000, (data)); \
1031 #define CATC_TRIGGER_START(lmdev) CATC_TRIGGER((lmdev), 0xcafecafe)
1033 void BnxeDumpMem(um_device_t
* pUM
,
1037 void BnxeDumpPkt(um_device_t
* pUM
,
1040 boolean_t contents
);
1042 /* XXX yuck (beware return strings lengths with kstat and mdb) */
1044 inline boolean_t
BnxeIsClientBound(um_device_t
* pUM
)
1046 return (CLIENT_HW(pUM
, LM_CLI_IDX_NDIS
) ||
1047 CLIENT_BOUND(pUM
, LM_CLI_IDX_FCOE
));
1050 inline char * BnxeClientsHw(um_device_t
* pUM
)
1052 if (CLIENT_HW(pUM
, LM_CLI_IDX_NDIS
) &&
1053 CLIENT_HW(pUM
, LM_CLI_IDX_FCOE
)) { return "L2,FCoE"; }
1054 else if (CLIENT_HW(pUM
, LM_CLI_IDX_NDIS
)) { return "L2"; }
1055 else if (CLIENT_HW(pUM
, LM_CLI_IDX_FCOE
)) { return "FCoE"; }
1056 else { return "None"; }
1059 inline char * BnxeClientsDevi(um_device_t
* pUM
)
1061 if (CLIENT_DEVI(pUM
, LM_CLI_IDX_FCOE
)) { return "FCoE"; }
1062 else { return "None"; }
1065 inline char * BnxeClientsBound(um_device_t
* pUM
)
1067 if (CLIENT_HW(pUM
, LM_CLI_IDX_NDIS
) &&
1068 CLIENT_BOUND(pUM
, LM_CLI_IDX_FCOE
)) { return "L2,FCoE"; }
1069 else if (CLIENT_HW(pUM
, LM_CLI_IDX_NDIS
)) { return "L2"; }
1070 else if (CLIENT_BOUND(pUM
, LM_CLI_IDX_FCOE
)) { return "FCoE"; }
1071 else { return "None"; }