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7790 Want support for XXV710
[unleashed.git] / usr / src / uts / common / io / i40e / core / i40e_type.h
blob33314193bbdb965525ce730a30874e2d427e15e5
1 /******************************************************************************
2
3 Copyright (c) 2013-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #ifndef _I40E_TYPE_H_
36 #define _I40E_TYPE_H_
37
38 #include "i40e_status.h"
39 #include "i40e_osdep.h"
40 #include "i40e_register.h"
41 #include "i40e_adminq.h"
42 #include "i40e_hmc.h"
43 #include "i40e_lan_hmc.h"
44 #include "i40e_devids.h"
45
46
47 #define BIT(a) (1UL << (a))
48 #define BIT_ULL(a) (1ULL << (a))
49
50 #ifndef I40E_MASK
51 /* I40E_MASK is a macro used on 32 bit registers */
52 #define I40E_MASK(mask, shift) (((uint32_t)(mask)) << ((uint32_t)(shift)))
53 #endif
54
55 #define I40E_MAX_PF 16
56 #define I40E_MAX_PF_VSI 64
57 #define I40E_MAX_PF_QP 128
58 #define I40E_MAX_VSI_QP 16
59 #define I40E_MAX_VF_VSI 3
60 #define I40E_MAX_CHAINED_RX_BUFFERS 5
61 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
62
63 /* something less than 1 minute */
64 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50)
65
66 /* Max default timeout in ms, */
67 #define I40E_MAX_NVM_TIMEOUT 18000
68
69 /* Check whether address is multicast. */
70 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
71
72 /* Check whether an address is broadcast. */
73 #define I40E_IS_BROADCAST(address) \
74 ((((u8 *)(address))[0] == ((u8)0xff)) && \
75 (((u8 *)(address))[1] == ((u8)0xff)))
76
77 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
78 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
79
80 /* forward declaration */
81 struct i40e_hw;
82 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
83
84 #define I40E_ETH_LENGTH_OF_ADDRESS 6
85 /* Data type manipulation macros. */
86 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
87 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
88
89 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
90 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF))
91
92 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
93 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF))
94
95 /* Number of Transmit Descriptors must be a multiple of 8. */
96 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
97 /* Number of Receive Descriptors must be a multiple of 32 if
98 * the number of descriptors is greater than 32.
99 */
100 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
101
102 #define I40E_DESC_UNUSED(R) \
103 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
104 (R)->next_to_clean - (R)->next_to_use - 1)
105
106 /* bitfields for Tx queue mapping in QTX_CTL */
107 #define I40E_QTX_CTL_VF_QUEUE 0x0
108 #define I40E_QTX_CTL_VM_QUEUE 0x1
109 #define I40E_QTX_CTL_PF_QUEUE 0x2
110
111 /* debug masks - set these bits in hw->debug_mask to control output */
112 enum i40e_debug_mask {
113 I40E_DEBUG_INIT = 0x00000001,
114 I40E_DEBUG_RELEASE = 0x00000002,
115
116 I40E_DEBUG_LINK = 0x00000010,
117 I40E_DEBUG_PHY = 0x00000020,
118 I40E_DEBUG_HMC = 0x00000040,
119 I40E_DEBUG_NVM = 0x00000080,
120 I40E_DEBUG_LAN = 0x00000100,
121 I40E_DEBUG_FLOW = 0x00000200,
122 I40E_DEBUG_DCB = 0x00000400,
123 I40E_DEBUG_DIAG = 0x00000800,
124 I40E_DEBUG_FD = 0x00001000,
125
126 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
127 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
128 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
129 I40E_DEBUG_AQ_COMMAND = 0x06000000,
130 I40E_DEBUG_AQ = 0x0F000000,
131
132 I40E_DEBUG_USER = 0xF0000000,
133
134 I40E_DEBUG_ALL = 0xFFFFFFFF
135 };
136
137 /* PCI Bus Info */
138 #define I40E_PCI_LINK_STATUS 0xB2
139 #define I40E_PCI_LINK_WIDTH 0x3F0
140 #define I40E_PCI_LINK_WIDTH_1 0x10
141 #define I40E_PCI_LINK_WIDTH_2 0x20
142 #define I40E_PCI_LINK_WIDTH_4 0x40
143 #define I40E_PCI_LINK_WIDTH_8 0x80
144 #define I40E_PCI_LINK_SPEED 0xF
145 #define I40E_PCI_LINK_SPEED_2500 0x1
146 #define I40E_PCI_LINK_SPEED_5000 0x2
147 #define I40E_PCI_LINK_SPEED_8000 0x3
148
149 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
150 I40E_GLGEN_MSCA_STCODE_SHIFT)
151 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
152 I40E_GLGEN_MSCA_OPCODE_SHIFT)
153 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
154 I40E_GLGEN_MSCA_OPCODE_SHIFT)
155
156 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
157 I40E_GLGEN_MSCA_STCODE_SHIFT)
158 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
159 I40E_GLGEN_MSCA_OPCODE_SHIFT)
160 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
161 I40E_GLGEN_MSCA_OPCODE_SHIFT)
162 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
163 I40E_GLGEN_MSCA_OPCODE_SHIFT)
164 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
165 I40E_GLGEN_MSCA_OPCODE_SHIFT)
166
167 #define I40E_PHY_COM_REG_PAGE 0x1E
168 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
169 #define I40E_PHY_LED_MANUAL_ON 0x100
170 #define I40E_PHY_LED_PROV_REG_1 0xC430
171 #define I40E_PHY_LED_MODE_MASK 0xFFFF
172 #define I40E_PHY_LED_MODE_ORIG 0x80000000
173
174 /* Memory types */
175 enum i40e_memset_type {
176 I40E_NONDMA_MEM = 0,
177 I40E_DMA_MEM
178 };
179
180 /* Memcpy types */
181 enum i40e_memcpy_type {
182 I40E_NONDMA_TO_NONDMA = 0,
183 I40E_NONDMA_TO_DMA,
184 I40E_DMA_TO_DMA,
185 I40E_DMA_TO_NONDMA
186 };
187
188 #define I40E_FW_API_VERSION_MINOR_X722 0x0005
189 #define I40E_FW_API_VERSION_MINOR_X710 0x0005
190
191
192 /* These are structs for managing the hardware information and the operations.
193 * The structures of function pointers are filled out at init time when we
194 * know for sure exactly which hardware we're working with. This gives us the
195 * flexibility of using the same main driver code but adapting to slightly
196 * different hardware needs as new parts are developed. For this architecture,
197 * the Firmware and AdminQ are intended to insulate the driver from most of the
198 * future changes, but these structures will also do part of the job.
199 */
200 enum i40e_mac_type {
201 I40E_MAC_UNKNOWN = 0,
202 I40E_MAC_X710,
203 I40E_MAC_XL710,
204 I40E_MAC_VF,
205 I40E_MAC_X722,
206 I40E_MAC_X722_VF,
207 I40E_MAC_GENERIC,
208 };
209
210 enum i40e_media_type {
211 I40E_MEDIA_TYPE_UNKNOWN = 0,
212 I40E_MEDIA_TYPE_FIBER,
213 I40E_MEDIA_TYPE_BASET,
214 I40E_MEDIA_TYPE_BACKPLANE,
215 I40E_MEDIA_TYPE_CX4,
216 I40E_MEDIA_TYPE_DA,
217 I40E_MEDIA_TYPE_VIRTUAL
218 };
219
220 enum i40e_fc_mode {
221 I40E_FC_NONE = 0,
222 I40E_FC_RX_PAUSE,
223 I40E_FC_TX_PAUSE,
224 I40E_FC_FULL,
225 I40E_FC_PFC,
226 I40E_FC_DEFAULT
227 };
228
229 enum i40e_set_fc_aq_failures {
230 I40E_SET_FC_AQ_FAIL_NONE = 0,
231 I40E_SET_FC_AQ_FAIL_GET = 1,
232 I40E_SET_FC_AQ_FAIL_SET = 2,
233 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
234 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
235 };
236
237 enum i40e_vsi_type {
238 I40E_VSI_MAIN = 0,
239 I40E_VSI_VMDQ1 = 1,
240 I40E_VSI_VMDQ2 = 2,
241 I40E_VSI_CTRL = 3,
242 I40E_VSI_FCOE = 4,
243 I40E_VSI_MIRROR = 5,
244 I40E_VSI_SRIOV = 6,
245 I40E_VSI_FDIR = 7,
246 I40E_VSI_TYPE_UNKNOWN
247 };
248
249 enum i40e_queue_type {
250 I40E_QUEUE_TYPE_RX = 0,
251 I40E_QUEUE_TYPE_TX,
252 I40E_QUEUE_TYPE_PE_CEQ,
253 I40E_QUEUE_TYPE_UNKNOWN
254 };
255
256 struct i40e_link_status {
257 enum i40e_aq_phy_type phy_type;
258 enum i40e_aq_link_speed link_speed;
259 u8 link_info;
260 u8 an_info;
261 u8 ext_info;
262 u8 loopback;
263 /* is Link Status Event notification to SW enabled */
264 bool lse_enable;
265 u16 max_frame_size;
266 bool crc_enable;
267 u8 pacing;
268 u8 requested_speeds;
269 u8 module_type[3];
270 /* 1st byte: module identifier */
271 #define I40E_MODULE_TYPE_SFP 0x03
272 #define I40E_MODULE_TYPE_QSFP 0x0D
273 /* 2nd byte: ethernet compliance codes for 10/40G */
274 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
275 #define I40E_MODULE_TYPE_40G_LR4 0x02
276 #define I40E_MODULE_TYPE_40G_SR4 0x04
277 #define I40E_MODULE_TYPE_40G_CR4 0x08
278 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
279 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
280 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
281 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
282 /* 3rd byte: ethernet compliance codes for 1G */
283 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
284 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
285 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
286 #define I40E_MODULE_TYPE_1000BASE_T 0x08
287 };
288
289 struct i40e_phy_info {
290 struct i40e_link_status link_info;
291 struct i40e_link_status link_info_old;
292 bool get_link_info;
293 enum i40e_media_type media_type;
294 /* all the phy types the NVM is capable of */
295 u64 phy_types;
296 };
297
298 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
299 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
300 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
301 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
302 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
303 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
304 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
305 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
306 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
307 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
308 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
309 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
310 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
311 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
312 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
313 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
314 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
315 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
316 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
317 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
318 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
319 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
320 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
321 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
322 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
323 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
324 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
325 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
326 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
327 #define I40E_CAP_PHY_TYPE_25GBASE_KR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_KR, 32)
328 #define I40E_CAP_PHY_TYPE_25GBASE_CR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_CR, 32)
329 #define I40E_CAP_PHY_TYPE_25GBASE_SR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_SR, 32)
330 #define I40E_CAP_PHY_TYPE_25GBASE_LR I40E_MASK((u64)I40E_AQ_PHY_TYPE_EXT_25G_LR, 32)
331 #define I40E_HW_CAP_MAX_GPIO 30
332 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
333 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
334
335 enum i40e_acpi_programming_method {
336 I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
337 I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
338 };
339
340 #define I40E_WOL_SUPPORT_MASK 1
341 #define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1)
342 #define I40E_PROXY_SUPPORT_MASK (1 << 2)
343
344 /* Capabilities of a PF or a VF or the whole device */
345 struct i40e_hw_capabilities {
346 u32 switch_mode;
347 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
348 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
349 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
350
351 u32 management_mode;
352 u32 mng_protocols_over_mctp;
353 #define I40E_MNG_PROTOCOL_PLDM 0x2
354 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
355 #define I40E_MNG_PROTOCOL_NCSI 0x8
356 u32 npar_enable;
357 u32 os2bmc;
358 u32 valid_functions;
359 bool sr_iov_1_1;
360 bool vmdq;
361 bool evb_802_1_qbg; /* Edge Virtual Bridging */
362 bool evb_802_1_qbh; /* Bridge Port Extension */
363 bool dcb;
364 bool fcoe;
365 bool iscsi; /* Indicates iSCSI enabled */
366 bool flex10_enable;
367 bool flex10_capable;
368 u32 flex10_mode;
369 #define I40E_FLEX10_MODE_UNKNOWN 0x0
370 #define I40E_FLEX10_MODE_DCC 0x1
371 #define I40E_FLEX10_MODE_DCI 0x2
372
373 u32 flex10_status;
374 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
375 #define I40E_FLEX10_STATUS_VC_MODE 0x2
376
377 bool sec_rev_disabled;
378 bool update_disabled;
379 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
380 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
381
382 bool mgmt_cem;
383 bool ieee_1588;
384 bool iwarp;
385 bool fd;
386 u32 fd_filters_guaranteed;
387 u32 fd_filters_best_effort;
388 bool rss;
389 u32 rss_table_size;
390 u32 rss_table_entry_width;
391 bool led[I40E_HW_CAP_MAX_GPIO];
392 bool sdp[I40E_HW_CAP_MAX_GPIO];
393 u32 nvm_image_type;
394 u32 num_flow_director_filters;
395 u32 num_vfs;
396 u32 vf_base_id;
397 u32 num_vsis;
398 u32 num_rx_qp;
399 u32 num_tx_qp;
400 u32 base_queue;
401 u32 num_msix_vectors;
402 u32 num_msix_vectors_vf;
403 u32 led_pin_num;
404 u32 sdp_pin_num;
405 u32 mdio_port_num;
406 u32 mdio_port_mode;
407 u8 rx_buf_chain_len;
408 u32 enabled_tcmap;
409 u32 maxtc;
410 u64 wr_csr_prot;
411 bool apm_wol_support;
412 enum i40e_acpi_programming_method acpi_prog_method;
413 bool proxy_support;
414 };
415
416 struct i40e_mac_info {
417 enum i40e_mac_type type;
418 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
419 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
420 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
421 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
422 u16 max_fcoeq;
423 };
424
425 enum i40e_aq_resources_ids {
426 I40E_NVM_RESOURCE_ID = 1
427 };
428
429 enum i40e_aq_resource_access_type {
430 I40E_RESOURCE_READ = 1,
431 I40E_RESOURCE_WRITE
432 };
433
434 struct i40e_nvm_info {
435 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
436 u32 timeout; /* [ms] */
437 u16 sr_size; /* Shadow RAM size in words */
438 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
439 u16 version; /* NVM package version */
440 u32 eetrack; /* NVM data version */
441 u32 oem_ver; /* OEM version info */
442 };
443
444 /* definitions used in NVM update support */
445
446 enum i40e_nvmupd_cmd {
447 I40E_NVMUPD_INVALID,
448 I40E_NVMUPD_READ_CON,
449 I40E_NVMUPD_READ_SNT,
450 I40E_NVMUPD_READ_LCB,
451 I40E_NVMUPD_READ_SA,
452 I40E_NVMUPD_WRITE_ERA,
453 I40E_NVMUPD_WRITE_CON,
454 I40E_NVMUPD_WRITE_SNT,
455 I40E_NVMUPD_WRITE_LCB,
456 I40E_NVMUPD_WRITE_SA,
457 I40E_NVMUPD_CSUM_CON,
458 I40E_NVMUPD_CSUM_SA,
459 I40E_NVMUPD_CSUM_LCB,
460 I40E_NVMUPD_STATUS,
461 I40E_NVMUPD_EXEC_AQ,
462 I40E_NVMUPD_GET_AQ_RESULT,
463 };
464
465 enum i40e_nvmupd_state {
466 I40E_NVMUPD_STATE_INIT,
467 I40E_NVMUPD_STATE_READING,
468 I40E_NVMUPD_STATE_WRITING,
469 I40E_NVMUPD_STATE_INIT_WAIT,
470 I40E_NVMUPD_STATE_WRITE_WAIT,
471 I40E_NVMUPD_STATE_ERROR
472 };
473
474 /* nvm_access definition and its masks/shifts need to be accessible to
475 * application, core driver, and shared code. Where is the right file?
476 */
477 #define I40E_NVM_READ 0xB
478 #define I40E_NVM_WRITE 0xC
479
480 #define I40E_NVM_MOD_PNT_MASK 0xFF
481
482 #define I40E_NVM_TRANS_SHIFT 8
483 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
484 #define I40E_NVM_CON 0x0
485 #define I40E_NVM_SNT 0x1
486 #define I40E_NVM_LCB 0x2
487 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
488 #define I40E_NVM_ERA 0x4
489 #define I40E_NVM_CSUM 0x8
490 #define I40E_NVM_EXEC 0xf
491
492 #define I40E_NVM_ADAPT_SHIFT 16
493 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT)
494
495 #define I40E_NVMUPD_MAX_DATA 4096
496 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
497
498 struct i40e_nvm_access {
499 u32 command;
500 u32 config;
501 u32 offset; /* in bytes */
502 u32 data_size; /* in bytes */
503 u8 data[1];
504 };
505
506 /* PCI bus types */
507 enum i40e_bus_type {
508 i40e_bus_type_unknown = 0,
509 i40e_bus_type_pci,
510 i40e_bus_type_pcix,
511 i40e_bus_type_pci_express,
512 i40e_bus_type_reserved
513 };
514
515 /* PCI bus speeds */
516 enum i40e_bus_speed {
517 i40e_bus_speed_unknown = 0,
518 i40e_bus_speed_33 = 33,
519 i40e_bus_speed_66 = 66,
520 i40e_bus_speed_100 = 100,
521 i40e_bus_speed_120 = 120,
522 i40e_bus_speed_133 = 133,
523 i40e_bus_speed_2500 = 2500,
524 i40e_bus_speed_5000 = 5000,
525 i40e_bus_speed_8000 = 8000,
526 i40e_bus_speed_reserved
527 };
528
529 /* PCI bus widths */
530 enum i40e_bus_width {
531 i40e_bus_width_unknown = 0,
532 i40e_bus_width_pcie_x1 = 1,
533 i40e_bus_width_pcie_x2 = 2,
534 i40e_bus_width_pcie_x4 = 4,
535 i40e_bus_width_pcie_x8 = 8,
536 i40e_bus_width_32 = 32,
537 i40e_bus_width_64 = 64,
538 i40e_bus_width_reserved
539 };
540
541 /* Bus parameters */
542 struct i40e_bus_info {
543 enum i40e_bus_speed speed;
544 enum i40e_bus_width width;
545 enum i40e_bus_type type;
546
547 u16 func;
548 u16 device;
549 u16 lan_id;
550 u16 bus_id;
551 };
552
553 /* Flow control (FC) parameters */
554 struct i40e_fc_info {
555 enum i40e_fc_mode current_mode; /* FC mode in effect */
556 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
557 };
558
559 #define I40E_MAX_TRAFFIC_CLASS 8
560 #define I40E_MAX_USER_PRIORITY 8
561 #define I40E_DCBX_MAX_APPS 32
562 #define I40E_LLDPDU_SIZE 1500
563 #define I40E_TLV_STATUS_OPER 0x1
564 #define I40E_TLV_STATUS_SYNC 0x2
565 #define I40E_TLV_STATUS_ERR 0x4
566 #define I40E_CEE_OPER_MAX_APPS 3
567 #define I40E_APP_PROTOID_FCOE 0x8906
568 #define I40E_APP_PROTOID_ISCSI 0x0cbc
569 #define I40E_APP_PROTOID_FIP 0x8914
570 #define I40E_APP_SEL_ETHTYPE 0x1
571 #define I40E_APP_SEL_TCPIP 0x2
572 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
573 #define I40E_CEE_APP_SEL_TCPIP 0x1
574
575 /* CEE or IEEE 802.1Qaz ETS Configuration data */
576 struct i40e_dcb_ets_config {
577 u8 willing;
578 u8 cbs;
579 u8 maxtcs;
580 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
581 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
582 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
583 };
584
585 /* CEE or IEEE 802.1Qaz PFC Configuration data */
586 struct i40e_dcb_pfc_config {
587 u8 willing;
588 u8 mbc;
589 u8 pfccap;
590 u8 pfcenable;
591 };
592
593 /* CEE or IEEE 802.1Qaz Application Priority data */
594 struct i40e_dcb_app_priority_table {
595 u8 priority;
596 u8 selector;
597 u16 protocolid;
598 };
599
600 struct i40e_dcbx_config {
601 u8 dcbx_mode;
602 #define I40E_DCBX_MODE_CEE 0x1
603 #define I40E_DCBX_MODE_IEEE 0x2
604 u8 app_mode;
605 #define I40E_DCBX_APPS_NON_WILLING 0x1
606 u32 numapps;
607 u32 tlv_status; /* CEE mode TLV status */
608 struct i40e_dcb_ets_config etscfg;
609 struct i40e_dcb_ets_config etsrec;
610 struct i40e_dcb_pfc_config pfc;
611 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
612 };
613
614 /* Port hardware description */
615 struct i40e_hw {
616 u8 *hw_addr;
617 void *back;
618
619 /* subsystem structs */
620 struct i40e_phy_info phy;
621 struct i40e_mac_info mac;
622 struct i40e_bus_info bus;
623 struct i40e_nvm_info nvm;
624 struct i40e_fc_info fc;
625
626 /* pci info */
627 u16 device_id;
628 u16 vendor_id;
629 u16 subsystem_device_id;
630 u16 subsystem_vendor_id;
631 u8 revision_id;
632 u8 port;
633 bool adapter_stopped;
634
635 /* capabilities for entire device and PCI func */
636 struct i40e_hw_capabilities dev_caps;
637 struct i40e_hw_capabilities func_caps;
638
639 /* Flow Director shared filter space */
640 u16 fdir_shared_filter_count;
641
642 /* device profile info */
643 u8 pf_id;
644 u16 main_vsi_seid;
645
646 /* for multi-function MACs */
647 u16 partition_id;
648 u16 num_partitions;
649 u16 num_ports;
650
651 /* Closest numa node to the device */
652 u16 numa_node;
653
654 /* Admin Queue info */
655 struct i40e_adminq_info aq;
656
657 /* state of nvm update process */
658 enum i40e_nvmupd_state nvmupd_state;
659 struct i40e_aq_desc nvm_wb_desc;
660 struct i40e_virt_mem nvm_buff;
661 bool nvm_release_on_done;
662 u16 nvm_wait_opcode;
663
664 /* HMC info */
665 struct i40e_hmc_info hmc; /* HMC info struct */
666
667 /* LLDP/DCBX Status */
668 u16 dcbx_status;
669
670 /* DCBX info */
671 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
672 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
673 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
674
675 /* WoL and proxy support */
676 u16 num_wol_proxy_filters;
677 u16 wol_proxy_vsi_seid;
678
679 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
680 u64 flags;
681
682 /* debug mask */
683 u32 debug_mask;
684 char err_str[16];
685 };
686
687 static INLINE bool i40e_is_vf(struct i40e_hw *hw)
688 {
689 return (hw->mac.type == I40E_MAC_VF ||
690 hw->mac.type == I40E_MAC_X722_VF);
691 }
692
693 struct i40e_driver_version {
694 u8 major_version;
695 u8 minor_version;
696 u8 build_version;
697 u8 subbuild_version;
698 u8 driver_string[32];
699 };
700
701 /* RX Descriptors */
702 union i40e_16byte_rx_desc {
703 struct {
704 __le64 pkt_addr; /* Packet buffer address */
705 __le64 hdr_addr; /* Header buffer address */
706 } read;
707 struct {
708 struct {
709 struct {
710 union {
711 __le16 mirroring_status;
712 __le16 fcoe_ctx_id;
713 } mirr_fcoe;
714 __le16 l2tag1;
715 } lo_dword;
716 union {
717 __le32 rss; /* RSS Hash */
718 __le32 fd_id; /* Flow director filter id */
719 __le32 fcoe_param; /* FCoE DDP Context id */
720 } hi_dword;
721 } qword0;
722 struct {
723 /* ext status/error/pktype/length */
724 __le64 status_error_len;
725 } qword1;
726 } wb; /* writeback */
727 };
728
729 union i40e_32byte_rx_desc {
730 struct {
731 __le64 pkt_addr; /* Packet buffer address */
732 __le64 hdr_addr; /* Header buffer address */
733 /* bit 0 of hdr_buffer_addr is DD bit */
734 __le64 rsvd1;
735 __le64 rsvd2;
736 } read;
737 struct {
738 struct {
739 struct {
740 union {
741 __le16 mirroring_status;
742 __le16 fcoe_ctx_id;
743 } mirr_fcoe;
744 __le16 l2tag1;
745 } lo_dword;
746 union {
747 __le32 rss; /* RSS Hash */
748 __le32 fcoe_param; /* FCoE DDP Context id */
749 /* Flow director filter id in case of
750 * Programming status desc WB
751 */
752 __le32 fd_id;
753 } hi_dword;
754 } qword0;
755 struct {
756 /* status/error/pktype/length */
757 __le64 status_error_len;
758 } qword1;
759 struct {
760 __le16 ext_status; /* extended status */
761 __le16 rsvd;
762 __le16 l2tag2_1;
763 __le16 l2tag2_2;
764 } qword2;
765 struct {
766 union {
767 __le32 flex_bytes_lo;
768 __le32 pe_status;
769 } lo_dword;
770 union {
771 __le32 flex_bytes_hi;
772 __le32 fd_id;
773 } hi_dword;
774 } qword3;
775 } wb; /* writeback */
776 };
777
778 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8
779 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
780 I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
781 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0
782 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \
783 I40E_RXD_QW0_FCOEINDX_SHIFT)
784
785 enum i40e_rx_desc_status_bits {
786 /* Note: These are predefined bit offsets */
787 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
788 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
789 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
790 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
791 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
792 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
793 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
794 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
795
796 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
797 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
798 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
799 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
800 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
801 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
802 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
803 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
804 };
805
806 #define I40E_RXD_QW1_STATUS_SHIFT 0
807 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
808 I40E_RXD_QW1_STATUS_SHIFT)
809
810 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
811 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
812 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
813
814 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
815 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
816
817 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST
818 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \
819 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
820
821 enum i40e_rx_desc_fltstat_values {
822 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
823 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
824 I40E_RX_DESC_FLTSTAT_RSV = 2,
825 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
826 };
827
828 #define I40E_RXD_PACKET_TYPE_UNICAST 0
829 #define I40E_RXD_PACKET_TYPE_MULTICAST 1
830 #define I40E_RXD_PACKET_TYPE_BROADCAST 2
831 #define I40E_RXD_PACKET_TYPE_MIRRORED 3
832
833 #define I40E_RXD_QW1_ERROR_SHIFT 19
834 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
835
836 enum i40e_rx_desc_error_bits {
837 /* Note: These are predefined bit offsets */
838 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
839 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
840 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
841 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
842 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
843 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
844 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
845 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
846 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
847 };
848
849 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
850 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
851 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
852 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
853 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
854 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
855 };
856
857 #define I40E_RXD_QW1_PTYPE_SHIFT 30
858 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
859
860 /* Packet type non-ip values */
861 enum i40e_rx_l2_ptype {
862 I40E_RX_PTYPE_L2_RESERVED = 0,
863 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
864 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
865 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
866 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
867 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
868 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
869 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
870 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
871 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
872 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
873 I40E_RX_PTYPE_L2_ARP = 11,
874 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
875 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
876 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
877 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
878 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
879 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
880 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
881 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
882 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
883 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
884 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
885 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
886 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
887 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
888 };
889
890 struct i40e_rx_ptype_decoded {
891 u32 ptype:8;
892 u32 known:1;
893 u32 outer_ip:1;
894 u32 outer_ip_ver:1;
895 u32 outer_frag:1;
896 u32 tunnel_type:3;
897 u32 tunnel_end_prot:2;
898 u32 tunnel_end_frag:1;
899 u32 inner_prot:4;
900 u32 payload_layer:3;
901 };
902
903 enum i40e_rx_ptype_outer_ip {
904 I40E_RX_PTYPE_OUTER_L2 = 0,
905 I40E_RX_PTYPE_OUTER_IP = 1
906 };
907
908 enum i40e_rx_ptype_outer_ip_ver {
909 I40E_RX_PTYPE_OUTER_NONE = 0,
910 I40E_RX_PTYPE_OUTER_IPV4 = 0,
911 I40E_RX_PTYPE_OUTER_IPV6 = 1
912 };
913
914 enum i40e_rx_ptype_outer_fragmented {
915 I40E_RX_PTYPE_NOT_FRAG = 0,
916 I40E_RX_PTYPE_FRAG = 1
917 };
918
919 enum i40e_rx_ptype_tunnel_type {
920 I40E_RX_PTYPE_TUNNEL_NONE = 0,
921 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
922 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
923 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
924 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
925 };
926
927 enum i40e_rx_ptype_tunnel_end_prot {
928 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
929 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
930 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
931 };
932
933 enum i40e_rx_ptype_inner_prot {
934 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
935 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
936 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
937 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
938 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
939 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
940 };
941
942 enum i40e_rx_ptype_payload_layer {
943 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
944 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
945 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
946 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
947 };
948
949 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF
950 #define I40E_RX_PTYPE_SHIFT 56
951
952 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
953 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
954 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
955
956 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
957 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
958 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
959
960 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
961 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
962
963 #define I40E_RXD_QW1_NEXTP_SHIFT 38
964 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
965
966 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0
967 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \
968 I40E_RXD_QW2_EXT_STATUS_SHIFT)
969
970 enum i40e_rx_desc_ext_status_bits {
971 /* Note: These are predefined bit offsets */
972 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
973 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
974 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
975 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
976 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
977 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
978 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
979 };
980
981 #define I40E_RXD_QW2_L2TAG2_SHIFT 0
982 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
983
984 #define I40E_RXD_QW2_L2TAG3_SHIFT 16
985 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
986
987 enum i40e_rx_desc_pe_status_bits {
988 /* Note: These are predefined bit offsets */
989 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
990 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
991 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
992 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
993 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
994 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
995 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
996 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
997 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
998 };
999
1000 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
1001 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
1002
1003 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
1004 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
1005 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1006
1007 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0
1008 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \
1009 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1010
1011 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
1012 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
1013 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1014
1015 enum i40e_rx_prog_status_desc_status_bits {
1016 /* Note: These are predefined bit offsets */
1017 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
1018 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
1019 };
1020
1021 enum i40e_rx_prog_status_desc_prog_id_masks {
1022 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
1023 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
1024 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
1025 };
1026
1027 enum i40e_rx_prog_status_desc_error_bits {
1028 /* Note: These are predefined bit offsets */
1029 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
1030 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
1031 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
1032 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
1033 };
1034
1035 #define I40E_TWO_BIT_MASK 0x3
1036 #define I40E_THREE_BIT_MASK 0x7
1037 #define I40E_FOUR_BIT_MASK 0xF
1038 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF
1039
1040 /* TX Descriptor */
1041 struct i40e_tx_desc {
1042 __le64 buffer_addr; /* Address of descriptor's data buf */
1043 __le64 cmd_type_offset_bsz;
1044 };
1045
1046 #define I40E_TXD_QW1_DTYPE_SHIFT 0
1047 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1048
1049 enum i40e_tx_desc_dtype_value {
1050 I40E_TX_DESC_DTYPE_DATA = 0x0,
1051 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
1052 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
1053 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
1054 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
1055 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
1056 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
1057 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
1058 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
1059 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
1060 };
1061
1062 #define I40E_TXD_QW1_CMD_SHIFT 4
1063 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1064
1065 enum i40e_tx_desc_cmd_bits {
1066 I40E_TX_DESC_CMD_EOP = 0x0001,
1067 I40E_TX_DESC_CMD_RS = 0x0002,
1068 I40E_TX_DESC_CMD_ICRC = 0x0004,
1069 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
1070 I40E_TX_DESC_CMD_DUMMY = 0x0010,
1071 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
1072 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
1073 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
1074 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
1075 I40E_TX_DESC_CMD_FCOET = 0x0080,
1076 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
1077 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
1078 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
1079 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
1080 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
1081 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
1082 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
1083 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
1084 };
1085
1086 #define I40E_TXD_QW1_OFFSET_SHIFT 16
1087 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
1088 I40E_TXD_QW1_OFFSET_SHIFT)
1089
1090 enum i40e_tx_desc_length_fields {
1091 /* Note: These are predefined bit offsets */
1092 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
1093 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1094 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1095 };
1096
1097 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1098 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1099 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1100 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1101
1102 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1103 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1104 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1105
1106 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1107 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1108
1109 /* Context descriptors */
1110 struct i40e_tx_context_desc {
1111 __le32 tunneling_params;
1112 __le16 l2tag2;
1113 __le16 rsvd;
1114 __le64 type_cmd_tso_mss;
1115 };
1116
1117 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1118 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1119
1120 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1121 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1122
1123 enum i40e_tx_ctx_desc_cmd_bits {
1124 I40E_TX_CTX_DESC_TSO = 0x01,
1125 I40E_TX_CTX_DESC_TSYN = 0x02,
1126 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1127 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1128 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1129 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1130 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1131 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1132 I40E_TX_CTX_DESC_SWPE = 0x40
1133 };
1134
1135 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1136 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1137 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1138
1139 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1140 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1141 I40E_TXD_CTX_QW1_MSS_SHIFT)
1142
1143 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1144 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1145
1146 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1147 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1148 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1149
1150 enum i40e_tx_ctx_desc_eipt_offload {
1151 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1152 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1153 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1154 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1155 };
1156
1157 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1158 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1159 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1160
1161 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1162 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1163
1164 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1165 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1166
1167 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1168 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1169
1170 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1171
1172 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1173 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1174 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1175
1176 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1177 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1178 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1179
1180 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1181 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1182 struct i40e_nop_desc {
1183 __le64 rsvd;
1184 __le64 dtype_cmd;
1185 };
1186
1187 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0
1188 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1189
1190 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4
1191 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1192
1193 enum i40e_tx_nop_desc_cmd_bits {
1194 /* Note: These are predefined bit offsets */
1195 I40E_TX_NOP_DESC_EOP_SHIFT = 0,
1196 I40E_TX_NOP_DESC_RS_SHIFT = 1,
1197 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
1198 };
1199
1200 struct i40e_filter_program_desc {
1201 __le32 qindex_flex_ptype_vsi;
1202 __le32 rsvd;
1203 __le32 dtype_cmd_cntindex;
1204 __le32 fd_id;
1205 };
1206 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1207 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1208 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1209 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1210 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1211 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1212 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1213 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1214 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1215
1216 /* Packet Classifier Types for filters */
1217 enum i40e_filter_pctype {
1218 /* Note: Values 0-28 are reserved for future use.
1219 * Value 29, 30, 32 are not supported on XL710 and X710.
1220 */
1221 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1222 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1223 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1224 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1225 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1226 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1227 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1228 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1229 /* Note: Values 37-38 are reserved for future use.
1230 * Value 39, 40, 42 are not supported on XL710 and X710.
1231 */
1232 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1233 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1234 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1235 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1236 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1237 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1238 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1239 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1240 /* Note: Value 47 is reserved for future use */
1241 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1242 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1243 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1244 /* Note: Values 51-62 are reserved for future use */
1245 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1246 };
1247
1248 enum i40e_filter_program_desc_dest {
1249 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1250 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1251 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1252 };
1253
1254 enum i40e_filter_program_desc_fd_status {
1255 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1256 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1257 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1258 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1259 };
1260
1261 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1262 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1263 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1264
1265 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0
1266 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1267
1268 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1269 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1270 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1271
1272 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1273 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1274
1275 enum i40e_filter_program_desc_pcmd {
1276 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1277 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1278 };
1279
1280 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1281 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1282
1283 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1284 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1285
1286 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1287 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1288 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1289 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1290
1291 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1292 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1293 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1294
1295 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1296 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1297 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1298
1299 enum i40e_filter_type {
1300 I40E_FLOW_DIRECTOR_FLTR = 0,
1301 I40E_PE_QUAD_HASH_FLTR = 1,
1302 I40E_ETHERTYPE_FLTR,
1303 I40E_FCOE_CTX_FLTR,
1304 I40E_MAC_VLAN_FLTR,
1305 I40E_HASH_FLTR
1306 };
1307
1308 struct i40e_vsi_context {
1309 u16 seid;
1310 u16 uplink_seid;
1311 u16 vsi_number;
1312 u16 vsis_allocated;
1313 u16 vsis_unallocated;
1314 u16 flags;
1315 u8 pf_num;
1316 u8 vf_num;
1317 u8 connection_type;
1318 struct i40e_aqc_vsi_properties_data info;
1319 };
1320
1321 struct i40e_veb_context {
1322 u16 seid;
1323 u16 uplink_seid;
1324 u16 veb_number;
1325 u16 vebs_allocated;
1326 u16 vebs_unallocated;
1327 u16 flags;
1328 struct i40e_aqc_get_veb_parameters_completion info;
1329 };
1330
1331 /* Statistics collected by each port, VSI, VEB, and S-channel */
1332 struct i40e_eth_stats {
1333 u64 rx_bytes; /* gorc */
1334 u64 rx_unicast; /* uprc */
1335 u64 rx_multicast; /* mprc */
1336 u64 rx_broadcast; /* bprc */
1337 u64 rx_discards; /* rdpc */
1338 u64 rx_unknown_protocol; /* rupp */
1339 u64 tx_bytes; /* gotc */
1340 u64 tx_unicast; /* uptc */
1341 u64 tx_multicast; /* mptc */
1342 u64 tx_broadcast; /* bptc */
1343 u64 tx_discards; /* tdpc */
1344 u64 tx_errors; /* tepc */
1345 };
1346
1347 /* Statistics collected per VEB per TC */
1348 struct i40e_veb_tc_stats {
1349 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1350 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1351 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1352 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1353 };
1354
1355 /* Statistics collected by the MAC */
1356 struct i40e_hw_port_stats {
1357 /* eth stats collected by the port */
1358 struct i40e_eth_stats eth;
1359
1360 /* additional port specific stats */
1361 u64 tx_dropped_link_down; /* tdold */
1362 u64 crc_errors; /* crcerrs */
1363 u64 illegal_bytes; /* illerrc */
1364 u64 error_bytes; /* errbc */
1365 u64 mac_local_faults; /* mlfc */
1366 u64 mac_remote_faults; /* mrfc */
1367 u64 rx_length_errors; /* rlec */
1368 u64 link_xon_rx; /* lxonrxc */
1369 u64 link_xoff_rx; /* lxoffrxc */
1370 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1371 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1372 u64 link_xon_tx; /* lxontxc */
1373 u64 link_xoff_tx; /* lxofftxc */
1374 u64 priority_xon_tx[8]; /* pxontxc[8] */
1375 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1376 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1377 u64 rx_size_64; /* prc64 */
1378 u64 rx_size_127; /* prc127 */
1379 u64 rx_size_255; /* prc255 */
1380 u64 rx_size_511; /* prc511 */
1381 u64 rx_size_1023; /* prc1023 */
1382 u64 rx_size_1522; /* prc1522 */
1383 u64 rx_size_big; /* prc9522 */
1384 u64 rx_undersize; /* ruc */
1385 u64 rx_fragments; /* rfc */
1386 u64 rx_oversize; /* roc */
1387 u64 rx_jabber; /* rjc */
1388 u64 tx_size_64; /* ptc64 */
1389 u64 tx_size_127; /* ptc127 */
1390 u64 tx_size_255; /* ptc255 */
1391 u64 tx_size_511; /* ptc511 */
1392 u64 tx_size_1023; /* ptc1023 */
1393 u64 tx_size_1522; /* ptc1522 */
1394 u64 tx_size_big; /* ptc9522 */
1395 u64 mac_short_packet_dropped; /* mspdc */
1396 u64 checksum_error; /* xec */
1397 /* flow director stats */
1398 u64 fd_atr_match;
1399 u64 fd_sb_match;
1400 u64 fd_atr_tunnel_match;
1401 u32 fd_atr_status;
1402 u32 fd_sb_status;
1403 /* EEE LPI */
1404 u32 tx_lpi_status;
1405 u32 rx_lpi_status;
1406 u64 tx_lpi_count; /* etlpic */
1407 u64 rx_lpi_count; /* erlpic */
1408 };
1409
1410 /* Checksum and Shadow RAM pointers */
1411 #define I40E_SR_NVM_CONTROL_WORD 0x00
1412 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03
1413 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04
1414 #define I40E_SR_OPTION_ROM_PTR 0x05
1415 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06
1416 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07
1417 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08
1418 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09
1419 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A
1420 #define I40E_SR_EMP_IMAGE_PTR 0x0B
1421 #define I40E_SR_PE_IMAGE_PTR 0x0C
1422 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D
1423 #define I40E_SR_MNG_CONFIG_PTR 0x0E
1424 #define I40E_SR_EMP_MODULE_PTR 0x0F
1425 #define I40E_SR_PBA_FLAGS 0x15
1426 #define I40E_SR_PBA_BLOCK_PTR 0x16
1427 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1428 #define I40E_NVM_OEM_VER_OFF 0x83
1429 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1430 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1431 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1432 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
1433 #define I40E_SR_NVM_MAP_VERSION 0x29
1434 #define I40E_SR_NVM_IMAGE_VERSION 0x2A
1435 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B
1436 #define I40E_SR_NVM_EETRACK_LO 0x2D
1437 #define I40E_SR_NVM_EETRACK_HI 0x2E
1438 #define I40E_SR_VPD_PTR 0x2F
1439 #define I40E_SR_PXE_SETUP_PTR 0x30
1440 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
1441 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
1442 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
1443 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
1444 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
1445 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
1446 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
1447 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
1448 #define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
1449 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1450 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1451 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
1452 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
1453 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
1454 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
1455 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1456 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
1457 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
1458 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
1459
1460 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1461 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1462 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1463 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1464 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1465
1466 /* Shadow RAM related */
1467 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1468 #define I40E_SR_BUF_ALIGNMENT 4096
1469 #define I40E_SR_WORDS_IN_1KB 512
1470 /* Checksum should be calculated such that after adding all the words,
1471 * including the checksum word itself, the sum should be 0xBABA.
1472 */
1473 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1474
1475 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1476
1477 enum i40e_switch_element_types {
1478 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1479 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1480 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1481 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1482 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1483 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1484 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1485 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1486 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1487 };
1488
1489 /* Supported EtherType filters */
1490 enum i40e_ether_type_index {
1491 I40E_ETHER_TYPE_1588 = 0,
1492 I40E_ETHER_TYPE_FIP = 1,
1493 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1494 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1495 I40E_ETHER_TYPE_LLDP = 4,
1496 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1497 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1498 I40E_ETHER_TYPE_QCN_CNM = 7,
1499 I40E_ETHER_TYPE_8021X = 8,
1500 I40E_ETHER_TYPE_ARP = 9,
1501 I40E_ETHER_TYPE_RSV1 = 10,
1502 I40E_ETHER_TYPE_RSV2 = 11,
1503 };
1504
1505 /* Filter context base size is 1K */
1506 #define I40E_HASH_FILTER_BASE_SIZE 1024
1507 /* Supported Hash filter values */
1508 enum i40e_hash_filter_size {
1509 I40E_HASH_FILTER_SIZE_1K = 0,
1510 I40E_HASH_FILTER_SIZE_2K = 1,
1511 I40E_HASH_FILTER_SIZE_4K = 2,
1512 I40E_HASH_FILTER_SIZE_8K = 3,
1513 I40E_HASH_FILTER_SIZE_16K = 4,
1514 I40E_HASH_FILTER_SIZE_32K = 5,
1515 I40E_HASH_FILTER_SIZE_64K = 6,
1516 I40E_HASH_FILTER_SIZE_128K = 7,
1517 I40E_HASH_FILTER_SIZE_256K = 8,
1518 I40E_HASH_FILTER_SIZE_512K = 9,
1519 I40E_HASH_FILTER_SIZE_1M = 10,
1520 };
1521
1522 /* DMA context base size is 0.5K */
1523 #define I40E_DMA_CNTX_BASE_SIZE 512
1524 /* Supported DMA context values */
1525 enum i40e_dma_cntx_size {
1526 I40E_DMA_CNTX_SIZE_512 = 0,
1527 I40E_DMA_CNTX_SIZE_1K = 1,
1528 I40E_DMA_CNTX_SIZE_2K = 2,
1529 I40E_DMA_CNTX_SIZE_4K = 3,
1530 I40E_DMA_CNTX_SIZE_8K = 4,
1531 I40E_DMA_CNTX_SIZE_16K = 5,
1532 I40E_DMA_CNTX_SIZE_32K = 6,
1533 I40E_DMA_CNTX_SIZE_64K = 7,
1534 I40E_DMA_CNTX_SIZE_128K = 8,
1535 I40E_DMA_CNTX_SIZE_256K = 9,
1536 };
1537
1538 /* Supported Hash look up table (LUT) sizes */
1539 enum i40e_hash_lut_size {
1540 I40E_HASH_LUT_SIZE_128 = 0,
1541 I40E_HASH_LUT_SIZE_512 = 1,
1542 };
1543
1544 /* Structure to hold a per PF filter control settings */
1545 struct i40e_filter_control_settings {
1546 /* number of PE Quad Hash filter buckets */
1547 enum i40e_hash_filter_size pe_filt_num;
1548 /* number of PE Quad Hash contexts */
1549 enum i40e_dma_cntx_size pe_cntx_num;
1550 /* number of FCoE filter buckets */
1551 enum i40e_hash_filter_size fcoe_filt_num;
1552 /* number of FCoE DDP contexts */
1553 enum i40e_dma_cntx_size fcoe_cntx_num;
1554 /* size of the Hash LUT */
1555 enum i40e_hash_lut_size hash_lut_size;
1556 /* enable FDIR filters for PF and its VFs */
1557 bool enable_fdir;
1558 /* enable Ethertype filters for PF and its VFs */
1559 bool enable_ethtype;
1560 /* enable MAC/VLAN filters for PF and its VFs */
1561 bool enable_macvlan;
1562 };
1563
1564 /* Structure to hold device level control filter counts */
1565 struct i40e_control_filter_stats {
1566 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1567 u16 etype_used; /* Used perfect EtherType filters */
1568 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1569 u16 etype_free; /* Un-used perfect EtherType filters */
1570 };
1571
1572 enum i40e_reset_type {
1573 I40E_RESET_POR = 0,
1574 I40E_RESET_CORER = 1,
1575 I40E_RESET_GLOBR = 2,
1576 I40E_RESET_EMPR = 3,
1577 };
1578
1579 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1580 #define I40E_NVM_LLDP_CFG_PTR 0xD
1581 struct i40e_lldp_variables {
1582 u16 length;
1583 u16 adminstatus;
1584 u16 msgfasttx;
1585 u16 msgtxinterval;
1586 u16 txparams;
1587 u16 timers;
1588 u16 crc8;
1589 };
1590
1591 /* Offsets into Alternate Ram */
1592 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1593 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1594 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1595 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1596 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1597 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1598
1599 /* Alternate Ram Bandwidth Masks */
1600 #define I40E_ALT_BW_VALUE_MASK 0xFF
1601 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1602 #define I40E_ALT_BW_VALID_MASK 0x80000000
1603
1604 /* RSS Hash Table Size */
1605 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1606
1607 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1608 #define I40E_L3_SRC_SHIFT 47
1609 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1610 #define I40E_L3_V6_SRC_SHIFT 43
1611 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1612 #define I40E_L3_DST_SHIFT 35
1613 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1614 #define I40E_L3_V6_DST_SHIFT 35
1615 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1616 #define I40E_L4_SRC_SHIFT 34
1617 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1618 #define I40E_L4_DST_SHIFT 33
1619 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1620 #define I40E_VERIFY_TAG_SHIFT 31
1621 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1622
1623 #define I40E_FLEX_50_SHIFT 13
1624 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1625 #define I40E_FLEX_51_SHIFT 12
1626 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1627 #define I40E_FLEX_52_SHIFT 11
1628 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1629 #define I40E_FLEX_53_SHIFT 10
1630 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1631 #define I40E_FLEX_54_SHIFT 9
1632 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1633 #define I40E_FLEX_55_SHIFT 8
1634 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1635 #define I40E_FLEX_56_SHIFT 7
1636 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1637 #define I40E_FLEX_57_SHIFT 6
1638 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1639 #endif /* _I40E_TYPE_H_ */
Unleashed OS