1 /******************************************************************************
3 Copyright (c) 2013-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #ifndef _I40E_ADMINQ_CMD_H_
36 #define _I40E_ADMINQ_CMD_H_
38 /* This header file defines the i40e Admin Queue commands and is shared between
39 * i40e Firmware and Software.
41 * This file needs to comply with the Linux Kernel coding style.
44 #define I40E_FW_API_VERSION_MAJOR 0x0001
45 #define I40E_FW_API_VERSION_MINOR 0x0005
71 /* Flags sub-structure
72 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
73 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
76 /* command flags and offsets*/
77 #define I40E_AQ_FLAG_DD_SHIFT 0
78 #define I40E_AQ_FLAG_CMP_SHIFT 1
79 #define I40E_AQ_FLAG_ERR_SHIFT 2
80 #define I40E_AQ_FLAG_VFE_SHIFT 3
81 #define I40E_AQ_FLAG_LB_SHIFT 9
82 #define I40E_AQ_FLAG_RD_SHIFT 10
83 #define I40E_AQ_FLAG_VFC_SHIFT 11
84 #define I40E_AQ_FLAG_BUF_SHIFT 12
85 #define I40E_AQ_FLAG_SI_SHIFT 13
86 #define I40E_AQ_FLAG_EI_SHIFT 14
87 #define I40E_AQ_FLAG_FE_SHIFT 15
89 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
90 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
91 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
92 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
93 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
94 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
95 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
96 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
97 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
98 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
99 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
102 enum i40e_admin_queue_err
{
103 I40E_AQ_RC_OK
= 0, /* success */
104 I40E_AQ_RC_EPERM
= 1, /* Operation not permitted */
105 I40E_AQ_RC_ENOENT
= 2, /* No such element */
106 I40E_AQ_RC_ESRCH
= 3, /* Bad opcode */
107 I40E_AQ_RC_EINTR
= 4, /* operation interrupted */
108 I40E_AQ_RC_EIO
= 5, /* I/O error */
109 I40E_AQ_RC_ENXIO
= 6, /* No such resource */
110 I40E_AQ_RC_E2BIG
= 7, /* Arg too long */
111 I40E_AQ_RC_EAGAIN
= 8, /* Try again */
112 I40E_AQ_RC_ENOMEM
= 9, /* Out of memory */
113 I40E_AQ_RC_EACCES
= 10, /* Permission denied */
114 I40E_AQ_RC_EFAULT
= 11, /* Bad address */
115 I40E_AQ_RC_EBUSY
= 12, /* Device or resource busy */
116 I40E_AQ_RC_EEXIST
= 13, /* object already exists */
117 I40E_AQ_RC_EINVAL
= 14, /* Invalid argument */
118 I40E_AQ_RC_ENOTTY
= 15, /* Not a typewriter */
119 I40E_AQ_RC_ENOSPC
= 16, /* No space left or alloc failure */
120 I40E_AQ_RC_ENOSYS
= 17, /* Function not implemented */
121 I40E_AQ_RC_ERANGE
= 18, /* Parameter out of range */
122 I40E_AQ_RC_EFLUSHED
= 19, /* Cmd flushed due to prev cmd error */
123 I40E_AQ_RC_BAD_ADDR
= 20, /* Descriptor contains a bad pointer */
124 I40E_AQ_RC_EMODE
= 21, /* Op not allowed in current dev mode */
125 I40E_AQ_RC_EFBIG
= 22, /* File too large */
128 /* Admin Queue command opcodes */
129 enum i40e_admin_queue_opc
{
131 i40e_aqc_opc_get_version
= 0x0001,
132 i40e_aqc_opc_driver_version
= 0x0002,
133 i40e_aqc_opc_queue_shutdown
= 0x0003,
134 i40e_aqc_opc_set_pf_context
= 0x0004,
136 /* resource ownership */
137 i40e_aqc_opc_request_resource
= 0x0008,
138 i40e_aqc_opc_release_resource
= 0x0009,
140 i40e_aqc_opc_list_func_capabilities
= 0x000A,
141 i40e_aqc_opc_list_dev_capabilities
= 0x000B,
144 i40e_aqc_opc_set_proxy_config
= 0x0104,
145 i40e_aqc_opc_set_ns_proxy_table_entry
= 0x0105,
148 i40e_aqc_opc_mac_address_read
= 0x0107,
149 i40e_aqc_opc_mac_address_write
= 0x0108,
152 i40e_aqc_opc_clear_pxe_mode
= 0x0110,
155 i40e_aqc_opc_set_wol_filter
= 0x0120,
156 i40e_aqc_opc_get_wake_reason
= 0x0121,
158 /* internal switch commands */
159 i40e_aqc_opc_get_switch_config
= 0x0200,
160 i40e_aqc_opc_add_statistics
= 0x0201,
161 i40e_aqc_opc_remove_statistics
= 0x0202,
162 i40e_aqc_opc_set_port_parameters
= 0x0203,
163 i40e_aqc_opc_get_switch_resource_alloc
= 0x0204,
164 i40e_aqc_opc_set_switch_config
= 0x0205,
165 i40e_aqc_opc_rx_ctl_reg_read
= 0x0206,
166 i40e_aqc_opc_rx_ctl_reg_write
= 0x0207,
168 i40e_aqc_opc_add_vsi
= 0x0210,
169 i40e_aqc_opc_update_vsi_parameters
= 0x0211,
170 i40e_aqc_opc_get_vsi_parameters
= 0x0212,
172 i40e_aqc_opc_add_pv
= 0x0220,
173 i40e_aqc_opc_update_pv_parameters
= 0x0221,
174 i40e_aqc_opc_get_pv_parameters
= 0x0222,
176 i40e_aqc_opc_add_veb
= 0x0230,
177 i40e_aqc_opc_update_veb_parameters
= 0x0231,
178 i40e_aqc_opc_get_veb_parameters
= 0x0232,
180 i40e_aqc_opc_delete_element
= 0x0243,
182 i40e_aqc_opc_add_macvlan
= 0x0250,
183 i40e_aqc_opc_remove_macvlan
= 0x0251,
184 i40e_aqc_opc_add_vlan
= 0x0252,
185 i40e_aqc_opc_remove_vlan
= 0x0253,
186 i40e_aqc_opc_set_vsi_promiscuous_modes
= 0x0254,
187 i40e_aqc_opc_add_tag
= 0x0255,
188 i40e_aqc_opc_remove_tag
= 0x0256,
189 i40e_aqc_opc_add_multicast_etag
= 0x0257,
190 i40e_aqc_opc_remove_multicast_etag
= 0x0258,
191 i40e_aqc_opc_update_tag
= 0x0259,
192 i40e_aqc_opc_add_control_packet_filter
= 0x025A,
193 i40e_aqc_opc_remove_control_packet_filter
= 0x025B,
194 i40e_aqc_opc_add_cloud_filters
= 0x025C,
195 i40e_aqc_opc_remove_cloud_filters
= 0x025D,
196 i40e_aqc_opc_clear_wol_switch_filters
= 0x025E,
198 i40e_aqc_opc_add_mirror_rule
= 0x0260,
199 i40e_aqc_opc_delete_mirror_rule
= 0x0261,
202 i40e_aqc_opc_dcb_ignore_pfc
= 0x0301,
203 i40e_aqc_opc_dcb_updated
= 0x0302,
206 i40e_aqc_opc_configure_vsi_bw_limit
= 0x0400,
207 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
= 0x0406,
208 i40e_aqc_opc_configure_vsi_tc_bw
= 0x0407,
209 i40e_aqc_opc_query_vsi_bw_config
= 0x0408,
210 i40e_aqc_opc_query_vsi_ets_sla_config
= 0x040A,
211 i40e_aqc_opc_configure_switching_comp_bw_limit
= 0x0410,
213 i40e_aqc_opc_enable_switching_comp_ets
= 0x0413,
214 i40e_aqc_opc_modify_switching_comp_ets
= 0x0414,
215 i40e_aqc_opc_disable_switching_comp_ets
= 0x0415,
216 i40e_aqc_opc_configure_switching_comp_ets_bw_limit
= 0x0416,
217 i40e_aqc_opc_configure_switching_comp_bw_config
= 0x0417,
218 i40e_aqc_opc_query_switching_comp_ets_config
= 0x0418,
219 i40e_aqc_opc_query_port_ets_config
= 0x0419,
220 i40e_aqc_opc_query_switching_comp_bw_config
= 0x041A,
221 i40e_aqc_opc_suspend_port_tx
= 0x041B,
222 i40e_aqc_opc_resume_port_tx
= 0x041C,
223 i40e_aqc_opc_configure_partition_bw
= 0x041D,
225 i40e_aqc_opc_query_hmc_resource_profile
= 0x0500,
226 i40e_aqc_opc_set_hmc_resource_profile
= 0x0501,
231 i40e_aqc_opc_get_phy_abilities
= 0x0600,
232 i40e_aqc_opc_set_phy_config
= 0x0601,
233 i40e_aqc_opc_set_mac_config
= 0x0603,
234 i40e_aqc_opc_set_link_restart_an
= 0x0605,
235 i40e_aqc_opc_get_link_status
= 0x0607,
236 i40e_aqc_opc_set_phy_int_mask
= 0x0613,
237 i40e_aqc_opc_get_local_advt_reg
= 0x0614,
238 i40e_aqc_opc_set_local_advt_reg
= 0x0615,
239 i40e_aqc_opc_get_partner_advt
= 0x0616,
240 i40e_aqc_opc_set_lb_modes
= 0x0618,
241 i40e_aqc_opc_get_phy_wol_caps
= 0x0621,
242 i40e_aqc_opc_set_phy_debug
= 0x0622,
243 i40e_aqc_opc_upload_ext_phy_fm
= 0x0625,
244 i40e_aqc_opc_run_phy_activity
= 0x0626,
247 i40e_aqc_opc_nvm_read
= 0x0701,
248 i40e_aqc_opc_nvm_erase
= 0x0702,
249 i40e_aqc_opc_nvm_update
= 0x0703,
250 i40e_aqc_opc_nvm_config_read
= 0x0704,
251 i40e_aqc_opc_nvm_config_write
= 0x0705,
252 i40e_aqc_opc_oem_post_update
= 0x0720,
253 i40e_aqc_opc_thermal_sensor
= 0x0721,
255 /* virtualization commands */
256 i40e_aqc_opc_send_msg_to_pf
= 0x0801,
257 i40e_aqc_opc_send_msg_to_vf
= 0x0802,
258 i40e_aqc_opc_send_msg_to_peer
= 0x0803,
260 /* alternate structure */
261 i40e_aqc_opc_alternate_write
= 0x0900,
262 i40e_aqc_opc_alternate_write_indirect
= 0x0901,
263 i40e_aqc_opc_alternate_read
= 0x0902,
264 i40e_aqc_opc_alternate_read_indirect
= 0x0903,
265 i40e_aqc_opc_alternate_write_done
= 0x0904,
266 i40e_aqc_opc_alternate_set_mode
= 0x0905,
267 i40e_aqc_opc_alternate_clear_port
= 0x0906,
270 i40e_aqc_opc_lldp_get_mib
= 0x0A00,
271 i40e_aqc_opc_lldp_update_mib
= 0x0A01,
272 i40e_aqc_opc_lldp_add_tlv
= 0x0A02,
273 i40e_aqc_opc_lldp_update_tlv
= 0x0A03,
274 i40e_aqc_opc_lldp_delete_tlv
= 0x0A04,
275 i40e_aqc_opc_lldp_stop
= 0x0A05,
276 i40e_aqc_opc_lldp_start
= 0x0A06,
277 i40e_aqc_opc_get_cee_dcb_cfg
= 0x0A07,
278 i40e_aqc_opc_lldp_set_local_mib
= 0x0A08,
279 i40e_aqc_opc_lldp_stop_start_spec_agent
= 0x0A09,
281 /* Tunnel commands */
282 i40e_aqc_opc_add_udp_tunnel
= 0x0B00,
283 i40e_aqc_opc_del_udp_tunnel
= 0x0B01,
284 i40e_aqc_opc_set_rss_key
= 0x0B02,
285 i40e_aqc_opc_set_rss_lut
= 0x0B03,
286 i40e_aqc_opc_get_rss_key
= 0x0B04,
287 i40e_aqc_opc_get_rss_lut
= 0x0B05,
290 i40e_aqc_opc_event_lan_overflow
= 0x1001,
293 i40e_aqc_opc_oem_parameter_change
= 0xFE00,
294 i40e_aqc_opc_oem_device_status_change
= 0xFE01,
295 i40e_aqc_opc_oem_ocsd_initialize
= 0xFE02,
296 i40e_aqc_opc_oem_ocbb_initialize
= 0xFE03,
299 i40e_aqc_opc_debug_read_reg
= 0xFF03,
300 i40e_aqc_opc_debug_write_reg
= 0xFF04,
301 i40e_aqc_opc_debug_modify_reg
= 0xFF07,
302 i40e_aqc_opc_debug_dump_internals
= 0xFF08,
305 /* command structures and indirect data structures */
307 /* Structure naming conventions:
308 * - no suffix for direct command descriptor structures
309 * - _data for indirect sent data
310 * - _resp for indirect return data (data which is both will use _data)
311 * - _completion for direct return data
312 * - _element_ for repeated elements (may also be _data or _resp)
314 * Command structures are expected to overlay the params.raw member of the basic
315 * descriptor, and as such cannot exceed 16 bytes in length.
318 /* This macro is used to generate a compilation error if a structure
319 * is not exactly the correct length. It gives a divide by zero error if the
320 * structure is not of the correct size, otherwise it creates an enum that is
323 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
324 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
326 /* This macro is used extensively to ensure that command structures are 16
327 * bytes in length as they have to map to the raw array of that size.
329 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
331 /* internal (0x00XX) commands */
333 /* Get version (direct 0x0001) */
334 struct i40e_aqc_get_version
{
343 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version
);
345 /* Send driver version (indirect 0x0002) */
346 struct i40e_aqc_driver_version
{
350 u8 driver_subbuild_ver
;
356 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version
);
358 /* Queue Shutdown (direct 0x0003) */
359 struct i40e_aqc_queue_shutdown
{
360 __le32 driver_unloading
;
361 #define I40E_AQ_DRIVER_UNLOADING 0x1
365 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown
);
367 /* Set PF context (0x0004, direct) */
368 struct i40e_aqc_set_pf_context
{
373 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context
);
375 /* Request resource ownership (direct 0x0008)
376 * Release resource ownership (direct 0x0009)
378 #define I40E_AQ_RESOURCE_NVM 1
379 #define I40E_AQ_RESOURCE_SDP 2
380 #define I40E_AQ_RESOURCE_ACCESS_READ 1
381 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
382 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
383 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
385 struct i40e_aqc_request_resource
{
389 __le32 resource_number
;
393 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource
);
395 /* Get function capabilities (indirect 0x000A)
396 * Get device capabilities (indirect 0x000B)
398 struct i40e_aqc_list_capabilites
{
400 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
408 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites
);
410 struct i40e_aqc_list_capabilities_element_resp
{
422 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
423 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
424 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
425 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
426 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
427 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
428 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
429 #define I40E_AQ_CAP_ID_SRIOV 0x0012
430 #define I40E_AQ_CAP_ID_VF 0x0013
431 #define I40E_AQ_CAP_ID_VMDQ 0x0014
432 #define I40E_AQ_CAP_ID_8021QBG 0x0015
433 #define I40E_AQ_CAP_ID_8021QBR 0x0016
434 #define I40E_AQ_CAP_ID_VSI 0x0017
435 #define I40E_AQ_CAP_ID_DCB 0x0018
436 #define I40E_AQ_CAP_ID_FCOE 0x0021
437 #define I40E_AQ_CAP_ID_ISCSI 0x0022
438 #define I40E_AQ_CAP_ID_RSS 0x0040
439 #define I40E_AQ_CAP_ID_RXQ 0x0041
440 #define I40E_AQ_CAP_ID_TXQ 0x0042
441 #define I40E_AQ_CAP_ID_MSIX 0x0043
442 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
443 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
444 #define I40E_AQ_CAP_ID_1588 0x0046
445 #define I40E_AQ_CAP_ID_IWARP 0x0051
446 #define I40E_AQ_CAP_ID_LED 0x0061
447 #define I40E_AQ_CAP_ID_SDP 0x0062
448 #define I40E_AQ_CAP_ID_MDIO 0x0063
449 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
450 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
451 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
452 #define I40E_AQ_CAP_ID_CEM 0x00F2
454 /* Set CPPM Configuration (direct 0x0103) */
455 struct i40e_aqc_cppm_configuration
{
456 __le16 command_flags
;
457 #define I40E_AQ_CPPM_EN_LTRC 0x0800
458 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
459 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
460 #define I40E_AQ_CPPM_EN_HPTC 0x4000
461 #define I40E_AQ_CPPM_EN_DMARC 0x8000
470 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration
);
472 /* Set ARP Proxy command / response (indirect 0x0104) */
473 struct i40e_aqc_arp_proxy_data
{
474 __le16 command_flags
;
475 #define I40E_AQ_ARP_INIT_IPV4 0x0800
476 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
477 #define I40E_AQ_ARP_ENA 0x2000
478 #define I40E_AQ_ARP_ADD_IPV4 0x4000
479 #define I40E_AQ_ARP_DEL_IPV4 0x8000
481 __le32 enabled_offloads
;
482 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
483 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
489 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data
);
491 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
492 struct i40e_aqc_ns_proxy_data
{
493 __le16 table_idx_mac_addr_0
;
494 __le16 table_idx_mac_addr_1
;
495 __le16 table_idx_ipv6_0
;
496 __le16 table_idx_ipv6_1
;
498 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
499 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
500 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
501 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
502 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
503 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
504 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
505 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
506 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
507 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
508 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
509 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
510 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
513 u8 local_mac_addr
[6];
514 u8 ipv6_addr_0
[16]; /* Warning! spec specifies BE byte order */
518 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data
);
520 /* Manage LAA Command (0x0106) - obsolete */
521 struct i40e_aqc_mng_laa
{
522 __le16 command_flags
;
523 #define I40E_AQ_LAA_FLAG_WR 0x8000
530 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa
);
532 /* Manage MAC Address Read Command (indirect 0x0107) */
533 struct i40e_aqc_mac_address_read
{
534 __le16 command_flags
;
535 #define I40E_AQC_LAN_ADDR_VALID 0x10
536 #define I40E_AQC_SAN_ADDR_VALID 0x20
537 #define I40E_AQC_PORT_ADDR_VALID 0x40
538 #define I40E_AQC_WOL_ADDR_VALID 0x80
539 #define I40E_AQC_MC_MAG_EN_VALID 0x100
540 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
541 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
547 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read
);
549 struct i40e_aqc_mac_address_read_data
{
556 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data
);
558 /* Manage MAC Address Write Command (0x0108) */
559 struct i40e_aqc_mac_address_write
{
560 __le16 command_flags
;
561 #define I40E_AQC_MC_MAG_EN 0x0100
562 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
563 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
564 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
565 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
566 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
567 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
574 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write
);
576 /* PXE commands (0x011x) */
578 /* Clear PXE Command and response (direct 0x0110) */
579 struct i40e_aqc_clear_pxe
{
584 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe
);
586 /* Set WoL Filter (0x0120) */
588 struct i40e_aqc_set_wol_filter
{
590 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
591 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
592 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
593 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
595 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
596 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
597 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
599 #define I40E_AQC_SET_WOL_FILTER 0x8000
600 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
601 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
602 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
603 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
605 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
606 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
612 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter
);
614 struct i40e_aqc_set_wol_filter_data
{
619 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data
);
621 /* Get Wake Reason (0x0121) */
623 struct i40e_aqc_get_wake_reason_completion
{
626 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
627 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
628 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
629 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
630 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
631 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
635 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion
);
637 /* Switch configuration commands (0x02xx) */
639 /* Used by many indirect commands that only pass an seid and a buffer in the
642 struct i40e_aqc_switch_seid
{
649 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid
);
651 /* Get Switch Configuration command (indirect 0x0200)
652 * uses i40e_aqc_switch_seid for the descriptor
654 struct i40e_aqc_get_switch_config_header_resp
{
660 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp
);
662 struct i40e_aqc_switch_config_element_resp
{
664 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
665 #define I40E_AQ_SW_ELEM_TYPE_PF 2
666 #define I40E_AQ_SW_ELEM_TYPE_VF 3
667 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
668 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
669 #define I40E_AQ_SW_ELEM_TYPE_PV 16
670 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
671 #define I40E_AQ_SW_ELEM_TYPE_PA 18
672 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
674 #define I40E_AQ_SW_ELEM_REV_1 1
677 __le16 downlink_seid
;
680 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
681 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
682 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
687 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp
);
689 /* Get Switch Configuration (indirect 0x0200)
690 * an array of elements are returned in the response buffer
691 * the first in the array is the header, remainder are elements
693 struct i40e_aqc_get_switch_config_resp
{
694 struct i40e_aqc_get_switch_config_header_resp header
;
695 struct i40e_aqc_switch_config_element_resp element
[1];
698 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp
);
700 /* Add Statistics (direct 0x0201)
701 * Remove Statistics (direct 0x0202)
703 struct i40e_aqc_add_remove_statistics
{
710 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics
);
712 /* Set Port Parameters command (direct 0x0203) */
713 struct i40e_aqc_set_port_parameters
{
714 __le16 command_flags
;
715 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
716 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
717 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
718 __le16 bad_frame_vsi
;
719 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
720 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
721 __le16 default_seid
; /* reserved for command */
725 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters
);
727 /* Get Switch Resource Allocation (indirect 0x0204) */
728 struct i40e_aqc_get_switch_resource_alloc
{
729 u8 num_entries
; /* reserved for command */
735 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc
);
737 /* expect an array of these structs in the response buffer */
738 struct i40e_aqc_switch_resource_alloc_element_resp
{
740 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
741 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
742 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
743 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
744 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
745 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
746 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
747 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
748 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
749 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
750 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
751 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
752 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
753 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
754 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
755 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
756 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
757 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
758 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
763 __le16 total_unalloced
;
767 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp
);
769 /* Set Switch Configuration (direct 0x0205) */
770 struct i40e_aqc_set_switch_config
{
772 /* flags used for both fields below */
773 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
774 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
779 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config
);
781 /* Read Receive control registers (direct 0x0206)
782 * Write Receive control registers (direct 0x0207)
783 * used for accessing Rx control registers that can be
784 * slow and need special handling when under high Rx load
786 struct i40e_aqc_rx_ctl_reg_read_write
{
793 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write
);
795 /* Add VSI (indirect 0x0210)
796 * this indirect command uses struct i40e_aqc_vsi_properties_data
797 * as the indirect buffer (128 bytes)
799 * Update VSI (indirect 0x211)
800 * uses the same data structure as Add VSI
802 * Get VSI (indirect 0x0212)
803 * uses the same completion and data structure as Add VSI
805 struct i40e_aqc_add_get_update_vsi
{
808 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
809 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
810 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
815 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
816 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
817 #define I40E_AQ_VSI_TYPE_VF 0x0
818 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
819 #define I40E_AQ_VSI_TYPE_PF 0x2
820 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
821 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
826 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi
);
828 struct i40e_aqc_add_get_update_vsi_completion
{
837 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion
);
839 struct i40e_aqc_vsi_properties_data
{
840 /* first 96 byte are written by SW */
841 __le16 valid_sections
;
842 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
843 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
844 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
845 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
846 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
847 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
848 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
849 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
850 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
851 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
853 __le16 switch_id
; /* 12bit id combined with flags below */
854 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
855 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
856 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
857 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
858 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
860 /* security section */
862 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
863 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
864 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
867 __le16 pvid
; /* VLANS include priority bits */
870 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
871 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
872 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
873 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
874 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
875 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
876 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
877 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
878 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
879 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
880 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
881 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
882 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
883 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
884 u8 pvlan_reserved
[3];
885 /* ingress egress up sections */
886 __le32 ingress_table
; /* bitmap, 3 bits per up */
887 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
888 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
889 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
890 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
891 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
892 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
893 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
894 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
895 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
896 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
897 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
898 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
899 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
900 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
901 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
902 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
903 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
904 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
905 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
906 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
907 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
908 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
909 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
910 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
911 __le32 egress_table
; /* same defines as for ingress table */
912 /* cascaded PV section */
915 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
916 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
917 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
918 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
919 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
920 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
921 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
922 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
923 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
925 /* queue mapping section */
926 __le16 mapping_flags
;
927 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
928 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
929 __le16 queue_mapping
[16];
930 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
931 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
932 __le16 tc_mapping
[8];
933 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
934 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
935 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
936 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
937 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
938 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
939 /* queueing option section */
940 u8 queueing_opt_flags
;
941 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
942 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
943 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
944 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
945 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
946 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
947 u8 queueing_opt_reserved
[3];
948 /* scheduler section */
951 /* outer up section */
952 __le32 outer_up_table
; /* same structure and defines as ingress tbl */
954 /* last 32 bytes are written by FW */
956 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
957 __le16 stat_counter_idx
;
959 u8 resp_reserved
[12];
962 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data
);
964 /* Add Port Virtualizer (direct 0x0220)
965 * also used for update PV (direct 0x0221) but only flags are used
966 * (IS_CTRL_PORT only works on add PV)
968 struct i40e_aqc_add_update_pv
{
969 __le16 command_flags
;
970 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
971 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
972 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
973 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
975 __le16 connected_seid
;
979 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv
);
981 struct i40e_aqc_add_update_pv_completion
{
982 /* reserved for update; for add also encodes error if rc == ENOSPC */
984 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
985 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
986 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
987 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
991 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion
);
993 /* Get PV Params (direct 0x0222)
994 * uses i40e_aqc_switch_seid for the descriptor
997 struct i40e_aqc_get_pv_params_completion
{
1000 __le16 pv_flags
; /* same flags as add_pv */
1001 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1002 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1003 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1005 __le16 default_port_seid
;
1008 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion
);
1010 /* Add VEB (direct 0x0230) */
1011 struct i40e_aqc_add_veb
{
1013 __le16 downlink_seid
;
1015 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1016 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1017 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1018 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1019 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1020 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1021 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1022 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1027 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb
);
1029 struct i40e_aqc_add_veb_completion
{
1032 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1034 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1035 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1036 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1037 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1038 __le16 statistic_index
;
1043 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion
);
1045 /* Get VEB Parameters (direct 0x0232)
1046 * uses i40e_aqc_switch_seid for the descriptor
1048 struct i40e_aqc_get_veb_parameters_completion
{
1051 __le16 veb_flags
; /* only the first/last flags from 0x0230 is valid */
1052 __le16 statistic_index
;
1058 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion
);
1060 /* Delete Element (direct 0x0243)
1061 * uses the generic i40e_aqc_switch_seid
1064 /* Add MAC-VLAN (indirect 0x0250) */
1066 /* used for the command for most vlan commands */
1067 struct i40e_aqc_macvlan
{
1068 __le16 num_addresses
;
1070 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1071 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1072 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1073 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1078 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan
);
1080 /* indirect data for command and response */
1081 struct i40e_aqc_add_macvlan_element_data
{
1085 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1086 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1087 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1088 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1089 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1090 __le16 queue_number
;
1091 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1092 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1093 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1094 /* response section */
1096 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1097 #define I40E_AQC_MM_HASH_MATCH 0x02
1098 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1102 struct i40e_aqc_add_remove_macvlan_completion
{
1103 __le16 perfect_mac_used
;
1104 __le16 perfect_mac_free
;
1105 __le16 unicast_hash_free
;
1106 __le16 multicast_hash_free
;
1111 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion
);
1113 /* Remove MAC-VLAN (indirect 0x0251)
1114 * uses i40e_aqc_macvlan for the descriptor
1115 * data points to an array of num_addresses of elements
1118 struct i40e_aqc_remove_macvlan_element_data
{
1122 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1123 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1124 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1125 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1129 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1130 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1131 u8 reply_reserved
[3];
1134 /* Add VLAN (indirect 0x0252)
1135 * Remove VLAN (indirect 0x0253)
1136 * use the generic i40e_aqc_macvlan for the command
1138 struct i40e_aqc_add_remove_vlan_element_data
{
1141 /* flags for add VLAN */
1142 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1143 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1144 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1145 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1146 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1147 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1148 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1149 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1150 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1151 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1152 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1153 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1154 /* flags for remove VLAN */
1155 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1158 /* flags for add VLAN */
1159 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1160 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1161 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1162 /* flags for remove VLAN */
1163 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1164 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1168 struct i40e_aqc_add_remove_vlan_completion
{
1176 /* Set VSI Promiscuous Modes (direct 0x0254) */
1177 struct i40e_aqc_set_vsi_promiscuous_modes
{
1178 __le16 promiscuous_flags
;
1180 /* flags used for both fields above */
1181 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1182 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1183 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1184 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1185 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1186 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1188 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1190 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1191 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1195 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes
);
1197 /* Add S/E-tag command (direct 0x0255)
1198 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1200 struct i40e_aqc_add_tag
{
1202 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1204 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1205 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1206 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1208 __le16 queue_number
;
1212 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag
);
1214 struct i40e_aqc_add_remove_tag_completion
{
1220 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion
);
1222 /* Remove S/E-tag command (direct 0x0256)
1223 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1225 struct i40e_aqc_remove_tag
{
1227 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1228 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1229 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1234 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag
);
1236 /* Add multicast E-Tag (direct 0x0257)
1237 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1238 * and no external data
1240 struct i40e_aqc_add_remove_mcast_etag
{
1243 u8 num_unicast_etags
;
1245 __le32 addr_high
; /* address of array of 2-byte s-tags */
1249 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag
);
1251 struct i40e_aqc_add_remove_mcast_etag_completion
{
1253 __le16 mcast_etags_used
;
1254 __le16 mcast_etags_free
;
1260 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion
);
1262 /* Update S/E-Tag (direct 0x0259) */
1263 struct i40e_aqc_update_tag
{
1265 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1266 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1267 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1273 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag
);
1275 struct i40e_aqc_update_tag_completion
{
1281 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion
);
1283 /* Add Control Packet filter (direct 0x025A)
1284 * Remove Control Packet filter (direct 0x025B)
1285 * uses the i40e_aqc_add_oveb_cloud,
1286 * and the generic direct completion structure
1288 struct i40e_aqc_add_remove_control_packet_filter
{
1292 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1293 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1294 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1295 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1296 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1298 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1299 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1300 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1305 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter
);
1307 struct i40e_aqc_add_remove_control_packet_filter_completion
{
1308 __le16 mac_etype_used
;
1310 __le16 mac_etype_free
;
1315 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion
);
1317 /* Add Cloud filters (indirect 0x025C)
1318 * Remove Cloud filters (indirect 0x025D)
1319 * uses the i40e_aqc_add_remove_cloud_filters,
1320 * and the generic indirect completion structure
1322 struct i40e_aqc_add_remove_cloud_filters
{
1326 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1327 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1328 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1334 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters
);
1336 struct i40e_aqc_add_remove_cloud_filters_element_data
{
1350 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1351 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1352 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1353 /* 0x0000 reserved */
1354 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1355 /* 0x0002 reserved */
1356 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1357 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1358 /* 0x0005 reserved */
1359 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1360 /* 0x0007 reserved */
1361 /* 0x0008 reserved */
1362 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1363 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1364 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1365 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1367 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1368 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1369 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1370 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1371 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1373 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1374 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1375 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1376 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1377 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1378 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1379 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1380 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1382 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1383 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1384 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1388 __le16 queue_number
;
1389 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1390 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1391 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1393 /* response section */
1394 u8 allocation_result
;
1395 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1396 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1397 u8 response_reserved
[7];
1400 struct i40e_aqc_remove_cloud_filters_completion
{
1401 __le16 perfect_ovlan_used
;
1402 __le16 perfect_ovlan_free
;
1409 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion
);
1411 /* Add Mirror Rule (indirect or direct 0x0260)
1412 * Delete Mirror Rule (indirect or direct 0x0261)
1413 * note: some rule types (4,5) do not use an external buffer.
1414 * take care to set the flags correctly.
1416 struct i40e_aqc_add_delete_mirror_rule
{
1419 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1420 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1421 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1422 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1423 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1424 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1425 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1426 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1428 __le16 destination
; /* VSI for add, rule id for delete */
1429 __le32 addr_high
; /* address of array of 2-byte VSI or VLAN ids */
1433 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule
);
1435 struct i40e_aqc_add_delete_mirror_rule_completion
{
1437 __le16 rule_id
; /* only used on add */
1438 __le16 mirror_rules_used
;
1439 __le16 mirror_rules_free
;
1444 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion
);
1448 /* PFC Ignore (direct 0x0301)
1449 * the command and response use the same descriptor structure
1451 struct i40e_aqc_pfc_ignore
{
1453 u8 command_flags
; /* unused on response */
1454 #define I40E_AQC_PFC_IGNORE_SET 0x80
1455 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1459 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore
);
1461 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1462 * with no parameters
1465 /* TX scheduler 0x04xx */
1467 /* Almost all the indirect commands use
1468 * this generic struct to pass the SEID in param0
1470 struct i40e_aqc_tx_sched_ind
{
1477 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind
);
1479 /* Several commands respond with a set of queue set handles */
1480 struct i40e_aqc_qs_handles_resp
{
1481 __le16 qs_handles
[8];
1484 /* Configure VSI BW limits (direct 0x0400) */
1485 struct i40e_aqc_configure_vsi_bw_limit
{
1490 u8 max_credit
; /* 0-3, limit = 2^max */
1494 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit
);
1496 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1497 * responds with i40e_aqc_qs_handles_resp
1499 struct i40e_aqc_configure_vsi_ets_sla_bw_data
{
1502 __le16 tc_bw_credits
[8]; /* FW writesback QS handles here */
1504 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1505 __le16 tc_bw_max
[2];
1509 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data
);
1511 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1512 * responds with i40e_aqc_qs_handles_resp
1514 struct i40e_aqc_configure_vsi_tc_bw_data
{
1517 u8 tc_bw_credits
[8];
1519 __le16 qs_handles
[8];
1522 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data
);
1524 /* Query vsi bw configuration (indirect 0x0408) */
1525 struct i40e_aqc_query_vsi_bw_config_resp
{
1527 u8 tc_suspended_bits
;
1529 __le16 qs_handles
[8];
1531 __le16 port_bw_limit
;
1533 u8 max_bw
; /* 0-3, limit = 2^max */
1537 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp
);
1539 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1540 struct i40e_aqc_query_vsi_ets_sla_config_resp
{
1543 u8 share_credits
[8];
1546 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1547 __le16 tc_bw_max
[2];
1550 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp
);
1552 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1553 struct i40e_aqc_configure_switching_comp_bw_limit
{
1558 u8 max_bw
; /* 0-3, limit = 2^max */
1562 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit
);
1564 /* Enable Physical Port ETS (indirect 0x0413)
1565 * Modify Physical Port ETS (indirect 0x0414)
1566 * Disable Physical Port ETS (indirect 0x0415)
1568 struct i40e_aqc_configure_switching_comp_ets_data
{
1572 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1573 u8 tc_strict_priority_flags
;
1575 u8 tc_bw_share_credits
[8];
1579 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data
);
1581 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1582 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data
{
1585 __le16 tc_bw_credit
[8];
1587 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1588 __le16 tc_bw_max
[2];
1592 I40E_CHECK_STRUCT_LEN(0x40,
1593 i40e_aqc_configure_switching_comp_ets_bw_limit_data
);
1595 /* Configure Switching Component Bandwidth Allocation per Tc
1598 struct i40e_aqc_configure_switching_comp_bw_config_data
{
1601 u8 absolute_credits
; /* bool */
1602 u8 tc_bw_share_credits
[8];
1606 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data
);
1608 /* Query Switching Component Configuration (indirect 0x0418) */
1609 struct i40e_aqc_query_switching_comp_ets_config_resp
{
1612 __le16 port_bw_limit
;
1614 u8 tc_bw_max
; /* 0-3, limit = 2^max */
1618 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp
);
1620 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1621 struct i40e_aqc_query_port_ets_config_resp
{
1625 u8 tc_strict_priority_bits
;
1627 u8 tc_bw_share_credits
[8];
1628 __le16 tc_bw_limits
[8];
1630 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1631 __le16 tc_bw_max
[2];
1635 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp
);
1637 /* Query Switching Component Bandwidth Allocation per Traffic Type
1640 struct i40e_aqc_query_switching_comp_bw_config_resp
{
1643 u8 absolute_credits_enable
; /* bool */
1644 u8 tc_bw_share_credits
[8];
1645 __le16 tc_bw_limits
[8];
1647 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1648 __le16 tc_bw_max
[2];
1651 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp
);
1653 /* Suspend/resume port TX traffic
1654 * (direct 0x041B and 0x041C) uses the generic SEID struct
1657 /* Configure partition BW
1660 struct i40e_aqc_configure_partition_bw_data
{
1661 __le16 pf_valid_bits
;
1662 u8 min_bw
[16]; /* guaranteed bandwidth */
1663 u8 max_bw
[16]; /* bandwidth limit */
1666 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data
);
1668 /* Get and set the active HMC resource profile and status.
1669 * (direct 0x0500) and (direct 0x0501)
1671 struct i40e_aq_get_set_hmc_resource_profile
{
1677 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile
);
1679 enum i40e_aq_hmc_profile
{
1680 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1681 I40E_HMC_PROFILE_DEFAULT
= 1,
1682 I40E_HMC_PROFILE_FAVOR_VF
= 2,
1683 I40E_HMC_PROFILE_EQUAL
= 3,
1686 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1688 /* set in param0 for get phy abilities to report qualified modules */
1689 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1690 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1692 enum i40e_aq_phy_type
{
1693 I40E_PHY_TYPE_SGMII
= 0x0,
1694 I40E_PHY_TYPE_1000BASE_KX
= 0x1,
1695 I40E_PHY_TYPE_10GBASE_KX4
= 0x2,
1696 I40E_PHY_TYPE_10GBASE_KR
= 0x3,
1697 I40E_PHY_TYPE_40GBASE_KR4
= 0x4,
1698 I40E_PHY_TYPE_XAUI
= 0x5,
1699 I40E_PHY_TYPE_XFI
= 0x6,
1700 I40E_PHY_TYPE_SFI
= 0x7,
1701 I40E_PHY_TYPE_XLAUI
= 0x8,
1702 I40E_PHY_TYPE_XLPPI
= 0x9,
1703 I40E_PHY_TYPE_40GBASE_CR4_CU
= 0xA,
1704 I40E_PHY_TYPE_10GBASE_CR1_CU
= 0xB,
1705 I40E_PHY_TYPE_10GBASE_AOC
= 0xC,
1706 I40E_PHY_TYPE_40GBASE_AOC
= 0xD,
1707 I40E_PHY_TYPE_100BASE_TX
= 0x11,
1708 I40E_PHY_TYPE_1000BASE_T
= 0x12,
1709 I40E_PHY_TYPE_10GBASE_T
= 0x13,
1710 I40E_PHY_TYPE_10GBASE_SR
= 0x14,
1711 I40E_PHY_TYPE_10GBASE_LR
= 0x15,
1712 I40E_PHY_TYPE_10GBASE_SFPP_CU
= 0x16,
1713 I40E_PHY_TYPE_10GBASE_CR1
= 0x17,
1714 I40E_PHY_TYPE_40GBASE_CR4
= 0x18,
1715 I40E_PHY_TYPE_40GBASE_SR4
= 0x19,
1716 I40E_PHY_TYPE_40GBASE_LR4
= 0x1A,
1717 I40E_PHY_TYPE_1000BASE_SX
= 0x1B,
1718 I40E_PHY_TYPE_1000BASE_LX
= 0x1C,
1719 I40E_PHY_TYPE_1000BASE_T_OPTICAL
= 0x1D,
1720 I40E_PHY_TYPE_20GBASE_KR2
= 0x1E,
1721 I40E_PHY_TYPE_25GBASE_KR
= 0x1F,
1722 I40E_PHY_TYPE_25GBASE_CR
= 0x20,
1723 I40E_PHY_TYPE_25GBASE_SR
= 0x21,
1724 I40E_PHY_TYPE_25GBASE_LR
= 0x22,
1728 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1729 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1730 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1731 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1732 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1733 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
1735 enum i40e_aq_link_speed
{
1736 I40E_LINK_SPEED_UNKNOWN
= 0,
1737 I40E_LINK_SPEED_100MB
= (1 << I40E_LINK_SPEED_100MB_SHIFT
),
1738 I40E_LINK_SPEED_1GB
= (1 << I40E_LINK_SPEED_1000MB_SHIFT
),
1739 I40E_LINK_SPEED_10GB
= (1 << I40E_LINK_SPEED_10GB_SHIFT
),
1740 I40E_LINK_SPEED_40GB
= (1 << I40E_LINK_SPEED_40GB_SHIFT
),
1741 I40E_LINK_SPEED_20GB
= (1 << I40E_LINK_SPEED_20GB_SHIFT
),
1742 I40E_LINK_SPEED_25GB
= (1 << I40E_LINK_SPEED_25GB_SHIFT
),
1745 struct i40e_aqc_module_desc
{
1753 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc
);
1755 struct i40e_aq_get_phy_abilities_resp
{
1756 __le32 phy_type
; /* bitmap using the above enum for offsets */
1757 u8 link_speed
; /* bitmap using the above enum bit patterns */
1759 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1760 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1761 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1762 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1763 #define I40E_AQ_PHY_AN_ENABLED 0x10
1764 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1765 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1766 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1767 __le16 eee_capability
;
1768 #define I40E_AQ_EEE_100BASE_TX 0x0002
1769 #define I40E_AQ_EEE_1000BASE_T 0x0004
1770 #define I40E_AQ_EEE_10GBASE_T 0x0008
1771 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1772 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1773 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1776 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1778 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
1779 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
1780 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1781 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1786 u8 qualified_module_count
;
1787 #define I40E_AQ_PHY_MAX_QMS 16
1788 struct i40e_aqc_module_desc qualified_module
[I40E_AQ_PHY_MAX_QMS
];
1791 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp
);
1793 /* Set PHY Config (direct 0x0601) */
1794 struct i40e_aq_set_phy_config
{ /* same bits as above in all */
1798 /* bits 0-2 use the values from get_phy_abilities_resp */
1799 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1800 #define I40E_AQ_PHY_ENABLE_AN 0x10
1801 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1802 __le16 eee_capability
;
1807 #define I40E_AQ_SET_FEC_ABILITY_KR (1 << 0)
1808 #define I40E_AQ_SET_FEC_ABILITY_RS (1 << 1)
1809 #define I40E_AQ_SET_FEC_REQUEST_KR (1 << 2)
1810 #define I40E_AQ_SET_FEC_REQUEST_RS (1 << 3)
1811 #define I40E_AQ_SET_FEC_AUTO (1 << 4)
1815 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config
);
1817 /* Set MAC Config command data structure (direct 0x0603) */
1818 struct i40e_aq_set_mac_config
{
1819 __le16 max_frame_size
;
1821 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1822 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1823 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1824 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1825 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1826 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1827 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1828 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1829 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1830 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1831 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1832 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1833 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1834 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1835 u8 tx_timer_priority
; /* bitmap */
1836 __le16 tx_timer_value
;
1837 __le16 fc_refresh_threshold
;
1841 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config
);
1843 /* Restart Auto-Negotiation (direct 0x605) */
1844 struct i40e_aqc_set_link_restart_an
{
1846 #define I40E_AQ_PHY_RESTART_AN 0x02
1847 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1851 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an
);
1853 /* Get Link Status cmd & response data structure (direct 0x0607) */
1854 struct i40e_aqc_get_link_status
{
1855 __le16 command_flags
; /* only field set on command */
1856 #define I40E_AQ_LSE_MASK 0x3
1857 #define I40E_AQ_LSE_NOP 0x0
1858 #define I40E_AQ_LSE_DISABLE 0x2
1859 #define I40E_AQ_LSE_ENABLE 0x3
1860 /* only response uses this flag */
1861 #define I40E_AQ_LSE_IS_ENABLED 0x1
1862 u8 phy_type
; /* i40e_aq_phy_type */
1863 u8 link_speed
; /* i40e_aq_link_speed */
1865 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1866 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1867 #define I40E_AQ_LINK_FAULT 0x02
1868 #define I40E_AQ_LINK_FAULT_TX 0x04
1869 #define I40E_AQ_LINK_FAULT_RX 0x08
1870 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1871 #define I40E_AQ_LINK_UP_PORT 0x20
1872 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1873 #define I40E_AQ_SIGNAL_DETECT 0x80
1875 #define I40E_AQ_AN_COMPLETED 0x01
1876 #define I40E_AQ_LP_AN_ABILITY 0x02
1877 #define I40E_AQ_PD_FAULT 0x04
1878 #define I40E_AQ_FEC_EN 0x08
1879 #define I40E_AQ_PHY_LOW_POWER 0x10
1880 #define I40E_AQ_LINK_PAUSE_TX 0x20
1881 #define I40E_AQ_LINK_PAUSE_RX 0x40
1882 #define I40E_AQ_QUALIFIED_MODULE 0x80
1884 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1885 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1886 #define I40E_AQ_LINK_TX_SHIFT 0x02
1887 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1888 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1889 #define I40E_AQ_LINK_TX_DRAINED 0x01
1890 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1891 #define I40E_AQ_LINK_FORCED_40G 0x10
1892 /* 25G Error Codes */
1893 #define I40E_AQ_25G_NO_ERR 0X00
1894 #define I40E_AQ_25G_NOT_PRESENT 0X01
1895 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
1896 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
1897 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
1898 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
1899 u8 loopback
; /* use defines from i40e_aqc_set_lb_mode */
1900 __le16 max_frame_size
;
1902 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
1903 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
1904 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1905 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1907 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1908 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1909 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1910 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1911 #define I40E_AQ_PWR_CLASS_MASK 0x03
1915 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status
);
1917 /* Set event mask command (direct 0x613) */
1918 struct i40e_aqc_set_phy_int_mask
{
1921 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1922 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1923 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1924 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1925 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1926 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1927 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1928 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1929 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1933 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask
);
1935 /* Get Local AN advt register (direct 0x0614)
1936 * Set Local AN advt register (direct 0x0615)
1937 * Get Link Partner AN advt register (direct 0x0616)
1939 struct i40e_aqc_an_advt_reg
{
1940 __le32 local_an_reg0
;
1941 __le16 local_an_reg1
;
1945 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg
);
1947 /* Set Loopback mode (0x0618) */
1948 struct i40e_aqc_set_lb_mode
{
1950 #define I40E_AQ_LB_PHY_LOCAL 0x01
1951 #define I40E_AQ_LB_PHY_REMOTE 0x02
1952 #define I40E_AQ_LB_MAC_LOCAL 0x04
1956 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode
);
1958 /* Set PHY Debug command (0x0622) */
1959 struct i40e_aqc_set_phy_debug
{
1961 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1962 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1963 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1964 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1965 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1966 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1967 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1968 /* Disable link manageability on a single port */
1969 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1970 /* Disable link manageability on all ports needs both bits 4 and 5 */
1971 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
1975 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug
);
1977 enum i40e_aq_phy_reg_type
{
1978 I40E_AQC_PHY_REG_INTERNAL
= 0x1,
1979 I40E_AQC_PHY_REG_EXERNAL_BASET
= 0x2,
1980 I40E_AQC_PHY_REG_EXERNAL_MODULE
= 0x3
1983 /* Run PHY Activity (0x0626) */
1984 struct i40e_aqc_run_phy_activity
{
1993 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity
);
1995 /* NVM Read command (indirect 0x0701)
1996 * NVM Erase commands (direct 0x0702)
1997 * NVM Update commands (indirect 0x0703)
1999 struct i40e_aqc_nvm_update
{
2001 #define I40E_AQ_NVM_LAST_CMD 0x01
2002 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2010 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update
);
2012 /* NVM Config Read (indirect 0x0704) */
2013 struct i40e_aqc_nvm_config_read
{
2015 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2016 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2017 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2018 __le16 element_count
;
2019 __le16 element_id
; /* Feature/field ID */
2020 __le16 element_id_msw
; /* MSWord of field ID */
2021 __le32 address_high
;
2025 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read
);
2027 /* NVM Config Write (indirect 0x0705) */
2028 struct i40e_aqc_nvm_config_write
{
2030 __le16 element_count
;
2032 __le32 address_high
;
2036 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write
);
2038 /* Used for 0x0704 as well as for 0x0705 commands */
2039 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2040 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2041 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2042 #define I40E_AQ_ANVM_FEATURE 0
2043 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2044 struct i40e_aqc_nvm_config_data_feature
{
2046 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2047 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2048 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2049 __le16 feature_options
;
2050 __le16 feature_selection
;
2053 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature
);
2055 struct i40e_aqc_nvm_config_data_immediate_field
{
2058 __le16 field_options
;
2062 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field
);
2064 /* OEM Post Update (indirect 0x0720)
2065 * no command data struct used
2067 struct i40e_aqc_nvm_oem_post_update
{
2068 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2073 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update
);
2075 struct i40e_aqc_nvm_oem_post_update_buffer
{
2082 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer
);
2084 /* Thermal Sensor (indirect 0x0721)
2085 * read or set thermal sensor configs and values
2086 * takes a sensor and command specific data buffer, not detailed here
2088 struct i40e_aqc_thermal_sensor
{
2090 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2091 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2092 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2098 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor
);
2100 /* Send to PF command (indirect 0x0801) id is only used by PF
2101 * Send to VF command (indirect 0x0802) id is only used by PF
2102 * Send to Peer PF command (indirect 0x0803)
2104 struct i40e_aqc_pf_vf_message
{
2111 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message
);
2113 /* Alternate structure */
2115 /* Direct write (direct 0x0900)
2116 * Direct read (direct 0x0902)
2118 struct i40e_aqc_alternate_write
{
2125 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write
);
2127 /* Indirect write (indirect 0x0901)
2128 * Indirect read (indirect 0x0903)
2131 struct i40e_aqc_alternate_ind_write
{
2138 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write
);
2140 /* Done alternate write (direct 0x0904)
2143 struct i40e_aqc_alternate_write_done
{
2145 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2146 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2147 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2148 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2152 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done
);
2154 /* Set OEM mode (direct 0x0905) */
2155 struct i40e_aqc_alternate_set_mode
{
2157 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2158 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2162 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode
);
2164 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2166 /* async events 0x10xx */
2168 /* Lan Queue Overflow Event (direct, 0x1001) */
2169 struct i40e_aqc_lan_overflow
{
2170 __le32 prtdcb_rupto
;
2175 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow
);
2177 /* Get LLDP MIB (indirect 0x0A00) */
2178 struct i40e_aqc_lldp_get_mib
{
2181 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2182 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2183 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2184 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2185 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2186 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2187 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2188 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2189 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2190 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2191 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2199 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib
);
2201 /* Configure LLDP MIB Change Event (direct 0x0A01)
2202 * also used for the event (with type in the command field)
2204 struct i40e_aqc_lldp_update_mib
{
2206 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2207 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2213 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib
);
2215 /* Add LLDP TLV (indirect 0x0A02)
2216 * Delete LLDP TLV (indirect 0x0A04)
2218 struct i40e_aqc_lldp_add_tlv
{
2219 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2227 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv
);
2229 /* Update LLDP TLV (indirect 0x0A03) */
2230 struct i40e_aqc_lldp_update_tlv
{
2231 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2240 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv
);
2242 /* Stop LLDP (direct 0x0A05) */
2243 struct i40e_aqc_lldp_stop
{
2245 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2246 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2250 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop
);
2252 /* Start LLDP (direct 0x0A06) */
2254 struct i40e_aqc_lldp_start
{
2256 #define I40E_AQ_LLDP_AGENT_START 0x1
2260 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start
);
2262 /* Get CEE DCBX Oper Config (0x0A07)
2263 * uses the generic descriptor struct
2264 * returns below as indirect response
2267 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2268 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2269 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2270 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2271 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2272 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2274 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2275 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2276 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2277 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2278 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2279 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2280 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2281 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2282 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2283 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2284 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2285 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2287 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2288 * word boundary layout issues, which the Linux compilers silently deal
2289 * with by adding padding, making the actual struct larger than designed.
2290 * However, the FW compiler for the NIC is less lenient and complains
2291 * about the struct. Hence, the struct defined here has an extra byte in
2292 * fields reserved3 and reserved4 to directly acknowledge that padding,
2293 * and the new length is used in the length check macro.
2295 struct i40e_aqc_get_cee_dcb_cfg_v1_resp
{
2303 __le16 oper_app_prio
;
2308 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp
);
2310 struct i40e_aqc_get_cee_dcb_cfg_resp
{
2315 __le16 oper_app_prio
;
2320 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp
);
2322 /* Set Local LLDP MIB (indirect 0x0A08)
2323 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2325 struct i40e_aqc_lldp_set_local_mib
{
2326 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2327 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2328 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2329 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2330 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2331 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2332 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2333 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2338 __le32 address_high
;
2342 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib
);
2344 struct i40e_aqc_lldp_set_local_mib_resp
{
2345 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2350 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp
);
2352 /* Stop/Start LLDP Agent (direct 0x0A09)
2353 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2355 struct i40e_aqc_lldp_stop_start_specific_agent
{
2356 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2357 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2358 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2363 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent
);
2365 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2366 struct i40e_aqc_add_udp_tunnel
{
2370 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2371 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2372 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2373 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2377 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel
);
2379 struct i40e_aqc_add_udp_tunnel_completion
{
2381 u8 filter_entry_index
;
2383 #define I40E_AQC_SINGLE_PF 0x0
2384 #define I40E_AQC_MULTIPLE_PFS 0x1
2389 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion
);
2391 /* remove UDP Tunnel command (0x0B01) */
2392 struct i40e_aqc_remove_udp_tunnel
{
2394 u8 index
; /* 0 to 15 */
2398 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel
);
2400 struct i40e_aqc_del_udp_tunnel_completion
{
2402 u8 index
; /* 0 to 15 */
2404 u8 total_filters_used
;
2408 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion
);
2410 struct i40e_aqc_get_set_rss_key
{
2411 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2412 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2413 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2414 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2421 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key
);
2423 struct i40e_aqc_get_set_rss_key_data
{
2424 u8 standard_rss_key
[0x28];
2425 u8 extended_hash_key
[0xc];
2428 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data
);
2430 struct i40e_aqc_get_set_rss_lut
{
2431 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2432 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2433 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2434 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2436 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2437 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2438 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2440 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2441 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2448 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut
);
2450 /* tunnel key structure 0x0B10 */
2452 struct i40e_aqc_tunnel_key_structure
{
2455 u8 key1_len
; /* 0 to 15 */
2456 u8 key2_len
; /* 0 to 15 */
2458 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2459 /* response flags */
2460 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2461 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2462 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2463 u8 network_key_index
;
2464 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2465 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2466 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2467 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2471 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure
);
2473 /* OEM mode commands (direct 0xFE0x) */
2474 struct i40e_aqc_oem_param_change
{
2476 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2477 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2478 #define I40E_AQ_OEM_PARAM_MAC 2
2479 __le32 param_value1
;
2480 __le16 param_value2
;
2484 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change
);
2486 struct i40e_aqc_oem_state_change
{
2488 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2489 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2493 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change
);
2495 /* Initialize OCSD (0xFE02, direct) */
2496 struct i40e_aqc_opc_oem_ocsd_initialize
{
2499 __le32 ocsd_memory_block_addr_high
;
2500 __le32 ocsd_memory_block_addr_low
;
2501 __le32 requested_update_interval
;
2504 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize
);
2506 /* Initialize OCBB (0xFE03, direct) */
2507 struct i40e_aqc_opc_oem_ocbb_initialize
{
2510 __le32 ocbb_memory_block_addr_high
;
2511 __le32 ocbb_memory_block_addr_low
;
2515 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize
);
2517 /* debug commands */
2519 /* get device id (0xFF00) uses the generic structure */
2521 /* set test more (0xFF01, internal) */
2523 struct i40e_acq_set_test_mode
{
2525 #define I40E_AQ_TEST_PARTIAL 0
2526 #define I40E_AQ_TEST_FULL 1
2527 #define I40E_AQ_TEST_NVM 2
2530 #define I40E_AQ_TEST_OPEN 0
2531 #define I40E_AQ_TEST_CLOSE 1
2532 #define I40E_AQ_TEST_INC 2
2534 __le32 address_high
;
2538 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode
);
2540 /* Debug Read Register command (0xFF03)
2541 * Debug Write Register command (0xFF04)
2543 struct i40e_aqc_debug_reg_read_write
{
2550 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write
);
2552 /* Scatter/gather Reg Read (indirect 0xFF05)
2553 * Scatter/gather Reg Write (indirect 0xFF06)
2556 /* i40e_aq_desc is used for the command */
2557 struct i40e_aqc_debug_reg_sg_element_data
{
2562 /* Debug Modify register (direct 0xFF07) */
2563 struct i40e_aqc_debug_modify_reg
{
2570 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg
);
2572 /* dump internal data (0xFF08, indirect) */
2574 #define I40E_AQ_CLUSTER_ID_AUX 0
2575 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2576 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2577 #define I40E_AQ_CLUSTER_ID_HMC 3
2578 #define I40E_AQ_CLUSTER_ID_MAC0 4
2579 #define I40E_AQ_CLUSTER_ID_MAC1 5
2580 #define I40E_AQ_CLUSTER_ID_MAC2 6
2581 #define I40E_AQ_CLUSTER_ID_MAC3 7
2582 #define I40E_AQ_CLUSTER_ID_DCB 8
2583 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2584 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2585 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2587 struct i40e_aqc_debug_dump_internals
{
2592 __le32 address_high
;
2596 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals
);
2598 struct i40e_aqc_debug_modify_internals
{
2600 u8 cluster_specific_params
[7];
2601 __le32 address_high
;
2605 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals
);
2607 #endif /* _I40E_ADMINQ_CMD_H_ */