4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
30 * Copyright 2018 Joyent, Inc.
31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
35 #include <sys/types.h>
36 #include <sys/thread.h>
37 #include <sys/cpuvar.h>
39 #include <sys/t_lock.h>
40 #include <sys/param.h>
43 #include <sys/class.h>
44 #include <sys/cmn_err.h>
45 #include <sys/debug.h>
47 #include <sys/asm_linkage.h>
48 #include <sys/x_call.h>
49 #include <sys/systm.h>
51 #include <sys/vtrace.h>
54 #include <vm/seg_kmem.h>
55 #include <vm/seg_kp.h>
56 #include <sys/segments.h>
58 #include <sys/stack.h>
59 #include <sys/smp_impldefs.h>
60 #include <sys/x86_archext.h>
61 #include <sys/machsystm.h>
62 #include <sys/traptrace.h>
63 #include <sys/clock.h>
64 #include <sys/cpc_impl.h>
67 #include <sys/dtrace.h>
68 #include <sys/archsystm.h>
70 #include <sys/reboot.h>
71 #include <sys/kdi_machimpl.h>
72 #include <vm/hat_i86.h>
73 #include <vm/vm_dep.h>
74 #include <sys/memnode.h>
75 #include <sys/pci_cfgspace.h>
76 #include <sys/mach_mmu.h>
77 #include <sys/sysmacros.h>
79 #include <sys/hypervisor.h>
81 #include <sys/cpu_module.h>
82 #include <sys/ontrap.h>
84 struct cpu cpus
[1] __aligned(MMU_PAGESIZE
);
85 struct cpu
*cpu
[NCPU
] = {&cpus
[0]};
86 struct cpu
*cpu_free_list
;
87 cpu_core_t cpu_core
[NCPU
];
89 #define cpu_next_free cpu_prev
92 * Useful for disabling MP bring-up on a MP capable system.
97 * to be set by a PSM to indicate what cpus
98 * are sitting around on the system.
103 * This variable is used by the hat layer to decide whether or not
104 * critical sections are needed to prevent race conditions. For sun4m,
105 * this variable is set once enough MP initialization has been done in
106 * order to allow cross calls.
108 int flushes_require_xcalls
;
110 cpuset_t cpu_ready_set
; /* initialized in startup() */
112 static void mp_startup_boot(void);
113 static void mp_startup_hotplug(void);
115 static void cpu_sep_enable(void);
116 static void cpu_sep_disable(void);
117 static void cpu_asysc_enable(void);
118 static void cpu_asysc_disable(void);
121 * Init CPU info - get CPU type info for processor_info system call.
124 init_cpu_info(struct cpu
*cp
)
126 processor_info_t
*pi
= &cp
->cpu_type_info
;
129 * Get clock-frequency property for the CPU.
131 pi
->pi_clock
= cpu_freq
;
134 * Current frequency in Hz.
136 cp
->cpu_curr_clock
= cpu_freq_hz
;
139 * Supported frequencies.
141 if (cp
->cpu_supp_freqs
== NULL
) {
142 cpu_set_supp_freqs(cp
, NULL
);
145 (void) strcpy(pi
->pi_processor_type
, "i386");
147 (void) strcpy(pi
->pi_fputypes
, "i387 compatible");
149 cp
->cpu_idstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
150 cp
->cpu_brandstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
153 * If called for the BSP, cp is equal to current CPU.
154 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
155 * of current CPU as default values for cpu_idstr and cpu_brandstr.
156 * They will be corrected in mp_startup_common() after cpuid_pass1()
157 * has been invoked on target CPU.
159 (void) cpuid_getidstr(CPU
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
160 (void) cpuid_getbrandstr(CPU
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
164 * Configure syscall support on this CPU.
168 init_cpu_syscall(struct cpu
*cp
)
172 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
173 is_x86_feature(x86_featureset
, X86FSET_ASYSC
)) {
178 * The syscall instruction imposes a certain ordering on
179 * segment selectors, so we double-check that ordering
182 CTASSERT(KDS_SEL
== KCS_SEL
+ 8);
183 CTASSERT(UDS_SEL
== U32CS_SEL
+ 8);
184 CTASSERT(UCS_SEL
== U32CS_SEL
+ 16);
188 * Turn syscall/sysret extensions on.
193 * Program the magic registers ..
196 ((uint64_t)(U32CS_SEL
<< 16 | KCS_SEL
)) << 32);
197 if (kpti_enable
== 1) {
199 (uint64_t)(uintptr_t)tr_sys_syscall
);
201 (uint64_t)(uintptr_t)tr_sys_syscall32
);
204 (uint64_t)(uintptr_t)sys_syscall
);
206 (uint64_t)(uintptr_t)sys_syscall32
);
210 * This list of flags is masked off the incoming
211 * %rfl when we enter the kernel.
213 flags
= PS_IE
| PS_T
;
214 if (is_x86_feature(x86_featureset
, X86FSET_SMAP
) == B_TRUE
)
216 wrmsr(MSR_AMD_SFMASK
, flags
);
220 * On 64-bit kernels on Nocona machines, the 32-bit syscall
221 * variant isn't available to 32-bit applications, but sysenter is.
223 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
224 is_x86_feature(x86_featureset
, X86FSET_SEP
)) {
228 * The sysenter instruction imposes a certain ordering on
229 * segment selectors, so we double-check that ordering
230 * here. See "sysenter" in Intel document 245471-012, "IA-32
231 * Intel Architecture Software Developer's Manual Volume 2:
232 * Instruction Set Reference"
234 CTASSERT(KDS_SEL
== KCS_SEL
+ 8);
236 CTASSERT(U32CS_SEL
== ((KCS_SEL
+ 16) | 3));
237 CTASSERT(UDS_SEL
== U32CS_SEL
+ 8);
243 * resume() sets this value to the base of the threads stack
244 * via a context handler.
246 wrmsr(MSR_INTC_SEP_ESP
, 0);
248 if (kpti_enable
== 1) {
249 wrmsr(MSR_INTC_SEP_EIP
,
250 (uint64_t)(uintptr_t)tr_sys_sysenter
);
252 wrmsr(MSR_INTC_SEP_EIP
,
253 (uint64_t)(uintptr_t)sys_sysenter
);
262 * Configure per-cpu ID GDT
265 init_cpu_id_gdt(struct cpu
*cp
)
267 /* Write cpu_id into limit field of GDT for usermode retrieval */
269 set_usegd(&cp
->cpu_gdt
[GDT_CPUID
], SDP_SHORT
, NULL
, cp
->cpu_id
,
270 SDT_MEMRODA
, SEL_UPL
, SDP_BYTES
, SDP_OP32
);
271 #elif defined(__i386)
272 set_usegd(&cp
->cpu_gdt
[GDT_CPUID
], NULL
, cp
->cpu_id
, SDT_MEMRODA
,
273 SEL_UPL
, SDP_BYTES
, SDP_OP32
);
276 #endif /* !defined(__xpv) */
279 * Multiprocessor initialization.
281 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
282 * startup and idle threads for the specified CPU.
283 * Parameter boot is true for boot time operations and is false for CPU
287 mp_cpu_configure_common(int cpun
, boolean_t boot
)
294 extern int idle_cpu_prefer_mwait
;
295 extern void cpu_idle_mwait();
298 extern void cpu_idle();
301 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cpun
];
304 ASSERT(MUTEX_HELD(&cpu_lock
));
305 ASSERT(cpun
< NCPU
&& cpu
[cpun
] == NULL
);
307 if (cpu_free_list
== NULL
) {
308 cp
= kmem_zalloc(sizeof (*cp
), KM_SLEEP
);
311 cpu_free_list
= cp
->cpu_next_free
;
314 cp
->cpu_m
.mcpu_istamp
= cpun
<< 16;
316 /* Create per CPU specific threads in the process p0. */
320 * Initialize the dispatcher first.
324 cpu_vm_data_init(cp
);
327 * Allocate and initialize the startup thread for this CPU.
328 * Interrupt and process switch stacks get allocated later
329 * when the CPU starts running.
331 tp
= thread_create(NULL
, 0, NULL
, NULL
, 0, procp
,
332 TS_STOPPED
, maxclsyspri
);
335 * Set state to TS_ONPROC since this thread will start running
336 * as soon as the CPU comes online.
338 * All the other fields of the thread structure are setup by
341 THREAD_ONPROC(tp
, cp
);
343 tp
->t_bound_cpu
= cp
;
344 tp
->t_affinitycnt
= 1;
346 tp
->t_disp_queue
= cp
->cpu_disp
;
349 * Setup thread to start in mp_startup_common.
352 tp
->t_sp
= (uintptr_t)(sp
- MINFRAME
);
354 tp
->t_sp
-= STACK_ENTRY_ALIGN
; /* fake a call */
357 * Setup thread start entry point for boot or hotplug.
360 tp
->t_pc
= (uintptr_t)mp_startup_boot
;
362 tp
->t_pc
= (uintptr_t)mp_startup_hotplug
;
369 cp
->cpu_dispthread
= tp
;
370 cp
->cpu_dispatch_pri
= DISP_PRIO(tp
);
373 * cpu_base_spl must be set explicitly here to prevent any blocking
374 * operations in mp_startup_common from causing the spl of the cpu
375 * to drop to 0 (allowing device interrupts before we're ready) in
377 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
378 * As an extra bit of security on DEBUG kernels, this is enforced with
379 * an assertion in mp_startup_common() -- before cpu_base_spl is set
380 * to its proper value.
382 cp
->cpu_base_spl
= ipltospl(LOCK_LEVEL
);
385 * Now, initialize per-CPU idle thread for this CPU.
387 tp
= thread_create(NULL
, PAGESIZE
, idle
, NULL
, 0, procp
, TS_ONPROC
, -1);
389 cp
->cpu_idle_thread
= tp
;
392 tp
->t_bound_cpu
= cp
;
393 tp
->t_affinitycnt
= 1;
395 tp
->t_disp_queue
= cp
->cpu_disp
;
398 * Bootstrap the CPU's PG data
400 pg_cpu_bootstrap(cp
);
403 * Perform CPC initialization on the new CPU.
408 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
411 setup_vaddr_for_ppcopy(cp
);
414 * Allocate page for new GDT and initialize from current GDT.
417 ASSERT((sizeof (*cp
->cpu_gdt
) * NGDT
) <= PAGESIZE
);
419 cp
->cpu_gdt
= kmem_zalloc(PAGESIZE
, KM_SLEEP
);
420 bcopy(CPU
->cpu_gdt
, cp
->cpu_gdt
, (sizeof (*cp
->cpu_gdt
) * NGDT
));
426 set_usegd(&cp
->cpu_gdt
[GDT_GS
], cp
, sizeof (struct cpu
) -1, SDT_MEMRWA
,
431 * Allocate pages for the CPU LDT.
433 cp
->cpu_m
.mcpu_ldt
= kmem_zalloc(LDT_CPU_SIZE
, KM_SLEEP
);
434 cp
->cpu_m
.mcpu_ldt_len
= 0;
437 * Allocate a per-CPU IDT and initialize the new IDT to the currently
441 ASSERT((sizeof (*CPU
->cpu_idt
) * NIDT
) <= PAGESIZE
);
443 cp
->cpu_idt
= kmem_alloc(PAGESIZE
, KM_SLEEP
);
444 bcopy(CPU
->cpu_idt
, cp
->cpu_idt
, PAGESIZE
);
447 * alloc space for cpuid info
449 cpuid_alloc_space(cp
);
451 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) &&
452 idle_cpu_prefer_mwait
) {
453 cp
->cpu_m
.mcpu_mwait
= cpuid_mwait_alloc(cp
);
454 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle_mwait
;
457 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle
;
466 * alloc space for ucode_info
468 ucode_alloc_space(cp
);
474 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
476 ttc
->ttc_first
= (uintptr_t)kmem_zalloc(trap_trace_bufsize
, KM_SLEEP
);
477 ttc
->ttc_next
= ttc
->ttc_first
;
478 ttc
->ttc_limit
= ttc
->ttc_first
+ trap_trace_bufsize
;
482 * Record that we have another CPU.
485 * Initialize the interrupt threads for this CPU
487 cpu_intr_alloc(cp
, NINTR_THREADS
);
489 cp
->cpu_flags
= CPU_OFFLINE
| CPU_QUIESCED
| CPU_POWEROFF
;
493 * Add CPU to list of available CPUs. It'll be on the active list
494 * after mp_startup_common().
502 * Undo what was done in mp_cpu_configure_common
505 mp_cpu_unconfigure_common(struct cpu
*cp
, int error
)
507 ASSERT(MUTEX_HELD(&cpu_lock
));
510 * Remove the CPU from the list of available CPUs.
512 cpu_del_unit(cp
->cpu_id
);
514 if (error
== ETIMEDOUT
) {
516 * The cpu was started, but never *seemed* to run any
517 * code in the kernel; it's probably off spinning in its
518 * own private world, though with potential references to
519 * our kmem-allocated IDTs and GDTs (for example).
521 * Worse still, it may actually wake up some time later,
522 * so rather than guess what it might or might not do, we
523 * leave the fundamental data structures intact.
530 * At this point, the only threads bound to this CPU should
531 * special per-cpu threads: it's idle thread, it's pause threads,
532 * and it's interrupt threads. Clean these up.
534 cpu_destroy_bound_threads(cp
);
535 cp
->cpu_idle_thread
= NULL
;
538 * Free the interrupt stack.
541 cp
->cpu_intr_stack
- (INTR_STACK_SIZE
- SA(MINFRAME
)));
542 cp
->cpu_intr_stack
= NULL
;
546 * Discard the trap trace buffer
549 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cp
->cpu_id
];
551 kmem_free((void *)ttc
->ttc_first
, trap_trace_bufsize
);
552 ttc
->ttc_first
= NULL
;
558 ucode_free_space(cp
);
560 /* Free CPU ID string and brand string. */
562 kmem_free(cp
->cpu_idstr
, CPU_IDSTRLEN
);
563 cp
->cpu_idstr
= NULL
;
565 if (cp
->cpu_brandstr
) {
566 kmem_free(cp
->cpu_brandstr
, CPU_IDSTRLEN
);
567 cp
->cpu_brandstr
= NULL
;
571 if (cp
->cpu_m
.mcpu_mwait
!= NULL
) {
572 cpuid_mwait_free(cp
);
573 cp
->cpu_m
.mcpu_mwait
= NULL
;
576 cpuid_free_space(cp
);
578 if (cp
->cpu_idt
!= CPU
->cpu_idt
)
579 kmem_free(cp
->cpu_idt
, PAGESIZE
);
582 kmem_free(cp
->cpu_m
.mcpu_ldt
, LDT_CPU_SIZE
);
583 cp
->cpu_m
.mcpu_ldt
= NULL
;
584 cp
->cpu_m
.mcpu_ldt_len
= 0;
586 kmem_free(cp
->cpu_gdt
, PAGESIZE
);
589 if (cp
->cpu_supp_freqs
!= NULL
) {
590 size_t len
= strlen(cp
->cpu_supp_freqs
) + 1;
591 kmem_free(cp
->cpu_supp_freqs
, len
);
592 cp
->cpu_supp_freqs
= NULL
;
595 teardown_vaddr_for_ppcopy(cp
);
599 cp
->cpu_dispthread
= NULL
;
600 cp
->cpu_thread
= NULL
; /* discarded by cpu_destroy_bound_threads() */
602 cpu_vm_data_destroy(cp
);
608 bzero(cp
, sizeof (*cp
));
609 cp
->cpu_next_free
= cpu_free_list
;
614 * Apply workarounds for known errata, and warn about those that are absent.
616 * System vendors occasionally create configurations which contain different
617 * revisions of the CPUs that are almost but not exactly the same. At the
618 * time of writing, this meant that their clock rates were the same, their
619 * feature sets were the same, but the required workaround were -not-
620 * necessarily the same. So, this routine is invoked on -every- CPU soon
621 * after starting to make sure that the resulting system contains the most
622 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
625 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
626 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
627 * prior to acknowledging their readiness to the master, so this routine will
628 * never be executed by multiple CPUs in parallel, thus making updates to
631 * These workarounds are based on Rev 3.57 of the Revision Guide for
632 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
635 #if defined(OPTERON_ERRATUM_88)
636 int opteron_erratum_88
; /* if non-zero -> at least one cpu has it */
639 #if defined(OPTERON_ERRATUM_91)
640 int opteron_erratum_91
; /* if non-zero -> at least one cpu has it */
643 #if defined(OPTERON_ERRATUM_93)
644 int opteron_erratum_93
; /* if non-zero -> at least one cpu has it */
647 #if defined(OPTERON_ERRATUM_95)
648 int opteron_erratum_95
; /* if non-zero -> at least one cpu has it */
651 #if defined(OPTERON_ERRATUM_100)
652 int opteron_erratum_100
; /* if non-zero -> at least one cpu has it */
655 #if defined(OPTERON_ERRATUM_108)
656 int opteron_erratum_108
; /* if non-zero -> at least one cpu has it */
659 #if defined(OPTERON_ERRATUM_109)
660 int opteron_erratum_109
; /* if non-zero -> at least one cpu has it */
663 #if defined(OPTERON_ERRATUM_121)
664 int opteron_erratum_121
; /* if non-zero -> at least one cpu has it */
667 #if defined(OPTERON_ERRATUM_122)
668 int opteron_erratum_122
; /* if non-zero -> at least one cpu has it */
671 #if defined(OPTERON_ERRATUM_123)
672 int opteron_erratum_123
; /* if non-zero -> at least one cpu has it */
675 #if defined(OPTERON_ERRATUM_131)
676 int opteron_erratum_131
; /* if non-zero -> at least one cpu has it */
679 #if defined(OPTERON_WORKAROUND_6336786)
680 int opteron_workaround_6336786
; /* non-zero -> WA relevant and applied */
681 int opteron_workaround_6336786_UP
= 0; /* Not needed for UP */
684 #if defined(OPTERON_WORKAROUND_6323525)
685 int opteron_workaround_6323525
; /* if non-zero -> at least one cpu has it */
688 #if defined(OPTERON_ERRATUM_298)
689 int opteron_erratum_298
;
692 #if defined(OPTERON_ERRATUM_721)
693 int opteron_erratum_721
;
697 workaround_warning(cpu_t
*cp
, uint_t erratum
)
699 cmn_err(CE_WARN
, "cpu%d: no workaround for erratum %u",
700 cp
->cpu_id
, erratum
);
704 workaround_applied(uint_t erratum
)
706 if (erratum
> 1000000)
707 cmn_err(CE_CONT
, "?workaround applied for cpu issue #%d\n",
710 cmn_err(CE_CONT
, "?workaround applied for cpu erratum #%d\n",
715 msr_warning(cpu_t
*cp
, const char *rw
, uint_t msr
, int error
)
717 cmn_err(CE_WARN
, "cpu%d: couldn't %smsr 0x%x, error %d",
718 cp
->cpu_id
, rw
, msr
, error
);
722 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
726 opteron_get_nnodes(void)
728 static uint_t nnodes
= 0;
735 * This routine uses a PCI config space based mechanism
736 * for retrieving the number of nodes in the system.
737 * Device 24, function 0, offset 0x60 as used here is not
738 * AMD processor architectural, and may not work on processor
739 * families other than those listed below.
741 * Callers of this routine must ensure that we're running on
742 * a processor which supports this mechanism.
743 * The assertion below is meant to catch calls on unsupported
746 family
= cpuid_getfamily(CPU
);
747 ASSERT(family
== 0xf || family
== 0x10 || family
== 0x11);
751 * Obtain the number of nodes in the system from
752 * bits [6:4] of the Node ID register on node 0.
754 * The actual node count is NodeID[6:4] + 1
756 * The Node ID register is accessed via function 0,
757 * offset 0x60. Node 0 is device 24.
759 nnodes
= ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
765 do_erratum_298(struct cpu
*cpu
)
767 static int osvwrc
= -3;
768 extern int osvw_opteron_erratum(cpu_t
*, uint_t
);
771 * L2 Eviction May Occur During Processor Operation To Set
772 * Accessed or Dirty Bit.
775 osvwrc
= osvw_opteron_erratum(cpu
, 298);
777 /* osvw return codes should be consistent for all cpus */
778 ASSERT(osvwrc
== osvw_opteron_erratum(cpu
, 298));
782 case 0: /* erratum is not present: do nothing */
784 case 1: /* erratum is present: BIOS workaround applied */
786 * check if workaround is actually in place and issue warning
789 if (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
790 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0)) {
791 #if defined(OPTERON_ERRATUM_298)
792 opteron_erratum_298
++;
794 workaround_warning(cpu
, 298);
799 case -1: /* cannot determine via osvw: check cpuid */
800 if ((cpuid_opteron_erratum(cpu
, 298) > 0) &&
801 (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
802 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0))) {
803 #if defined(OPTERON_ERRATUM_298)
804 opteron_erratum_298
++;
806 workaround_warning(cpu
, 298);
816 workaround_errata(struct cpu
*cpu
)
823 if (cpuid_opteron_erratum(cpu
, 88) > 0) {
825 * SWAPGS May Fail To Read Correct GS Base
827 #if defined(OPTERON_ERRATUM_88)
829 * The workaround is an mfence in the relevant assembler code
831 opteron_erratum_88
++;
833 workaround_warning(cpu
, 88);
838 if (cpuid_opteron_erratum(cpu
, 91) > 0) {
840 * Software Prefetches May Report A Page Fault
842 #if defined(OPTERON_ERRATUM_91)
846 opteron_erratum_91
++;
848 workaround_warning(cpu
, 91);
853 if (cpuid_opteron_erratum(cpu
, 93) > 0) {
855 * RSM Auto-Halt Restart Returns to Incorrect RIP
857 #if defined(OPTERON_ERRATUM_93)
861 opteron_erratum_93
++;
863 workaround_warning(cpu
, 93);
869 if (cpuid_opteron_erratum(cpu
, 95) > 0) {
871 * RET Instruction May Return to Incorrect EIP
873 #if defined(OPTERON_ERRATUM_95)
876 * Workaround this by ensuring that 32-bit user code and
877 * 64-bit kernel code never occupy the same address
880 if (_userlimit32
> 0xc0000000ul
)
881 *(uintptr_t *)&_userlimit32
= 0xc0000000ul
;
884 ASSERT((uint32_t)COREHEAP_BASE
== 0xc0000000u
);
885 opteron_erratum_95
++;
888 workaround_warning(cpu
, 95);
893 if (cpuid_opteron_erratum(cpu
, 100) > 0) {
895 * Compatibility Mode Branches Transfer to Illegal Address
897 #if defined(OPTERON_ERRATUM_100)
901 opteron_erratum_100
++;
903 workaround_warning(cpu
, 100);
909 if (cpuid_opteron_erratum(cpu
, 108) > 0) {
911 * CPUID Instruction May Return Incorrect Model Number In
914 #if defined(OPTERON_ERRATUM_108)
916 * (Our cpuid-handling code corrects the model number on
920 workaround_warning(cpu
, 108);
926 if (cpuid_opteron_erratum(cpu
, 109) > 0) do {
928 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
930 #if defined(OPTERON_ERRATUM_109)
932 * The "workaround" is to print a warning to upgrade the BIOS
935 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
938 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
939 msr_warning(cpu
, "rd", msr
, err
);
940 workaround_warning(cpu
, 109);
944 opteron_erratum_109
++;
946 workaround_warning(cpu
, 109);
949 /*CONSTANTCONDITION*/
953 if (cpuid_opteron_erratum(cpu
, 121) > 0) {
955 * Sequential Execution Across Non_Canonical Boundary Caused
958 #if defined(OPTERON_ERRATUM_121)
961 * Erratum 121 is only present in long (64 bit) mode.
962 * Workaround is to include the page immediately before the
963 * va hole to eliminate the possibility of system hangs due to
964 * sequential execution across the va hole boundary.
966 if (opteron_erratum_121
)
967 opteron_erratum_121
++;
970 hole_start
-= PAGESIZE
;
973 * hole_start not yet initialized by
974 * mmu_init. Initialize hole_start
975 * with value to be subtracted.
977 hole_start
= PAGESIZE
;
979 opteron_erratum_121
++;
983 workaround_warning(cpu
, 121);
989 if (cpuid_opteron_erratum(cpu
, 122) > 0) do {
991 * TLB Flush Filter May Cause Coherency Problem in
992 * Multiprocessor Systems
994 #if defined(OPTERON_ERRATUM_122)
996 const uint_t msr
= MSR_AMD_HWCR
;
1000 * Erratum 122 is only present in MP configurations (multi-core
1001 * or multi-processor).
1004 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1006 if (!opteron_erratum_122
&& xpv_nr_phys_cpus() == 1)
1009 if (!opteron_erratum_122
&& opteron_get_nnodes() == 1 &&
1010 cpuid_get_ncpu_per_chip(cpu
) == 1)
1013 /* disable TLB Flush Filter */
1015 if ((error
= checked_rdmsr(msr
, &value
)) != 0) {
1016 msr_warning(cpu
, "rd", msr
, error
);
1017 workaround_warning(cpu
, 122);
1020 value
|= (uint64_t)AMD_HWCR_FFDIS
;
1021 if ((error
= checked_wrmsr(msr
, value
)) != 0) {
1022 msr_warning(cpu
, "wr", msr
, error
);
1023 workaround_warning(cpu
, 122);
1027 opteron_erratum_122
++;
1029 workaround_warning(cpu
, 122);
1032 /*CONSTANTCONDITION*/
1036 if (cpuid_opteron_erratum(cpu
, 123) > 0) do {
1038 * Bypassed Reads May Cause Data Corruption of System Hang in
1039 * Dual Core Processors
1041 #if defined(OPTERON_ERRATUM_123)
1043 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
1047 * Erratum 123 applies only to multi-core cpus.
1049 if (cpuid_get_ncpu_per_chip(cpu
) < 2)
1052 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1056 * The "workaround" is to print a warning to upgrade the BIOS
1058 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
1059 msr_warning(cpu
, "rd", msr
, err
);
1060 workaround_warning(cpu
, 123);
1064 opteron_erratum_123
++;
1066 workaround_warning(cpu
, 123);
1070 /*CONSTANTCONDITION*/
1074 if (cpuid_opteron_erratum(cpu
, 131) > 0) do {
1076 * Multiprocessor Systems with Four or More Cores May Deadlock
1077 * Waiting for a Probe Response
1079 #if defined(OPTERON_ERRATUM_131)
1081 const uint_t msr
= MSR_AMD_NB_CFG
;
1082 const uint64_t wabits
=
1083 AMD_NB_CFG_SRQ_HEARTBEAT
| AMD_NB_CFG_SRQ_SPR
;
1087 * Erratum 131 applies to any system with four or more cores.
1089 if (opteron_erratum_131
)
1092 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1094 if (xpv_nr_phys_cpus() < 4)
1097 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu
) < 4)
1101 * Print a warning if neither of the workarounds for
1102 * erratum 131 is present.
1104 if ((error
= checked_rdmsr(msr
, &nbcfg
)) != 0) {
1105 msr_warning(cpu
, "rd", msr
, error
);
1106 workaround_warning(cpu
, 131);
1108 } else if ((nbcfg
& wabits
) == 0) {
1109 opteron_erratum_131
++;
1111 /* cannot have both workarounds set */
1112 ASSERT((nbcfg
& wabits
) != wabits
);
1115 workaround_warning(cpu
, 131);
1118 /*CONSTANTCONDITION*/
1122 * This isn't really an erratum, but for convenience the
1123 * detection/workaround code lives here and in cpuid_opteron_erratum.
1125 if (cpuid_opteron_erratum(cpu
, 6336786) > 0) {
1126 #if defined(OPTERON_WORKAROUND_6336786)
1128 * Disable C1-Clock ramping on multi-core/multi-processor
1129 * K8 platforms to guard against TSC drift.
1131 if (opteron_workaround_6336786
) {
1132 opteron_workaround_6336786
++;
1134 } else if ((DOMAIN_IS_INITDOMAIN(xen_info
) &&
1135 xpv_nr_phys_cpus() > 1) ||
1136 opteron_workaround_6336786_UP
) {
1138 * XXPV Hmm. We can't walk the Northbridges on
1139 * the hypervisor; so just complain and drive
1140 * on. This probably needs to be fixed in
1141 * the hypervisor itself.
1143 opteron_workaround_6336786
++;
1144 workaround_warning(cpu
, 6336786);
1146 } else if ((opteron_get_nnodes() *
1147 cpuid_get_ncpu_per_chip(cpu
) > 1) ||
1148 opteron_workaround_6336786_UP
) {
1150 uint_t node
, nnodes
;
1153 nnodes
= opteron_get_nnodes();
1154 for (node
= 0; node
< nnodes
; node
++) {
1156 * Clear PMM7[1:0] (function 3, offset 0x87)
1157 * Northbridge device is the node id + 24.
1159 data
= pci_getb_func(0, node
+ 24, 3, 0x87);
1161 pci_putb_func(0, node
+ 24, 3, 0x87, data
);
1163 opteron_workaround_6336786
++;
1167 workaround_warning(cpu
, 6336786);
1174 * Mutex primitives don't work as expected.
1176 if (cpuid_opteron_erratum(cpu
, 6323525) > 0) {
1177 #if defined(OPTERON_WORKAROUND_6323525)
1179 * This problem only occurs with 2 or more cores. If bit in
1180 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1181 * is to patch the semaphone routines with the lfence
1182 * instruction to provide necessary load memory barrier with
1183 * possible subsequent read-modify-write ops.
1185 * It is too early in boot to call the patch routine so
1186 * set erratum variable to be done in startup_end().
1188 if (opteron_workaround_6323525
) {
1189 opteron_workaround_6323525
++;
1191 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
)) {
1192 if (DOMAIN_IS_INITDOMAIN(xen_info
)) {
1194 * XXPV Use dom0_msr here when extended
1195 * operations are supported?
1197 if (xpv_nr_phys_cpus() > 1)
1198 opteron_workaround_6323525
++;
1201 * We have no way to tell how many physical
1202 * cpus there are, or even if this processor
1203 * has the problem, so enable the workaround
1204 * unconditionally (at some performance cost).
1206 opteron_workaround_6323525
++;
1209 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
) &&
1210 ((opteron_get_nnodes() *
1211 cpuid_get_ncpu_per_chip(cpu
)) > 1)) {
1212 if ((xrdmsr(MSR_AMD_BU_CFG
) & (UINT64_C(1) << 33)) == 0)
1213 opteron_workaround_6323525
++;
1217 workaround_warning(cpu
, 6323525);
1222 missing
+= do_erratum_298(cpu
);
1224 if (cpuid_opteron_erratum(cpu
, 721) > 0) {
1225 #if defined(OPTERON_ERRATUM_721)
1228 if (!on_trap(&otd
, OT_DATA_ACCESS
))
1229 wrmsr(MSR_AMD_DE_CFG
,
1230 rdmsr(MSR_AMD_DE_CFG
) | AMD_DE_CFG_E721
);
1233 opteron_erratum_721
++;
1235 workaround_warning(cpu
, 721);
1248 workaround_errata_end()
1250 #if defined(OPTERON_ERRATUM_88)
1251 if (opteron_erratum_88
)
1252 workaround_applied(88);
1254 #if defined(OPTERON_ERRATUM_91)
1255 if (opteron_erratum_91
)
1256 workaround_applied(91);
1258 #if defined(OPTERON_ERRATUM_93)
1259 if (opteron_erratum_93
)
1260 workaround_applied(93);
1262 #if defined(OPTERON_ERRATUM_95)
1263 if (opteron_erratum_95
)
1264 workaround_applied(95);
1266 #if defined(OPTERON_ERRATUM_100)
1267 if (opteron_erratum_100
)
1268 workaround_applied(100);
1270 #if defined(OPTERON_ERRATUM_108)
1271 if (opteron_erratum_108
)
1272 workaround_applied(108);
1274 #if defined(OPTERON_ERRATUM_109)
1275 if (opteron_erratum_109
) {
1277 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1278 " processor\nerratum 109 was not detected; updating your"
1279 " system's BIOS to a version\ncontaining this"
1280 " microcode patch is HIGHLY recommended or erroneous"
1281 " system\noperation may occur.\n");
1284 #if defined(OPTERON_ERRATUM_121)
1285 if (opteron_erratum_121
)
1286 workaround_applied(121);
1288 #if defined(OPTERON_ERRATUM_122)
1289 if (opteron_erratum_122
)
1290 workaround_applied(122);
1292 #if defined(OPTERON_ERRATUM_123)
1293 if (opteron_erratum_123
) {
1295 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1296 " processor\nerratum 123 was not detected; updating your"
1297 " system's BIOS to a version\ncontaining this"
1298 " microcode patch is HIGHLY recommended or erroneous"
1299 " system\noperation may occur.\n");
1302 #if defined(OPTERON_ERRATUM_131)
1303 if (opteron_erratum_131
) {
1305 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1306 " processor\nerratum 131 was not detected; updating your"
1307 " system's BIOS to a version\ncontaining this"
1308 " microcode patch is HIGHLY recommended or erroneous"
1309 " system\noperation may occur.\n");
1312 #if defined(OPTERON_WORKAROUND_6336786)
1313 if (opteron_workaround_6336786
)
1314 workaround_applied(6336786);
1316 #if defined(OPTERON_WORKAROUND_6323525)
1317 if (opteron_workaround_6323525
)
1318 workaround_applied(6323525);
1320 #if defined(OPTERON_ERRATUM_298)
1321 if (opteron_erratum_298
) {
1323 "BIOS microcode patch for AMD 64/Opteron(tm)"
1324 " processor\nerratum 298 was not detected; updating your"
1325 " system's BIOS to a version\ncontaining this"
1326 " microcode patch is HIGHLY recommended or erroneous"
1327 " system\noperation may occur.\n");
1330 #if defined(OPTERON_ERRATUM_721)
1331 if (opteron_erratum_721
)
1332 workaround_applied(721);
1337 * The procset_slave and procset_master are used to synchronize
1338 * between the control CPU and the target CPU when starting CPUs.
1340 static cpuset_t procset_slave
, procset_master
;
1343 mp_startup_wait(cpuset_t
*sp
, processorid_t cpuid
)
1347 for (tempset
= *sp
; !CPU_IN_SET(tempset
, cpuid
);
1348 tempset
= *(volatile cpuset_t
*)sp
) {
1351 CPUSET_ATOMIC_DEL(*(cpuset_t
*)sp
, cpuid
);
1355 mp_startup_signal(cpuset_t
*sp
, processorid_t cpuid
)
1359 CPUSET_ATOMIC_ADD(*(cpuset_t
*)sp
, cpuid
);
1360 for (tempset
= *sp
; CPU_IN_SET(tempset
, cpuid
);
1361 tempset
= *(volatile cpuset_t
*)sp
) {
1367 mp_start_cpu_common(cpu_t
*cp
, boolean_t boot
)
1369 _NOTE(ARGUNUSED(boot
));
1375 processorid_t cpuid
;
1377 extern void cpupm_init(cpu_t
*);
1382 ctx
= mach_cpucontext_alloc(cp
);
1385 "cpu%d: failed to allocate context", cp
->cpu_id
);
1388 error
= mach_cpu_start(cp
, ctx
);
1391 "cpu%d: failed to start, error %d", cp
->cpu_id
, error
);
1392 mach_cpucontext_free(cp
, ctx
, error
);
1396 for (delays
= 0, tempset
= procset_slave
; !CPU_IN_SET(tempset
, cpuid
);
1398 if (delays
== 500) {
1400 * After five seconds, things are probably looking
1401 * a bit bleak - explain the hang.
1403 cmn_err(CE_NOTE
, "cpu%d: started, "
1404 "but not running in the kernel yet", cpuid
);
1405 } else if (delays
> 2000) {
1407 * We waited at least 20 seconds, bail ..
1410 cmn_err(CE_WARN
, "cpu%d: timed out", cpuid
);
1411 mach_cpucontext_free(cp
, ctx
, error
);
1416 * wait at least 10ms, then check again..
1418 delay(USEC_TO_TICK_ROUNDUP(10000));
1419 tempset
= *((volatile cpuset_t
*)&procset_slave
);
1421 CPUSET_ATOMIC_DEL(procset_slave
, cpuid
);
1423 mach_cpucontext_free(cp
, ctx
, 0);
1426 if (tsc_gethrtime_enable
)
1427 tsc_sync_master(cpuid
);
1430 if (dtrace_cpu_init
!= NULL
) {
1431 (*dtrace_cpu_init
)(cpuid
);
1435 * During CPU DR operations, the cpu_lock is held by current
1436 * (the control) thread. We can't release the cpu_lock here
1437 * because that will break the CPU DR logic.
1438 * On the other hand, CPUPM and processor group initialization
1439 * routines need to access the cpu_lock. So we invoke those
1440 * routines here on behalf of mp_startup_common().
1442 * CPUPM and processor group initialization routines depend
1443 * on the cpuid probing results. Wait for mp_startup_common()
1444 * to signal that cpuid probing is done.
1446 mp_startup_wait(&procset_slave
, cpuid
);
1450 (void) pg_cpu_init(cp
, B_FALSE
);
1452 mp_startup_signal(&procset_master
, cpuid
);
1458 * Start a single cpu, assuming that the kernel context is available
1459 * to successfully start another cpu.
1461 * (For example, real mode code is mapped into the right place
1462 * in memory and is ready to be run.)
1465 start_cpu(processorid_t who
)
1474 * Check if there's at least a Mbyte of kmem available
1475 * before attempting to start the cpu.
1477 if (kmem_avail() < 1024 * 1024) {
1479 * Kick off a reap in case that helps us with
1487 * First configure cpu.
1489 cp
= mp_cpu_configure_common(who
, B_TRUE
);
1495 error
= mp_start_cpu_common(cp
, B_TRUE
);
1497 mp_cpu_unconfigure_common(cp
, error
);
1501 mutex_exit(&cpu_lock
);
1502 tempset
= cpu_ready_set
;
1503 while (!CPU_IN_SET(tempset
, who
)) {
1505 tempset
= *((volatile cpuset_t
*)&cpu_ready_set
);
1507 mutex_enter(&cpu_lock
);
1513 start_other_cpus(int cprboot
)
1515 _NOTE(ARGUNUSED(cprboot
));
1518 uint_t bootcpuid
= 0;
1521 * Initialize our own cpu_info.
1526 init_cpu_id_gdt(CPU
);
1529 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_idstr
);
1530 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_brandstr
);
1533 * KPTI initialisation happens very early in boot, before logging is
1534 * set up. Output a status message now as the boot CPU comes online.
1536 cmn_err(CE_CONT
, "?KPTI %s (PCID %s, INVPCID %s)\n",
1537 kpti_enable
? "enabled" : "disabled",
1538 x86_use_pcid
== 1 ? "in use" :
1539 (is_x86_feature(x86_featureset
, X86FSET_PCID
) ? "disabled" :
1541 x86_use_pcid
== 1 && x86_use_invpcid
== 1 ? "in use" :
1542 (is_x86_feature(x86_featureset
, X86FSET_INVPCID
) ? "disabled" :
1546 * Initialize our syscall handlers
1548 init_cpu_syscall(CPU
);
1551 * Take the boot cpu out of the mp_cpus set because we know
1552 * it's already running. Add it to the cpu_ready_set for
1553 * precisely the same reason.
1555 CPUSET_DEL(mp_cpus
, bootcpuid
);
1556 CPUSET_ADD(cpu_ready_set
, bootcpuid
);
1559 * skip the rest of this if
1560 * . only 1 cpu dectected and system isn't hotplug-capable
1563 if ((CPUSET_ISNULL(mp_cpus
) && plat_dr_support_cpu() == 0) ||
1566 cmn_err(CE_CONT
, "?***** Not in MP mode\n");
1571 * perform such initialization as is needed
1572 * to be able to take CPUs on- and off-line.
1576 xc_init_cpu(CPU
); /* initialize processor crosscalls */
1578 if (mach_cpucontext_init() != 0)
1581 flushes_require_xcalls
= 1;
1584 * We lock our affinity to the master CPU to ensure that all slave CPUs
1585 * do their TSC syncs with the same CPU.
1587 affinity_set(CPU_CURRENT
);
1589 for (who
= 0; who
< NCPU
; who
++) {
1590 if (!CPU_IN_SET(mp_cpus
, who
))
1592 ASSERT(who
!= bootcpuid
);
1594 mutex_enter(&cpu_lock
);
1595 if (start_cpu(who
) != 0)
1596 CPUSET_DEL(mp_cpus
, who
);
1597 cpu_state_change_notify(who
, CPU_SETUP
);
1598 mutex_exit(&cpu_lock
);
1601 /* Free the space allocated to hold the microcode file */
1606 mach_cpucontext_fini();
1609 if (get_hwenv() == HW_NATIVE
)
1610 workaround_errata_end();
1611 cmi_post_mpstartup();
1613 if (use_mp
&& ncpus
!= boot_max_ncpus
) {
1615 "System detected %d cpus, but "
1616 "only %d cpu(s) were enabled during boot.",
1617 boot_max_ncpus
, ncpus
);
1619 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1625 mp_cpu_configure(int cpuid
)
1629 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1633 cp
= cpu_get(cpuid
);
1639 * Check if there's at least a Mbyte of kmem available
1640 * before attempting to start the cpu.
1642 if (kmem_avail() < 1024 * 1024) {
1644 * Kick off a reap in case that helps us with
1651 cp
= mp_cpu_configure_common(cpuid
, B_FALSE
);
1652 ASSERT(cp
!= NULL
&& cpu_get(cpuid
) == cp
);
1654 return (cp
!= NULL
? 0 : EAGAIN
);
1658 mp_cpu_unconfigure(int cpuid
)
1662 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1664 } else if (cpuid
< 0 || cpuid
>= max_ncpus
) {
1668 cp
= cpu_get(cpuid
);
1672 mp_cpu_unconfigure_common(cp
, 0);
1678 * Startup function for 'other' CPUs (besides boot cpu).
1679 * Called from real_mode_start.
1681 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1682 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1683 * hat_unload which requires CPU_READY to be set.
1686 mp_startup_common(boolean_t boot
)
1689 uchar_t new_x86_featureset
[BT_SIZEOFMAP(NUM_X86_FEATURES
)];
1690 extern void cpu_event_init_cpu(cpu_t
*);
1693 * We need to get TSC on this proc synced (i.e., any delta
1694 * from cpu0 accounted for) as soon as we can, because many
1695 * many things use gethrtime/pc_gethrestime, including
1696 * interrupts, cmn_err, etc. Before we can do that, we want to
1697 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1700 bzero(new_x86_featureset
, BT_SIZEOFMAP(NUM_X86_FEATURES
));
1701 cpuid_pass1(cp
, new_x86_featureset
);
1703 if (boot
&& get_hwenv() == HW_NATIVE
&&
1704 cpuid_getvendor(CPU
) == X86_VENDOR_Intel
&&
1705 cpuid_getfamily(CPU
) == 6 &&
1706 (cpuid_getmodel(CPU
) == 0x2d || cpuid_getmodel(CPU
) == 0x3e) &&
1707 is_x86_feature(new_x86_featureset
, X86FSET_TSC
)) {
1708 (void) wrmsr(REG_TSC
, 0UL);
1711 /* Let the control CPU continue into tsc_sync_master() */
1712 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1715 if (tsc_gethrtime_enable
)
1720 * Once this was done from assembly, but it's safer here; if
1721 * it blocks, we need to be able to swtch() to and from, and
1722 * since we get here by calling t_pc, we need to do that call
1723 * before swtch() overwrites it.
1725 (void) (*ap_mlsetup
)();
1729 * Program this cpu's PAT
1735 * Set up TSC_AUX to contain the cpuid for this processor
1736 * for the rdtscp instruction.
1738 if (is_x86_feature(x86_featureset
, X86FSET_TSCP
))
1739 (void) wrmsr(MSR_AMD_TSCAUX
, cp
->cpu_id
);
1742 * Initialize this CPU's syscall handlers
1744 init_cpu_syscall(cp
);
1747 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1748 * highest level at which a routine is permitted to block on
1749 * an adaptive mutex (allows for cpu poke interrupt in case
1750 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1751 * device interrupts that may end up in the hat layer issuing cross
1752 * calls before CPU_READY is set.
1754 splx(ipltospl(LOCK_LEVEL
));
1758 * Do a sanity check to make sure this new CPU is a sane thing
1759 * to add to the collection of processors running this system.
1761 * XXX Clearly this needs to get more sophisticated, if x86
1762 * systems start to get built out of heterogenous CPUs; as is
1763 * likely to happen once the number of processors in a configuration
1764 * gets large enough.
1766 if (compare_x86_featureset(x86_featureset
, new_x86_featureset
) ==
1768 cmn_err(CE_CONT
, "cpu%d: featureset\n", cp
->cpu_id
);
1769 print_x86_featureset(new_x86_featureset
);
1770 cmn_err(CE_WARN
, "cpu%d feature mismatch", cp
->cpu_id
);
1774 * There exists a small subset of systems which expose differing
1775 * MWAIT/MONITOR support between CPUs. If MWAIT support is absent from
1776 * the boot CPU, but is found on a later CPU, the system continues to
1777 * operate as if no MWAIT support is available.
1779 * The reverse case, where MWAIT is available on the boot CPU but not
1780 * on a subsequently initialized CPU, is not presently allowed and will
1781 * result in a panic.
1783 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) !=
1784 is_x86_feature(new_x86_featureset
, X86FSET_MWAIT
)) {
1785 if (!is_x86_feature(x86_featureset
, X86FSET_MWAIT
)) {
1786 remove_x86_feature(new_x86_featureset
, X86FSET_MWAIT
);
1788 panic("unsupported mixed cpu mwait support detected");
1793 * We could be more sophisticated here, and just mark the CPU
1794 * as "faulted" but at this point we'll opt for the easier
1795 * answer of dying horribly. Provided the boot cpu is ok,
1796 * the system can be recovered by booting with use_mp set to zero.
1798 if (workaround_errata(cp
) != 0)
1799 panic("critical workaround(s) missing for cpu%d", cp
->cpu_id
);
1802 * We can touch cpu_flags here without acquiring the cpu_lock here
1803 * because the cpu_lock is held by the control CPU which is running
1804 * mp_start_cpu_common().
1805 * Need to clear CPU_QUIESCED flag before calling any function which
1806 * may cause thread context switching, such as kmem_alloc() etc.
1807 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1808 * it's set. So the startup thread may have no chance to switch back
1809 * again if it's switched away with CPU_QUIESCED set.
1811 cp
->cpu_flags
&= ~(CPU_POWEROFF
| CPU_QUIESCED
);
1816 * Setup this processor for XSAVE.
1818 if (fp_save_mech
== FP_XSAVE
) {
1819 xsave_setup_msr(cp
);
1824 cpuid_pass4(cp
, NULL
);
1827 * Correct cpu_idstr and cpu_brandstr on target CPU after
1828 * cpuid_pass1() is done.
1830 (void) cpuid_getidstr(cp
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
1831 (void) cpuid_getbrandstr(cp
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
1833 cp
->cpu_flags
|= CPU_RUNNING
| CPU_READY
| CPU_EXISTS
;
1835 post_startup_cpu_fixups();
1837 cpu_event_init_cpu(cp
);
1840 * Enable preemption here so that contention for any locks acquired
1841 * later in mp_startup_common may be preempted if the thread owning
1842 * those locks is continuously executing on other CPUs (for example,
1843 * this CPU must be preemptible to allow other CPUs to pause it during
1844 * their startup phases). It's safe to enable preemption here because
1845 * the CPU state is pretty-much fully constructed.
1847 curthread
->t_preempt
= 0;
1849 /* The base spl should still be at LOCK LEVEL here */
1850 ASSERT(cp
->cpu_base_spl
== ipltospl(LOCK_LEVEL
));
1851 set_base_spl(); /* Restore the spl to its proper value */
1853 pghw_physid_create(cp
);
1855 * Delegate initialization tasks, which need to access the cpu_lock,
1856 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1857 * during CPU DR operations.
1859 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1860 mp_startup_wait(&procset_master
, cp
->cpu_id
);
1861 pg_cmt_cpu_startup(cp
);
1864 mutex_enter(&cpu_lock
);
1865 cp
->cpu_flags
&= ~CPU_OFFLINE
;
1866 cpu_enable_intr(cp
);
1868 mutex_exit(&cpu_lock
);
1871 /* Enable interrupts */
1875 * Fill out cpu_ucode_info. Update microcode if necessary.
1882 * Set up the CPU module for this CPU. This can't be done
1883 * before this CPU is made CPU_READY, because we may (in
1884 * heterogeneous systems) need to go load another CPU module.
1885 * The act of attempting to load a module may trigger a
1886 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1890 if ((hdl
= cmi_init(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(CPU
),
1891 cmi_ntv_hwcoreid(CPU
), cmi_ntv_hwstrandid(CPU
))) != NULL
) {
1892 if (is_x86_feature(x86_featureset
, X86FSET_MCA
))
1894 cp
->cpu_m
.mcpu_cmi_hdl
= hdl
;
1899 if (boothowto
& RB_DEBUG
)
1903 * Setting the bit in cpu_ready_set must be the last operation in
1904 * processor initialization; the boot CPU will continue to boot once
1905 * it sees this bit set for all active CPUs.
1907 CPUSET_ATOMIC_ADD(cpu_ready_set
, cp
->cpu_id
);
1909 (void) mach_cpu_create_device_node(cp
, NULL
);
1911 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_idstr
);
1912 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_brandstr
);
1913 cmn_err(CE_CONT
, "?cpu%d initialization complete - online\n",
1917 * Now we are done with the startup thread, so free it up.
1920 panic("mp_startup: cannot return");
1925 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1928 mp_startup_boot(void)
1930 mp_startup_common(B_TRUE
);
1934 * Startup function for hotplug CPUs at runtime.
1937 mp_startup_hotplug(void)
1939 mp_startup_common(B_FALSE
);
1943 * Start CPU on user request.
1947 mp_cpu_start(struct cpu
*cp
)
1949 ASSERT(MUTEX_HELD(&cpu_lock
));
1954 * Stop CPU on user request.
1957 mp_cpu_stop(struct cpu
*cp
)
1959 extern int cbe_psm_timer_mode
;
1960 ASSERT(MUTEX_HELD(&cpu_lock
));
1964 * We can't offline vcpu0.
1966 if (cp
->cpu_id
== 0)
1971 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1972 * can't stop it. (This is true only for machines with no TSC.)
1975 if ((cbe_psm_timer_mode
== TIMER_PERIODIC
) && (cp
->cpu_id
== 0))
1982 * Take the specified CPU out of participation in interrupts.
1985 cpu_disable_intr(struct cpu
*cp
)
1987 if (psm_disable_intr(cp
->cpu_id
) != DDI_SUCCESS
)
1990 cp
->cpu_flags
&= ~CPU_ENABLE
;
1995 * Allow the specified CPU to participate in interrupts.
1998 cpu_enable_intr(struct cpu
*cp
)
2000 ASSERT(MUTEX_HELD(&cpu_lock
));
2001 cp
->cpu_flags
|= CPU_ENABLE
;
2002 psm_enable_intr(cp
->cpu_id
);
2006 mp_cpu_faulted_enter(struct cpu
*cp
)
2009 _NOTE(ARGUNUSED(cp
));
2011 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
2016 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
2017 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
2020 cmi_faulted_enter(hdl
);
2027 mp_cpu_faulted_exit(struct cpu
*cp
)
2030 _NOTE(ARGUNUSED(cp
));
2032 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
2037 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
2038 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
2041 cmi_faulted_exit(hdl
);
2048 * The following two routines are used as context operators on threads belonging
2049 * to processes with a private LDT (see sysi86). Due to the rarity of such
2050 * processes, these routines are currently written for best code readability and
2051 * organization rather than speed. We could avoid checking x86_featureset at
2052 * every context switch by installing different context ops, depending on
2053 * x86_featureset, at LDT creation time -- one for each combination of fast
2059 cpu_fast_syscall_disable(void *arg
)
2061 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2062 is_x86_feature(x86_featureset
, X86FSET_SEP
))
2064 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2065 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
2066 cpu_asysc_disable();
2071 cpu_fast_syscall_enable(void *arg
)
2073 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2074 is_x86_feature(x86_featureset
, X86FSET_SEP
))
2076 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2077 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
2082 cpu_sep_enable(void)
2084 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2085 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2087 wrmsr(MSR_INTC_SEP_CS
, (uint64_t)(uintptr_t)KCS_SEL
);
2091 cpu_sep_disable(void)
2093 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2094 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2097 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2098 * the sysenter or sysexit instruction to trigger a #gp fault.
2100 wrmsr(MSR_INTC_SEP_CS
, 0);
2104 cpu_asysc_enable(void)
2106 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2107 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2109 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) |
2110 (uint64_t)(uintptr_t)AMD_EFER_SCE
);
2114 cpu_asysc_disable(void)
2116 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2117 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2120 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2121 * executing syscall or sysret with this bit off will incur a #ud trap.
2123 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) &
2124 ~((uint64_t)(uintptr_t)AMD_EFER_SCE
));