usr/src/uts/intel/sys/debugreg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright (c) 1999 by Sun Microsystems, Inc.
  24  * All rights reserved.
  25  */
  26 /*      Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
  27 /*      Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T   */
  28 /*        All Rights Reserved   */
  29
  30 #ifndef _SYS_DEBUGREG_H
  31 #define _SYS_DEBUGREG_H
  32
  33 #ifdef  __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 /*
  38  * Specify masks for accessing the i386 debug registers.
  39  */
  40
  41 /*
  42  * The debug registers are found in an array (debugreg) in the u block.
  43  * On the i386, there are 4 registers to specify linear addresses.
  44  * dr4 and dr5 are reserved.
  45  */
  46 #define DR_FIRSTADDR    0       /* u.u_debugreg[DR_FIRSTADDR] */
  47 #define DR_LASTADDR     3       /* u.u_debugreg[DR_LASTADDR]  */
  48
  49 /*
  50  * The debug status is found in dr6 after a debug trap.
  51  */
  52 #define DR_STATUS       6       /* u.u_debugreg[DR_STATUS] */
  53 #define DR_TRAP0        0x1     /* Trap from debug register #0 */
  54 #define DR_TRAP1        0x2     /* Trap from debug register #1 */
  55 #define DR_TRAP2        0x4     /* Trap from debug register #2 */
  56 #define DR_TRAP3        0x8     /* Trap from debug register #3 */
  57 #define DR_ICEALSO      0x2000  /* Flag bit reserved for in-circuit-emulator */
  58 #define DR_SINGLESTEP   0x4000  /* Trap resulting from the single-step flag */
  59 #define DR_TASKSWITCH   0x8000  /* Trap resulting from a task-switch */
  60
  61 /*
  62  * dr7 controls the rest of the debug registers.
  63  * use shifts and masks because arrays of fields tend to get aligned.
  64  * For example,
  65  *    dr7 & DR_LOCAL_ENABLE_MASK
  66  *    dr7 >> (DR_LOCAL_ENABLE_SHIFT + r# * DR_ENABLE_SIZE) & 0x1
  67  *    dr7 >> (DR_CONTROL_SHIFT + r# * DR_CONTROL_SIZE) & DR_RW_MASK
  68  * Note that the GLOBAL bits below and always turned off by the kernel.
  69  */
  70 #define DR_CONTROL              7       /* u.u_debugreg[DR_CONTROL] */
  71 #define DR_LOCAL_ENABLE_MASK    0x55    /* Enable all 4 regs for ldt addrs */
  72 #define DR_GLOBAL_ENABLE_MASK   0xAA    /* Enable all 4 regs for gdt addrs */
  73 #define DR_CONTROL_RESERVED     0xFC00  /* Bits reserved by Intel */
  74 #define DR_LOCAL_SLOWDOWN       0x100   /* Slow the pipeline for ldt addrs */
  75 #define DR_GLOBAL_SLOWDOWN      0x200   /* Slow the pipeline for gdt addrs */
  76
  77 #define DR_LOCAL_ENABLE_SHIFT   0       /* Additional shift: local enable  */
  78 #define DR_GLOBAL_ENABLE_SHIFT  1       /* Additional shift: global enable */
  79 #define DR_ENABLE_SIZE          2       /* 2 enable bits per register  */
  80
  81 #define DR_TRAPS        (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)
  82 #define DR_ENABLE0      0x03    /* Local or Global enable of trap 0 */
  83 #define DR_ENABLE1      0x0C    /* Local or Global enable of trap 1 */
  84 #define DR_ENABLE2      0x30    /* Local or Global enable of trap 2 */
  85 #define DR_ENABLE3      0xC0    /* Local or Global enable of trap 3 */
  86
  87 #define DR_CONTROL_SHIFT        16      /* Shift to register control bits */
  88 #define DR_CONTROL_SIZE         4       /* 4 control bits per register */
  89 #define DR_RW_MASK              0x3     /* Two bits specify r/w access */
  90 #define DR_RW_EXECUTE           0x0     /* Settings for the read/write mask */
  91 #define DR_RW_WRITE             0x1
  92 #define DR_RW_IO_RW             0x2     /* I/O space on Pentium and beyond */
  93 #define DR_RW_READ              0x3
  94 #define DR_LEN_MASK             0xC     /* Two bits specify data length */
  95 #define DR_LEN_1                0x0     /* Settings for data length */
  96 #define DR_LEN_2                0x4
  97 #define DR_LEN_4                0xC
  98
  99 #ifdef  __cplusplus
 100 }
 101 #endif
 102
 103 #endif  /* _SYS_DEBUGREG_H */