usr/src/test/util-tests/tests/dis/risc-v/tst.regs.s

   1 /*
   2  * This file and its contents are supplied under the terms of the
   3  * Common Development and Distribution License ("CDDL"), version 1.0.
   4  * You may only use this file in accordance with the terms of version
   5  * 1.0 of the CDDL.
   6  *
   7  * A full copy of the text of the CDDL should have accompanied this
   8  * source.  A copy of the CDDL is also available via the Internet at
   9  * http://www.illumos.org/license/CDDL.
  10  */
  11
  12 /*
  13  * Copyright 2018, Joyent, Inc.
  14  */
  15
  16 /*
  17  * Test that we properly name all registers in their place.
  18  */
  19
  20 .text
  21 .align 16
  22 .globl libdis_test
  23 .type libdis_test, @function
  24 libdis_test:
  25         add     x0, x0, x0
  26         add     ra, ra, ra
  27         add     sp, sp, sp
  28         add     gp, gp, gp
  29         add     tp, tp, tp
  30         add     t0, t0, t0
  31         add     t1, t1, t1
  32         add     t2, t2, t2
  33         add     s0, s0, s0
  34         add     s1, s1, s1
  35         add     a0, a0, a0
  36         add     a1, a1, a1
  37         add     a2, a2, a2
  38         add     a3, a3, a3
  39         add     a4, a4, a4
  40         add     a5, a5, a5
  41         add     a6, a6, a6
  42         add     a7, a7, a7
  43         add     s2, s2, s2
  44         add     s3, s3, s3
  45         add     s4, s4, s4
  46         add     s5, s5, s5
  47         add     s6, s6, s6
  48         add     s7, s7, s7
  49         add     s8, s8, s8
  50         add     s9, s9, s9
  51         add     s10, s10, s10
  52         add     s11, s11, s11
  53         add     t3, t3, t3
  54         add     t4, t4, t4
  55         add     t5, t5, t5
  56         add     t6, t6, t6
  57
  58         add     x0, ra, sp
  59         add     ra, sp, gp
  60         add     sp, gp, tp
  61         add     gp, tp, t0
  62         add     tp, t0, t1
  63         add     t0, t1, t2
  64         add     t1, t2, s0
  65         add     t2, s0, s1
  66         add     s0, s1, a0
  67         add     s1, a0, a1
  68         add     a0, a1, a2
  69         add     a1, a2, a3
  70         add     a2, a3, a4
  71         add     a3, a4, a5
  72         add     a4, a5, a6
  73         add     a5, a6, a7
  74         add     a6, a7, s2
  75         add     a7, s2, s3
  76         add     s2, s3, s4
  77         add     s3, s4, s5
  78         add     s4, s5, s6
  79         add     s5, s6, s7
  80         add     s6, s7, s8
  81         add     s7, s8, s9
  82         add     s8, s9, s10
  83         add     s9, s10, s11
  84         add     s10, s11, t3
  85         add     s11, t3, t4
  86         add     t3, t4, t5
  87         add     t4, t5, t6
  88         add     t5, t6, x0
  89         add     t6, x0, ra
  90 .size libdis_test, [.-libdis_test]