usr/src/uts/common/io/qede/579xx/hsi/mcp/spad_layout.h

   1 /*
   2 * CDDL HEADER START
   3 *
   4 * The contents of this file are subject to the terms of the
   5 * Common Development and Distribution License, v.1,  (the "License").
   6 * You may not use this file except in compliance with the License.
   7 *
   8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9 * or http://opensource.org/licenses/CDDL-1.0.
  10 * See the License for the specific language governing permissions
  11 * and limitations under the License.
  12 *
  13 * When distributing Covered Code, include this CDDL HEADER in each
  14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15 * If applicable, add the following below this CDDL HEADER, with the
  16 * fields enclosed by brackets "[]" replaced with your own identifying
  17 * information: Portions Copyright [yyyy] [name of copyright owner]
  18 *
  19 * CDDL HEADER END
  20 */
  21
  22 /*
  23 * Copyright 2014-2017 Cavium, Inc.
  24 * The contents of this file are subject to the terms of the Common Development
  25 * and Distribution License, v.1,  (the "License").
  26
  27 * You may not use this file except in compliance with the License.
  28
  29 * You can obtain a copy of the License at available
  30 * at http://opensource.org/licenses/CDDL-1.0
  31
  32 * See the License for the specific language governing permissions and
  33 * limitations under the License.
  34 */
  35
  36 /****************************************************************************
  37  * Name:        spad_layout.h
  38  *
  39  * Description: Global definitions
  40  *
  41  * Created:     01/09/2013
  42  *
  43  ****************************************************************************/
  44 /*
  45  *          Spad Layout                                NVM CFG                         MCP public
  46  *==========================================================================================================
  47  *     MCP_REG_SCRATCH                         REG_RD(MISC_REG_GEN_PURP_CR0)       REG_RD(MISC_REG_SHARED_MEM_ADDR)
  48  *    +------------------+                      +-------------------------+        +-------------------+
  49  *    |  Num Sections(4B)|Currently 4           |   Num Sections(4B)      |        |   Num Sections(4B)|Currently 6
  50  *    +------------------+                      +-------------------------+        +-------------------+
  51  *    | Offsize(Trace)   |4B -+             +-- | Offset(NVM_CFG1)        |        | Offsize(drv_mb)   |
  52  *  +-| Offsize(NVM_CFG) |4B  |             |   | (Size is fixed)         |        | Offsize(mfw_mb)   |
  53  *+-|-| Offsize(Public)  |4B  |             +-> +-------------------------+        | Offsize(global)   |
  54  *| | | Offsize(Private) |4B  |                 |                         |        | Offsize(path)     |
  55  *| | +------------------+ <--+                 | nvm_cfg1_glob           |        | Offsize(port)     |
  56  *| | |                  |                      +-------------------------+        | Offsize(func)     |
  57  *| | |      Trace       |                      | nvm_cfg1_path 0         |        +-------------------+
  58  *| +>+------------------+                      | nvm_cfg1_path 1         |        | drv_mb   PF0/2/4..|8 Funcs of engine0
  59  *|   |                  |                      +-------------------------+        | drv_mb   PF1/3/5..|8 Funcs of engine1
  60  *|   |     NVM_CFG      |                      | nvm_cfg1_port 0         |        +-------------------+
  61  *+-> +------------------+                      |            ....         |        | mfw_mb   PF0/2/4..|8 Funcs of engine0
  62  *    |                  |                      | nvm_cfg1_port 3         |        | mfw_mb   PF1/3/5..|8 Funcs of engine1
  63  *    |   Public Data    |                      +-------------------------+        +-------------------+
  64  *    +------------------+   8 Funcs of Engine 0| nvm_cfg1_func PF0/2/4/..|        |                   |
  65  *    |                  |   8 Funcs of Engine 1| nvm_cfg1_func PF1/3/5/..|        | public_global     |
  66  *    |   Private Data   |                      +-------------------------+        +-------------------+
  67  *    +------------------+                                                         | public_path 0     |
  68  *    |       Code       |                                                         | public_path 1     |
  69  *    |   Static Area    |                                                         +-------------------+
  70  *    +---            ---+                                                         | public_port 0     |
  71  *    |       Code       |                                                         |        ....       |
  72  *    |      PIM Area    |                                                         | public_port 3     |
  73  *    +------------------+                                                         +-------------------+
  74  *                                                                                 | public_func 0/2/4.|8 Funcs of engine0
  75  *                                                                                 | public_func 1/3/5.|8 Funcs of engine1
  76  *                                                                                 +-------------------+
  77 */
  78 #ifndef SPAD_LAYOUT_H
  79 #define SPAD_LAYOUT_H
  80
  81 #ifndef MDUMP_PARSE_TOOL
  82
  83 #define PORT_0          0
  84 #define PORT_1          1
  85 #define PORT_2          2
  86 #define PORT_3          3
  87
  88 #include "mcp_public.h"
  89 #include "mfw_hsi.h"
  90 #include "nvm_cfg.h"
  91
  92 #ifdef MFW
  93 #include "mcp_private.h"
  94 #endif
  95
  96 extern struct spad_layout g_spad;
  97
  98 /* TBD - Consider renaming to MCP_STATIC_SPAD_SIZE, since the real size includes another 64kb */
  99 #define MCP_SPAD_SIZE                       0x00028000  /* 160 KB */
 100
 101 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
 102 #endif /* MDUMP_PARSE_TOOL */
 103
 104 #define TO_OFFSIZE(_offset, _size) \
 105     (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
 106           (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
 107
 108 enum spad_sections {
 109         SPAD_SECTION_TRACE,
 110         SPAD_SECTION_NVM_CFG,
 111         SPAD_SECTION_PUBLIC,
 112         SPAD_SECTION_PRIVATE,
 113         SPAD_SECTION_MAX
 114 };
 115
 116 #ifndef MDUMP_PARSE_TOOL
 117 struct spad_layout {
 118         struct nvm_cfg nvm_cfg;
 119         struct mcp_public_data public_data;
 120 #ifdef MFW                      /* Drivers will not be compiled with this flag. */
 121         /* Linux should remove this appearance at all. */
 122         struct mcp_private_data private_data;
 123 #endif
 124 };
 125
 126 #endif /* MDUMP_PARSE_TOOL */
 127
 128 #define MCP_TRACE_SIZE          2048    /* 2kb */
 129 #define STRUCT_OFFSET(f)    (STATIC_INIT_BASE + __builtin_offsetof(struct static_init, f))
 130
 131 /* This section is located at a fixed location in the beginning of the scratchpad,
 132  * to ensure that the MCP trace is not run over during MFW upgrade.
 133  * All the rest of data has a floating location which differs from version to version,
 134  * and is pointed by the mcp_meta_data below.
 135  * Moreover, the spad_layout section is part of the MFW firmware, and is loaded with it
 136  * from nvram in order to clear this portion.
 137  */
 138 struct static_init {
 139         u32 num_sections;                                               /* 0xe20000 */
 140         offsize_t sections[SPAD_SECTION_MAX];                           /* 0xe20004 */
 141 #define SECTION(_sec_) *((offsize_t*)(STRUCT_OFFSET(sections[_sec_])))
 142
 143         struct mcp_trace trace;                                         /* 0xe20014 */
 144 #define MCP_TRACE_P ((struct mcp_trace*)(STRUCT_OFFSET(trace)))
 145         u8 trace_buffer[MCP_TRACE_SIZE];                                /* 0xe20030 */
 146 #define MCP_TRACE_BUF ((u8*)(STRUCT_OFFSET(trace_buffer)))
 147         /* running_mfw has the same definition as in nvm_map.h.
 148          * This bit indicate both the running dir, and the running bundle.
 149          * It is set once when the LIM is loaded.
 150          */
 151         u32 running_mfw;                                                /* 0xe20830 */
 152 #define RUNNING_MFW *((u32*)(STRUCT_OFFSET(running_mfw)))
 153         u32 build_time;                                                 /* 0xe20834 */
 154 #define MFW_BUILD_TIME *((u32*)(STRUCT_OFFSET(build_time)))
 155         u32 reset_type;                                                 /* 0xe20838 */
 156 #define RESET_TYPE *((u32*)(STRUCT_OFFSET(reset_type)))
 157         u32 mfw_secure_mode;                                            /* 0xe2083c */
 158 #define MFW_SECURE_MODE *((u32*)(STRUCT_OFFSET(mfw_secure_mode)))
 159         u16 pme_status_pf_bitmap;                                       /* 0xe20840 */
 160 #define PME_STATUS_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_status_pf_bitmap)))
 161         u16 pme_enable_pf_bitmap;
 162 #define PME_ENABLE_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_enable_pf_bitmap)))
 163         u32 mim_nvm_addr;                                               /* 0xe20844 */
 164         u32 mim_start_addr;                                             /* 0xe20848 */
 165         u32 ah_pcie_link_params; /* 0xe20850 Stores PCIe link configuration at start, so they can be used later also for Hot-Reset, without the need to re-reading them from nvm cfg. */
 166 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK     (0x000000ff)
 167 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT    (0)
 168 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK     (0x0000ff00)
 169 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT    (8)
 170 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK      (0x00ff0000)
 171 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT     (16)
 172 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK       (0xff000000)
 173 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT      (24)
 174 #define AH_PCIE_LINK_PARAMS *((u32*)(STRUCT_OFFSET(ah_pcie_link_params)))
 175
 176         u32 flags;                                                      /* 0xe20850 */
 177 #define M_GLOB_FLAGS            *((u32*)(STRUCT_OFFSET(flags)))
 178 #define FLAGS_VAUX_REQUIRED             (1 << 0)
 179 #define FLAGS_WAIT_AVS_READY            (1 << 1)
 180 #define FLAGS_FAILURE_ISSUED            (1 << 2)
 181 #define FLAGS_FAILURE_DETECTED          (1 << 3)
 182 #define FLAGS_VAUX                      (1 << 4)
 183 #define FLAGS_PERST_ASSERT_OCCURED      (1 << 5)
 184 #define FLAGS_HOT_RESET_STEP2           (1 << 6)
 185 #define FLAGS_MSIX_SYNC_ALLOWED         (1 << 7)
 186 #define FLAGS_PROGRAM_PCI_COMPLETED     (1 << 8)
 187 #define FLAGS_SMBUS_AUX_MODE            (1 << 9)
 188 #define FLAGS_PEND_SMBUS_VMAIN_TO_AUX   (1 << 10)
 189 #define FLAGS_NVM_CFG_EFUSE_FAILURE     (1 << 11)
 190 #define FLAGS_POWER_TRANSITION          (1 << 12)
 191 #define FLAGS_OS_DRV_LOADED             (1 << 29)
 192 #define FLAGS_OVER_TEMP_OCCUR           (1 << 30)
 193 #define FLAGS_FAN_FAIL_OCCUR            (1 << 31)
 194         u32 rsrv_persist[4]; /* Persist reserved for MFW upgrades */    /* 0xe20854 */
 195
 196 };
 197
 198 #ifndef MDUMP_PARSE_TOOL
 199 #define NVM_CFG1(x)             g_spad.nvm_cfg.cfg1.x
 200 #define NVM_GLOB(x)             NVM_CFG1(glob).x
 201 #define NVM_GLOB_VAL(n, m, o)   ((NVM_GLOB(n) & m) >> o)
 202 #endif /* MDUMP_PARSE_TOOL */
 203
 204 #endif                          /* SPAD_LAYOUT_H */