usr/src/uts/common/io/qede/579xx/drivers/ecore/hsi_repository/fcoe_common.h

   1 /*
   2 * CDDL HEADER START
   3 *
   4 * The contents of this file are subject to the terms of the
   5 * Common Development and Distribution License, v.1,  (the "License").
   6 * You may not use this file except in compliance with the License.
   7 *
   8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9 * or http://opensource.org/licenses/CDDL-1.0.
  10 * See the License for the specific language governing permissions
  11 * and limitations under the License.
  12 *
  13 * When distributing Covered Code, include this CDDL HEADER in each
  14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15 * If applicable, add the following below this CDDL HEADER, with the
  16 * fields enclosed by brackets "[]" replaced with your own identifying
  17 * information: Portions Copyright [yyyy] [name of copyright owner]
  18 *
  19 * CDDL HEADER END
  20 */
  21
  22 /*
  23 * Copyright 2014-2017 Cavium, Inc.
  24 * The contents of this file are subject to the terms of the Common Development
  25 * and Distribution License, v.1,  (the "License").
  26
  27 * You may not use this file except in compliance with the License.
  28
  29 * You can obtain a copy of the License at available
  30 * at http://opensource.org/licenses/CDDL-1.0
  31
  32 * See the License for the specific language governing permissions and
  33 * limitations under the License.
  34 */
  35
  36 #ifndef __FCOE_COMMON__
  37 #define __FCOE_COMMON__
  38 /*********************/
  39 /* FCOE FW CONSTANTS */
  40 /*********************/
  41
  42 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN   12
  43
  44
  45
  46
  47
  48 /*
  49  * fields coppied from ABTSrsp pckt
  50  */
  51 struct fcoe_abts_pkt
  52 {
  53         __le32 abts_rsp_fc_payload_lo /* Abts flow: last 32 bits of fcPayload, out of 96 */;
  54         __le16 abts_rsp_rx_id /* Abts flow: rxId parameter of the abts packet */;
  55         u8 abts_rsp_rctl /* Abts flow: rctl parameter of the abts packet */;
  56         u8 reserved2;
  57 };
  58
  59
  60 /*
  61  * FCoE additional WQE (Sq/ XferQ) information
  62  */
  63 union fcoe_additional_info_union
  64 {
  65         __le32 previous_tid /* Previous tid. Used for Send XFER WQEs in Multiple continuation mode - Target only. */;
  66         __le32 parent_tid /* Parent tid. Used for write tasks in a continuation mode - Target only */;
  67         __le32 burst_length /* The desired burst length. */;
  68         __le32 seq_rec_updated_offset /* The updated offset in SGL - Used in sequence recovery */;
  69 };
  70
  71
  72 /*
  73  * Cached data sges
  74  */
  75 struct fcoe_exp_ro
  76 {
  77         __le32 data_offset /* data-offset */;
  78         __le32 reserved /* High data-offset */;
  79 };
  80
  81 /*
  82  * Union of Cleanup address \ expected relative offsets
  83  */
  84 union fcoe_cleanup_addr_exp_ro_union
  85 {
  86         struct regpair abts_rsp_fc_payload_hi /* Abts flow: first 64 bits of fcPayload, out of 96 */;
  87         struct fcoe_exp_ro exp_ro /* Expected relative offsets */;
  88 };
  89
  90
  91 /*
  92  * FCoE Ramrod Command IDs
  93  */
  94 enum fcoe_completion_status
  95 {
  96         FCOE_COMPLETION_STATUS_SUCCESS /* FCoE ramrod completed successfully */,
  97         FCOE_COMPLETION_STATUS_FCOE_VER_ERR /* Wrong FCoE version */,
  98         FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR /* src_mac_arr for the current physical port is full- allocation failed */,
  99         MAX_FCOE_COMPLETION_STATUS
 100 };
 101
 102
 103 /*
 104  * FC address (SID/DID) network presentation
 105  */
 106 struct fc_addr_nw
 107 {
 108         u8 addr_lo /* First byte of the SID/DID address that comes/goes from/to the NW (for example if SID is 11:22:33 - this is 0x11) */;
 109         u8 addr_mid;
 110         u8 addr_hi;
 111 };
 112
 113 /*
 114  * FCoE connection offload
 115  */
 116 struct fcoe_conn_offload_ramrod_data
 117 {
 118         struct regpair sq_pbl_addr /* SQ Pbl base address */;
 119         struct regpair sq_curr_page_addr /* SQ current page address */;
 120         struct regpair sq_next_page_addr /* SQ next page address */;
 121         struct regpair xferq_pbl_addr /* XFERQ Pbl base address */;
 122         struct regpair xferq_curr_page_addr /* XFERQ current page address */;
 123         struct regpair xferq_next_page_addr /* XFERQ next page address */;
 124         struct regpair respq_pbl_addr /* RESPQ Pbl base address */;
 125         struct regpair respq_curr_page_addr /* RESPQ current page address */;
 126         struct regpair respq_next_page_addr /* RESPQ next page address */;
 127         __le16 dst_mac_addr_lo /* First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */;
 128         __le16 dst_mac_addr_mid;
 129         __le16 dst_mac_addr_hi;
 130         __le16 src_mac_addr_lo /* Source MAC address in NW order - First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */;
 131         __le16 src_mac_addr_mid;
 132         __le16 src_mac_addr_hi;
 133         __le16 tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */;
 134         __le16 e_d_tov_timer_val /* E_D_TOV timeout value in resolution of 1 msec */;
 135         __le16 rx_max_fc_pay_len /* Maximum acceptable FC payload size supported by us */;
 136         __le16 vlan_tag;
 137 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK              0xFFF /* Vlan id */
 138 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT             0
 139 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK                  0x1 /* Canonical format indicator */
 140 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT                 12
 141 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK             0x7 /* Vlan priority */
 142 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT            13
 143         __le16 physical_q0 /* Physical QM queue to be linked to logical queue 0 (fastPath queue) */;
 144         __le16 rec_rr_tov_timer_val /* REC_TOV timeout value in resolution of 1 msec  */;
 145         struct fc_addr_nw s_id /* Source ID in NW order, received during FLOGI */;
 146         u8 max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */;
 147         struct fc_addr_nw d_id /* Destination ID in NW order, received after inquiry of the fabric network */;
 148         u8 flags;
 149 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK  0x1 /* Continuously increasing SEQ_CNT indication, received during PLOGI */
 150 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
 151 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK           0x1 /* Confirmation request supported */
 152 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT          1
 153 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK          0x1 /* REC allowed */
 154 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT         2
 155 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK          0x1 /* Does inner vlan exist */
 156 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT         3
 157 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK                 0x3 /* indication for conn mode: 0=Initiator, 1=Target, 2=Both Initiator and Traget */
 158 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT                4
 159 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK            0x3
 160 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT           6
 161         __le16 conn_id /* Drivers connection ID. Should be sent in EQs to speed-up drivers access to connection data. */;
 162         u8 def_q_idx /* Default queue number to be used for unsolicited traffic */;
 163         u8 reserved[5];
 164 };
 165
 166
 167 /*
 168  * FCoE terminate connection request
 169  */
 170 struct fcoe_conn_terminate_ramrod_data
 171 {
 172         struct regpair terminate_params_addr /* Terminate params ptr */;
 173 };
 174
 175
 176 /*
 177  * Data sgl
 178  */
 179 struct fcoe_slow_sgl_ctx
 180 {
 181         struct regpair base_sgl_addr /* Address of first SGE in SGL */;
 182         __le16 curr_sge_off /* Offset in current BD (in bytes) */;
 183         __le16 remainder_num_sges /* Number of BDs */;
 184         __le16 curr_sgl_index /* Index of current SGE */;
 185         __le16 reserved;
 186 };
 187
 188 /*
 189  * Union of DIX SGL \ cached DIX sges
 190  */
 191 union fcoe_dix_desc_ctx
 192 {
 193         struct fcoe_slow_sgl_ctx dix_sgl /* DIX slow-SGL data base */;
 194         struct scsi_sge cached_dix_sge /* Cached DIX sge */;
 195 };
 196
 197
 198
 199 /*
 200  * Data sgl
 201  */
 202 struct fcoe_fast_sgl_ctx
 203 {
 204         struct regpair sgl_start_addr /* Current sge address */;
 205         __le32 sgl_byte_offset /* Byte offset from the beginning of the first page in the SGL. In case SGL starts in the middle of page then driver should init this value with the start offset */;
 206         __le16 task_reuse_cnt /* The reuse count for that task. Wrap ion 4K value. */;
 207         __le16 init_offset_in_first_sge /* offset from the beginning of the first page in the SGL, never changed by FW */;
 208 };
 209
 210
 211 /*
 212  * FCP CMD payload
 213  */
 214 struct fcoe_fcp_cmd_payload
 215 {
 216         __le32 opaque[8] /* The FCP_CMD payload */;
 217 };
 218
 219
 220 /*
 221  * FCP RSP payload
 222  */
 223 struct fcoe_fcp_rsp_payload
 224 {
 225         __le32 opaque[6] /* The FCP_RSP payload */;
 226 };
 227
 228
 229 /*
 230  * FCP RSP payload
 231  */
 232 struct fcoe_fcp_xfer_payload
 233 {
 234         __le32 opaque[3] /* The FCP_XFER payload */;
 235 };
 236
 237
 238 /*
 239  * FCoE firmware function init
 240  */
 241 struct fcoe_init_func_ramrod_data
 242 {
 243         struct scsi_init_func_params func_params /* Common SCSI init params passed by driver to FW in function init ramrod */;
 244         struct scsi_init_func_queues q_params /* SCSI RQ/CQ/CMDQ firmware function init parameters */;
 245         __le16 mtu /* Max transmission unit */;
 246         __le16 sq_num_pages_in_pbl /* Number of pages at Send Queue */;
 247         __le32 reserved;
 248 };
 249
 250
 251 /*
 252  * FCoE: Mode of the connection: Target or Initiator or both
 253  */
 254 enum fcoe_mode_type
 255 {
 256         FCOE_INITIATOR_MODE=0x0,
 257         FCOE_TARGET_MODE=0x1,
 258         FCOE_BOTH_OR_NOT_CHOSEN=0x3,
 259         MAX_FCOE_MODE_TYPE
 260 };
 261
 262
 263 /*
 264  * Per PF FCoE receive path statistics - tStorm RAM structure
 265  */
 266 struct fcoe_rx_stat
 267 {
 268         struct regpair fcoe_rx_byte_cnt /* Number of FCoE bytes that were received */;
 269         struct regpair fcoe_rx_data_pkt_cnt /* Number of FCoE FCP DATA packets that were received */;
 270         struct regpair fcoe_rx_xfer_pkt_cnt /* Number of FCoE FCP XFER RDY packets that were received */;
 271         struct regpair fcoe_rx_other_pkt_cnt /* Number of FCoE packets which are not DATA/XFER_RDY that were received */;
 272         __le32 fcoe_silent_drop_pkt_cmdq_full_cnt /* Number of packets that were silently dropped since CMDQ was full */;
 273         __le32 fcoe_silent_drop_pkt_rq_full_cnt /* Number of packets that were silently dropped since RQ (BDQ) was full */;
 274         __le32 fcoe_silent_drop_pkt_crc_error_cnt /* Number of packets that were silently dropped due to FC CRC error */;
 275         __le32 fcoe_silent_drop_pkt_task_invalid_cnt /* Number of packets that were silently dropped since task was not valid */;
 276         __le32 fcoe_silent_drop_total_pkt_cnt /* Number of FCoE packets that were silently dropped */;
 277         __le32 rsrv;
 278 };
 279
 280
 281
 282 /*
 283  * FCoe statistics request
 284  */
 285 struct fcoe_stat_ramrod_data
 286 {
 287         struct regpair stat_params_addr /* Statistics host address */;
 288 };
 289
 290
 291 /*
 292  * The fcoe storm task context protection-information of Ystorm
 293  */
 294 struct protection_info_ctx
 295 {
 296         __le16 flags;
 297 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK        0x3 /* 0=none, 1=DIF, 2=DIX */
 298 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT       0
 299 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK           0x1 /* 0=no, 1=yes */
 300 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT          2
 301 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK  0x1 /* 0=no, 1=yes */
 302 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
 303 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK     0xF /* Protection log interval (9=512 10=1024  11=2048 12=4096 13=8192) */
 304 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT    4
 305 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK  0x1 /* 0=no, 1=yes */
 306 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
 307 #define PROTECTION_INFO_CTX_RESERVED0_MASK             0x7F
 308 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT            9
 309         u8 dix_block_size /* Source protection data size */;
 310         u8 dst_size /* Destination protection data size */;
 311 };
 312
 313 /*
 314  * The fcoe storm task context protection-information of Ystorm
 315  */
 316 union protection_info_union_ctx
 317 {
 318         struct protection_info_ctx info;
 319         __le32 value /* If and only if this field is not 0 then protection is set */;
 320 };
 321
 322 /*
 323  * FCP RSP payload
 324  */
 325 struct fcp_rsp_payload_padded
 326 {
 327         struct fcoe_fcp_rsp_payload rsp_payload /* The FCP_RSP payload */;
 328         __le32 reserved[2];
 329 };
 330
 331 /*
 332  * FCP RSP payload
 333  */
 334 struct fcp_xfer_payload_padded
 335 {
 336         struct fcoe_fcp_xfer_payload xfer_payload /* The FCP_XFER payload */;
 337         __le32 reserved[5];
 338 };
 339
 340 /*
 341  * Task params
 342  */
 343 struct fcoe_tx_data_params
 344 {
 345         __le32 data_offset /* Data offset */;
 346         __le32 offset_in_io /* For sequence cleanup */;
 347         u8 flags;
 348 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK  0x1 /* Should we send offset in IO */
 349 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
 350 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK           0x1 /* Should the PBF drop this data */
 351 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT          1
 352 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK       0x1 /* Indication if the task after seqqence recovery flow */
 353 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT      2
 354 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK           0x1F
 355 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT          3
 356         u8 dif_residual /* Residual from protection interval */;
 357         __le16 seq_cnt /* Sequence counter */;
 358         __le16 single_sge_saved_offset /* Saved SGE length for single SGE case */;
 359         __le16 next_dif_offset /* Tracking next DIF offset in FC payload */;
 360         __le16 seq_id /* Sequence ID (Set [saved] upon seq_cnt==0 (start of sequence) and used throughout sequence) */;
 361         __le16 reserved3;
 362 };
 363
 364 /*
 365  * Middle path parameters: FC header fields provided by the driver
 366  */
 367 struct fcoe_tx_mid_path_params
 368 {
 369         __le32 parameter;
 370         u8 r_ctl;
 371         u8 type;
 372         u8 cs_ctl;
 373         u8 df_ctl;
 374         __le16 rx_id;
 375         __le16 ox_id;
 376 };
 377
 378 /*
 379  * Task params
 380  */
 381 struct fcoe_tx_params
 382 {
 383         struct fcoe_tx_data_params data /* Data offset */;
 384         struct fcoe_tx_mid_path_params mid_path;
 385 };
 386
 387 /*
 388  * Union of FCP CMD payload \ TX params \ ABTS \ Cleanup
 389  */
 390 union fcoe_tx_info_union_ctx
 391 {
 392         struct fcoe_fcp_cmd_payload fcp_cmd_payload /* FCP CMD payload */;
 393         struct fcp_rsp_payload_padded fcp_rsp_payload /* FCP RSP payload */;
 394         struct fcp_xfer_payload_padded fcp_xfer_payload /* FCP XFER payload */;
 395         struct fcoe_tx_params tx_params /* Task TX params */;
 396 };
 397
 398 /*
 399  * The fcoe storm task context of Ystorm
 400  */
 401 struct ystorm_fcoe_task_st_ctx
 402 {
 403         u8 task_type /* Task type. use enum fcoe_task_type  */;
 404         u8 sgl_mode;
 405 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK  0x1 /* use enum scsi_sgl_mode (use enum scsi_sgl_mode) */
 406 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
 407 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK         0x7F
 408 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT        1
 409         u8 cached_dix_sge /* Dix sge is cached on task context */;
 410         u8 expect_first_xfer /* Will let Ystorm know when it should initialize fcp_cmd_payload_params_union.params */;
 411         __le32 num_pbf_zero_write /* The amount of bytes that PBF should dummy write - Relevant for protection only. */;
 412         union protection_info_union_ctx protection_info_union /* Protection information */;
 413         __le32 data_2_trns_rem /* Entire SGL-buffer remainder */;
 414         struct scsi_sgl_params sgl_params;
 415         u8 reserved1[12];
 416         union fcoe_tx_info_union_ctx tx_info_union /* Union of FCP CMD payload / TX params / ABTS / Cleanup */;
 417         union fcoe_dix_desc_ctx dix_desc /* Union of DIX SGL / cached DIX sges */;
 418         struct scsi_cached_sges data_desc /* Data cached SGEs */;
 419         __le16 ox_id /* OX-ID. Used in Target mode only */;
 420         __le16 rx_id /* RX-ID. Used in Target mode only */;
 421         __le32 task_rety_identifier /* Parameter field of the FCP CMDs FC header */;
 422         u8 reserved2[8];
 423 };
 424
 425 struct e4_ystorm_fcoe_task_ag_ctx
 426 {
 427         u8 byte0 /* cdu_validation */;
 428         u8 byte1 /* state */;
 429         __le16 word0 /* icid */;
 430         u8 flags0;
 431 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK     0xF /* connection_type */
 432 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT    0
 433 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK        0x1 /* exist_in_qm0 */
 434 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT       4
 435 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK        0x1 /* exist_in_qm1 */
 436 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT       5
 437 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK        0x1 /* bit2 */
 438 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT       6
 439 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK        0x1 /* bit3 */
 440 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT       7
 441         u8 flags1;
 442 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK         0x3 /* cf0 */
 443 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT        0
 444 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK         0x3 /* cf1 */
 445 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT        2
 446 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK  0x3 /* cf2special */
 447 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
 448 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK       0x1 /* cf0en */
 449 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT      6
 450 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK       0x1 /* cf1en */
 451 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT      7
 452         u8 flags2;
 453 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK        0x1 /* bit4 */
 454 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT       0
 455 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK     0x1 /* rule0en */
 456 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT    1
 457 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK     0x1 /* rule1en */
 458 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT    2
 459 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK     0x1 /* rule2en */
 460 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT    3
 461 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK     0x1 /* rule3en */
 462 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT    4
 463 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK     0x1 /* rule4en */
 464 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT    5
 465 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK     0x1 /* rule5en */
 466 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT    6
 467 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK     0x1 /* rule6en */
 468 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT    7
 469         u8 byte2 /* byte2 */;
 470         __le32 reg0 /* reg0 */;
 471         u8 byte3 /* byte3 */;
 472         u8 byte4 /* byte4 */;
 473         __le16 rx_id /* word1 */;
 474         __le16 word2 /* word2 */;
 475         __le16 word3 /* word3 */;
 476         __le16 word4 /* word4 */;
 477         __le16 word5 /* word5 */;
 478         __le32 reg1 /* reg1 */;
 479         __le32 reg2 /* reg2 */;
 480 };
 481
 482 struct e4_tstorm_fcoe_task_ag_ctx
 483 {
 484         u8 reserved /* cdu_validation */;
 485         u8 byte1 /* state */;
 486         __le16 icid /* icid */;
 487         u8 flags0;
 488 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK     0xF /* connection_type */
 489 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT    0
 490 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
 491 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT       4
 492 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK                0x1 /* exist_in_qm1 */
 493 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT               5
 494 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK     0x1 /* bit2 */
 495 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT    6
 496 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK               0x1 /* bit3 */
 497 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT              7
 498         u8 flags1;
 499 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK        0x1 /* bit4 */
 500 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT       0
 501 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK                0x1 /* bit5 */
 502 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT               1
 503 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK       0x3 /* timer0cf */
 504 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT      2
 505 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK           0x3 /* timer1cf */
 506 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT          4
 507 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK                 0x3 /* timer2cf */
 508 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT                6
 509         u8 flags2;
 510 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK      0x3 /* timer_stop_all */
 511 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT     0
 512 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK       0x3 /* cf4 */
 513 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT      2
 514 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK         0x3 /* cf5 */
 515 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT        4
 516 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK     0x3 /* cf6 */
 517 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT    6
 518         u8 flags3;
 519 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK       0x3 /* cf7 */
 520 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT      0
 521 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK    0x1 /* cf0en */
 522 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT   2
 523 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK        0x1 /* cf1en */
 524 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT       3
 525 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK               0x1 /* cf2en */
 526 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT              4
 527 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK   0x1 /* cf3en */
 528 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT  5
 529 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK    0x1 /* cf4en */
 530 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT   6
 531 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK      0x1 /* cf5en */
 532 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT     7
 533         u8 flags4;
 534 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK  0x1 /* cf6en */
 535 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
 536 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK    0x1 /* cf7en */
 537 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT   1
 538 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK             0x1 /* rule0en */
 539 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT            2
 540 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK             0x1 /* rule1en */
 541 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT            3
 542 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK             0x1 /* rule2en */
 543 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT            4
 544 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK             0x1 /* rule3en */
 545 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT            5
 546 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK             0x1 /* rule4en */
 547 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT            6
 548 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK             0x1 /* rule5en */
 549 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT            7
 550         u8 cleanup_state /* byte2 */;
 551         __le16 last_sent_tid /* word1 */;
 552         __le32 rec_rr_tov_exp_timeout /* reg0 */;
 553         u8 byte3 /* byte3 */;
 554         u8 byte4 /* byte4 */;
 555         __le16 word2 /* word2 */;
 556         __le16 word3 /* word3 */;
 557         __le16 word4 /* word4 */;
 558         __le32 data_offset_end_of_seq /* reg1 */;
 559         __le32 data_offset_next /* reg2 */;
 560 };
 561
 562 /*
 563  * FW read- write (modifyable) part The fcoe task storm context of Tstorm
 564  */
 565 struct fcoe_tstorm_fcoe_task_st_ctx_read_write
 566 {
 567         union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union /* Union of Cleanup address / expected relative offsets */;
 568         __le16 flags;
 569 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK       0x1 /* Rx SGL type. use enum scsi_sgl_mode  (use enum scsi_sgl_mode) */
 570 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT      0
 571 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK   0x1 /* Expected first frame flag */
 572 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT  1
 573 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK        0x1 /* Sequence active */
 574 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT       2
 575 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK       0x1 /* Sequence timeout for an active Sequence */
 576 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT      3
 577 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK  0x1 /* Set by Data-in flow. Indicate that this exchange contains a single FCP DATA packet */
 578 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
 579 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK   0x1 /* The status of the current out of order received Sequence */
 580 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT  5
 581 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK        0x3 /* number of additional CQE that will be produced for this task completion */
 582 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT       6
 583 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK             0xFF
 584 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT            8
 585         __le16 seq_cnt /* Sequence counter */;
 586         u8 seq_id /* Sequence id */;
 587         u8 ooo_rx_seq_id /* The last out of order received SEQ_ID */;
 588         __le16 rx_id /* RX_ID of the exchange - should match each packet expect for the first */;
 589         struct fcoe_abts_pkt abts_data /* The last out of order received SEQ_CNT */;
 590         __le32 e_d_tov_exp_timeout_val /* E_D_TOV timer val (in msec) */;
 591         __le16 ooo_rx_seq_cnt /* The last out of order received SEQ_CNT */;
 592         __le16 reserved1;
 593 };
 594
 595 /*
 596  * FW read only part The fcoe task storm context of Tstorm
 597  */
 598 struct fcoe_tstorm_fcoe_task_st_ctx_read_only
 599 {
 600         u8 task_type /* Task type. use enum fcoe_task_type */;
 601         u8 dev_type /* Device type (disk or tape). use enum fcoe_device_type */;
 602         u8 conf_supported /* Confirmation supported indication */;
 603         u8 glbl_q_num /* Global RQ/CQ num to be used for sense data placement/completion */;
 604         __le32 cid /* CID which that tasks associated to */;
 605         __le32 fcp_cmd_trns_size /* IO size as reflected in FCP CMD */;
 606         __le32 rsrv;
 607 };
 608
 609 /*
 610  * The fcoe task storm context of Tstorm
 611  */
 612 struct tstorm_fcoe_task_st_ctx
 613 {
 614         struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write /* FW read- write (modifyable) part The fcoe task storm context of Tstorm */;
 615         struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only /* FW read only part The fcoe task storm context of Tstorm */;
 616 };
 617
 618 struct e4_mstorm_fcoe_task_ag_ctx
 619 {
 620         u8 byte0 /* cdu_validation */;
 621         u8 byte1 /* state */;
 622         __le16 icid /* icid */;
 623         u8 flags0;
 624 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK    0xF /* connection_type */
 625 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT   0
 626 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
 627 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT      4
 628 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK         0x1 /* exist_in_qm1 */
 629 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT        5
 630 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK               0x1 /* bit2 */
 631 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT              6
 632 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK               0x1 /* bit3 */
 633 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT              7
 634         u8 flags1;
 635 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK      0x3 /* cf0 */
 636 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT     0
 637 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK                0x3 /* cf1 */
 638 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT               2
 639 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK                0x3 /* cf2 */
 640 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT               4
 641 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK   0x1 /* cf0en */
 642 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT  6
 643 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
 644 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT             7
 645         u8 flags2;
 646 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
 647 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT             0
 648 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
 649 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT           1
 650 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
 651 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT           2
 652 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
 653 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT           3
 654 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
 655 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT           4
 656 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
 657 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT           5
 658 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK  0x1 /* rule5en */
 659 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
 660 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
 661 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT           7
 662         u8 cleanup_state /* byte2 */;
 663         __le32 received_bytes /* reg0 */;
 664         u8 byte3 /* byte3 */;
 665         u8 glbl_q_num /* byte4 */;
 666         __le16 word1 /* word1 */;
 667         __le16 tid_to_xfer /* word2 */;
 668         __le16 word3 /* word3 */;
 669         __le16 word4 /* word4 */;
 670         __le16 word5 /* word5 */;
 671         __le32 expected_bytes /* reg1 */;
 672         __le32 reg2 /* reg2 */;
 673 };
 674
 675 /*
 676  * The fcoe task storm context of Mstorm
 677  */
 678 struct mstorm_fcoe_task_st_ctx
 679 {
 680         struct regpair rsp_buf_addr /* Buffer to place the sense/response data attached to FCP_RSP frame */;
 681         __le32 rsrv[2];
 682         struct scsi_sgl_params sgl_params;
 683         __le32 data_2_trns_rem /* Entire SGL buffer size remainder */;
 684         __le32 data_buffer_offset /* Buffer offset */;
 685         __le16 parent_id /* Used for multiple continuation in Target mode */;
 686         __le16 flags;
 687 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK     0xF /* Protection log interval (9=512 10=1024  11=2048 12=4096 13=8192) */
 688 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT    0
 689 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK        0x3 /* 0=none, 1=DIF, 2=DIX */
 690 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT       4
 691 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK           0x1 /* 0=no, 1=yes */
 692 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT          6
 693 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK  0x1 /* 0 = 24 Bytes FC Header not included in Middle-Path placement, 1 = 24 Bytes FC Header included in MP placement */
 694 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
 695 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK        0x3 /* DIX block size: can be 0:2B, 1:4B, 2:8B */
 696 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT       8
 697 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK  0x1 /* 0=no, 1=yes */
 698 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
 699 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK    0x1 /* Indication to a single cached DIX SGE instead of SGL */
 700 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT   11
 701 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK         0x1
 702 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT        12
 703 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK           0x1 /* use_enum scsi_sgl_mode (use enum scsi_sgl_mode) */
 704 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT          13
 705 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK              0x3
 706 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT             14
 707         struct scsi_cached_sges data_desc /* Union of Data SGL / cached sge */;
 708 };
 709
 710 struct e4_ustorm_fcoe_task_ag_ctx
 711 {
 712         u8 reserved /* cdu_validation */;
 713         u8 byte1 /* state */;
 714         __le16 icid /* icid */;
 715         u8 flags0;
 716 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
 717 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
 718 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
 719 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
 720 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
 721 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT            5
 722 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK              0x3 /* timer0cf */
 723 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT             6
 724         u8 flags1;
 725 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK              0x3 /* timer1cf */
 726 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT             0
 727 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK              0x3 /* timer2cf */
 728 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT             2
 729 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
 730 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT             4
 731 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK     0x3 /* cf4 */
 732 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT    6
 733         u8 flags2;
 734 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
 735 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT           0
 736 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
 737 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT           1
 738 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
 739 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT           2
 740 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
 741 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT           3
 742 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK  0x1 /* cf4en */
 743 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
 744 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
 745 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT         5
 746 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
 747 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT         6
 748 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
 749 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT         7
 750         u8 flags3;
 751 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
 752 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT         0
 753 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
 754 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT         1
 755 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
 756 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT         2
 757 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
 758 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT         3
 759 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK   0xF /* nibble1 */
 760 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT  4
 761         __le32 dif_err_intervals /* reg0 */;
 762         __le32 dif_error_1st_interval /* reg1 */;
 763         __le32 global_cq_num /* reg2 */;
 764         __le32 reg3 /* reg3 */;
 765         __le32 reg4 /* reg4 */;
 766         __le32 reg5 /* reg5 */;
 767 };
 768
 769 /*
 770  * fcoe task context
 771  */
 772 struct fcoe_task_context
 773 {
 774         struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */;
 775         struct regpair ystorm_st_padding[2] /* padding */;
 776         struct tdif_task_context tdif_context /* tdif context */;
 777         struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
 778         struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
 779         struct timers_context timer_context /* timer context */;
 780         struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */;
 781         struct regpair tstorm_st_padding[2] /* padding */;
 782         struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
 783         struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */;
 784         struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
 785         struct rdif_task_context rdif_context /* rdif context */;
 786 };
 787
 788
 789
 790
 791
 792
 793
 794
 795 /*
 796  * Per PF FCoE transmit path statistics - pStorm RAM structure
 797  */
 798 struct fcoe_tx_stat
 799 {
 800         struct regpair fcoe_tx_byte_cnt /* Transmitted FCoE bytes count */;
 801         struct regpair fcoe_tx_data_pkt_cnt /* Transmitted FCoE FCP DATA packets count */;
 802         struct regpair fcoe_tx_xfer_pkt_cnt /* Transmitted FCoE XFER_RDY packets count */;
 803         struct regpair fcoe_tx_other_pkt_cnt /* Transmitted FCoE packets which are not DATA/XFER_RDY count */;
 804 };
 805
 806
 807 /*
 808  * FCoE SQ/XferQ element
 809  */
 810 struct fcoe_wqe
 811 {
 812         __le16 task_id /* Initiator - The task identifier (OX_ID). Target - Continuation tid or RX_ID in non-continuation mode */;
 813         __le16 flags;
 814 #define FCOE_WQE_REQ_TYPE_MASK       0xF /* Type of the wqe request. use enum fcoe_sqe_request_type  (use enum fcoe_sqe_request_type) */
 815 #define FCOE_WQE_REQ_TYPE_SHIFT      0
 816 #define FCOE_WQE_SGL_MODE_MASK       0x1 /* The driver will give a hint about sizes of SGEs for better credits evaluation at Xstorm. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */
 817 #define FCOE_WQE_SGL_MODE_SHIFT      4
 818 #define FCOE_WQE_CONTINUATION_MASK   0x1 /* Indication if this wqe is a continuation to an existing task (Target only) */
 819 #define FCOE_WQE_CONTINUATION_SHIFT  5
 820 #define FCOE_WQE_SEND_AUTO_RSP_MASK  0x1 /* Indication to FW to send FCP_RSP after all data was sent - Target only */
 821 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
 822 #define FCOE_WQE_RESERVED_MASK       0x1
 823 #define FCOE_WQE_RESERVED_SHIFT      7
 824 #define FCOE_WQE_NUM_SGES_MASK       0xF /* Number of SGEs. 8 = at least 8 sges */
 825 #define FCOE_WQE_NUM_SGES_SHIFT      8
 826 #define FCOE_WQE_RESERVED1_MASK      0xF
 827 #define FCOE_WQE_RESERVED1_SHIFT     12
 828         union fcoe_additional_info_union additional_info_union /* Additional wqe information (if needed) */;
 829 };
 830
 831
 832
 833
 834
 835
 836
 837
 838
 839 /*
 840  * FCoE XFRQ element
 841  */
 842 struct xfrqe_prot_flags
 843 {
 844         u8 flags;
 845 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK  0xF /* Protection log interval (9=512 10=1024  11=2048 12=4096 13=8192) */
 846 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
 847 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK             0x1 /* If DIF protection is configured against target (0=no, 1=yes) */
 848 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT            4
 849 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK          0x3 /* If DIF/DIX protection is configured against the host (0=none, 1=DIF, 2=DIX) */
 850 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT         5
 851 #define XFRQE_PROT_FLAGS_RESERVED_MASK                0x1 /* Must set to 0 */
 852 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT               7
 853 };
 854
 855
 856
 857
 858
 859
 860
 861 struct e5_mstorm_fcoe_task_ag_ctx
 862 {
 863         u8 byte0 /* cdu_validation */;
 864         u8 byte1 /* state_and_core_id */;
 865         __le16 icid /* icid */;
 866         u8 flags0;
 867 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK    0xF /* connection_type */
 868 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT   0
 869 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
 870 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT      4
 871 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK         0x1 /* exist_in_qm1 */
 872 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT        5
 873 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK               0x1 /* bit2 */
 874 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT              6
 875 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK               0x1 /* bit3 */
 876 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT              7
 877         u8 flags1;
 878 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK      0x3 /* cf0 */
 879 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT     0
 880 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK                0x3 /* cf1 */
 881 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT               2
 882 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK                0x3 /* cf2 */
 883 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT               4
 884 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK   0x1 /* cf0en */
 885 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT  6
 886 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
 887 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT             7
 888         u8 flags2;
 889 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
 890 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT             0
 891 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
 892 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT           1
 893 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
 894 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT           2
 895 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
 896 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT           3
 897 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
 898 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT           4
 899 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
 900 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT           5
 901 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK  0x1 /* rule5en */
 902 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
 903 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
 904 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT           7
 905         u8 flags3;
 906 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK       0x1 /* bit4 */
 907 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT      0
 908 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK       0x3 /* cf3 */
 909 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT      1
 910 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK       0x3 /* cf4 */
 911 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT      3
 912 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK       0x1 /* cf3en */
 913 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT      5
 914 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK       0x1 /* cf4en */
 915 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT      6
 916 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK       0x1 /* rule7en */
 917 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT      7
 918         __le32 received_bytes /* reg0 */;
 919         u8 cleanup_state /* byte2 */;
 920         u8 byte3 /* byte3 */;
 921         u8 glbl_q_num /* byte4 */;
 922         u8 e4_reserved7 /* byte5 */;
 923         __le16 word1 /* regpair0 */;
 924         __le16 tid_to_xfer /* word2 */;
 925         __le16 word3 /* word3 */;
 926         __le16 word4 /* word4 */;
 927         __le16 word5 /* regpair1 */;
 928         __le16 e4_reserved8 /* word6 */;
 929         __le32 expected_bytes /* reg1 */;
 930 };
 931
 932
 933 struct e5_tstorm_fcoe_task_ag_ctx
 934 {
 935         u8 reserved /* cdu_validation */;
 936         u8 byte1 /* state_and_core_id */;
 937         __le16 icid /* icid */;
 938         u8 flags0;
 939 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK     0xF /* connection_type */
 940 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT    0
 941 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
 942 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT       4
 943 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK                0x1 /* exist_in_qm1 */
 944 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT               5
 945 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK     0x1 /* bit2 */
 946 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT    6
 947 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK               0x1 /* bit3 */
 948 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT              7
 949         u8 flags1;
 950 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK        0x1 /* bit4 */
 951 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT       0
 952 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK                0x1 /* bit5 */
 953 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT               1
 954 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK       0x3 /* timer0cf */
 955 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT      2
 956 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK           0x3 /* timer1cf */
 957 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT          4
 958 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK                 0x3 /* timer2cf */
 959 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT                6
 960         u8 flags2;
 961 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK      0x3 /* timer_stop_all */
 962 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT     0
 963 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK       0x3 /* cf4 */
 964 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT      2
 965 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK         0x3 /* cf5 */
 966 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT        4
 967 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK     0x3 /* cf6 */
 968 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT    6
 969         u8 flags3;
 970 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK       0x3 /* cf7 */
 971 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT      0
 972 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK    0x1 /* cf0en */
 973 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT   2
 974 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK        0x1 /* cf1en */
 975 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT       3
 976 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK               0x1 /* cf2en */
 977 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT              4
 978 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK   0x1 /* cf3en */
 979 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT  5
 980 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK    0x1 /* cf4en */
 981 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT   6
 982 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK      0x1 /* cf5en */
 983 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT     7
 984         u8 flags4;
 985 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK  0x1 /* cf6en */
 986 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
 987 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK    0x1 /* cf7en */
 988 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT   1
 989 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK             0x1 /* rule0en */
 990 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT            2
 991 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK             0x1 /* rule1en */
 992 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT            3
 993 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK             0x1 /* rule2en */
 994 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT            4
 995 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK             0x1 /* rule3en */
 996 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT            5
 997 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK             0x1 /* rule4en */
 998 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT            6
 999 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK             0x1 /* rule5en */
1000 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT            7
1001         u8 cleanup_state /* byte2 */;
1002         __le16 last_sent_tid /* word1 */;
1003         __le32 rec_rr_tov_exp_timeout /* reg0 */;
1004         u8 byte3 /* regpair0 */;
1005         u8 byte4 /* byte4 */;
1006         __le16 word2 /* word2 */;
1007         __le16 word3 /* word3 */;
1008         __le16 word4 /* word4 */;
1009         __le32 data_offset_end_of_seq /* regpair1 */;
1010         __le32 data_offset_next /* reg2 */;
1011 };
1012
1013
1014 struct e5_ustorm_fcoe_task_ag_ctx
1015 {
1016         u8 reserved /* cdu_validation */;
1017         u8 byte1 /* state_and_core_id */;
1018         __le16 icid /* icid */;
1019         u8 flags0;
1020 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
1021 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
1022 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
1023 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
1024 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
1025 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT            5
1026 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_MASK              0x3 /* timer0cf */
1027 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT             6
1028         u8 flags1;
1029 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_MASK              0x3 /* timer1cf */
1030 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT             0
1031 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_MASK              0x3 /* timer2cf */
1032 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT             2
1033 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
1034 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT             4
1035 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK     0x3 /* dif_error_cf */
1036 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT    6
1037         u8 flags2;
1038 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
1039 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT           0
1040 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
1041 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT           1
1042 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
1043 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT           2
1044 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
1045 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT           3
1046 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK  0x1 /* cf4en */
1047 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
1048 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
1049 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT         5
1050 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
1051 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT         6
1052 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
1053 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT         7
1054         u8 flags3;
1055 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
1056 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT         0
1057 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
1058 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT         1
1059 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
1060 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT         2
1061 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
1062 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT         3
1063 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit2 */
1064 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT    4
1065 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK     0x1 /* bit3 */
1066 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT    5
1067 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK     0x1 /* bit4 */
1068 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT    6
1069 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK     0x1 /* rule7en */
1070 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT    7
1071         u8 flags4;
1072 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK     0x3 /* cf5 */
1073 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT    0
1074 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK     0x1 /* cf5en */
1075 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT    2
1076 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_MASK     0x1 /* rule8en */
1077 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_SHIFT    3
1078 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK   0xF /* dif_error_type */
1079 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT  4
1080         u8 byte2 /* byte2 */;
1081         u8 byte3 /* byte3 */;
1082         u8 e4_reserved8 /* byte4 */;
1083         __le32 dif_err_intervals /* dif_err_intervals */;
1084         __le32 dif_error_1st_interval /* dif_error_1st_interval */;
1085         __le32 global_cq_num /* reg2 */;
1086         __le32 reg3 /* reg3 */;
1087         __le32 reg4 /* reg4 */;
1088 };
1089
1090
1091 struct e5_ystorm_fcoe_task_ag_ctx
1092 {
1093         u8 byte0 /* cdu_validation */;
1094         u8 byte1 /* state_and_core_id */;
1095         __le16 word0 /* icid */;
1096         u8 flags0;
1097 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK       0xF /* connection_type */
1098 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT      0
1099 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK          0x1 /* exist_in_qm0 */
1100 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT         4
1101 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK          0x1 /* exist_in_qm1 */
1102 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT         5
1103 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK          0x1 /* bit2 */
1104 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT         6
1105 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK          0x1 /* bit3 */
1106 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT         7
1107         u8 flags1;
1108 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK           0x3 /* cf0 */
1109 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT          0
1110 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK           0x3 /* cf1 */
1111 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT          2
1112 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK    0x3 /* cf2special */
1113 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT   4
1114 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK         0x1 /* cf0en */
1115 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT        6
1116 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK         0x1 /* cf1en */
1117 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT        7
1118         u8 flags2;
1119 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK          0x1 /* bit4 */
1120 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT         0
1121 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK       0x1 /* rule0en */
1122 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT      1
1123 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK       0x1 /* rule1en */
1124 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT      2
1125 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK       0x1 /* rule2en */
1126 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT      3
1127 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK       0x1 /* rule3en */
1128 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT      4
1129 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK       0x1 /* rule4en */
1130 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT      5
1131 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK       0x1 /* rule5en */
1132 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT      6
1133 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK       0x1 /* rule6en */
1134 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT      7
1135         u8 flags3;
1136 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK  0x1 /* bit5 */
1137 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0
1138 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK  0x3 /* cf3 */
1139 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1
1140 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK  0x3 /* cf4 */
1141 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
1142 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK  0x1 /* cf3en */
1143 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5
1144 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK  0x1 /* cf4en */
1145 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6
1146 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK  0x1 /* rule7en */
1147 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7
1148         __le32 reg0 /* reg0 */;
1149         u8 byte2 /* byte2 */;
1150         u8 byte3 /* byte3 */;
1151         u8 byte4 /* byte4 */;
1152         u8 e4_reserved7 /* byte5 */;
1153         __le16 rx_id /* word1 */;
1154         __le16 word2 /* word2 */;
1155         __le16 word3 /* word3 */;
1156         __le16 word4 /* word4 */;
1157         __le16 word5 /* word5 */;
1158         __le16 e4_reserved8 /* word6 */;
1159         __le32 reg1 /* reg1 */;
1160 };
1161
1162
1163 /*
1164  * FCoE doorbell data
1165  */
1166 struct fcoe_db_data
1167 {
1168         u8 params;
1169 #define FCOE_DB_DATA_DEST_MASK         0x3 /* destination of doorbell (use enum db_dest) */
1170 #define FCOE_DB_DATA_DEST_SHIFT        0
1171 #define FCOE_DB_DATA_AGG_CMD_MASK      0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */
1172 #define FCOE_DB_DATA_AGG_CMD_SHIFT     2
1173 #define FCOE_DB_DATA_BYPASS_EN_MASK    0x1 /* enable QM bypass */
1174 #define FCOE_DB_DATA_BYPASS_EN_SHIFT   4
1175 #define FCOE_DB_DATA_RESERVED_MASK     0x1
1176 #define FCOE_DB_DATA_RESERVED_SHIFT    5
1177 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK  0x3 /* aggregative value selection */
1178 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
1179         u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */;
1180         __le16 sq_prod;
1181 };
1182
1183 #endif /* __FCOE_COMMON__ */