usr/src/uts/common/io/qede/579xx/drivers/ecore/hsi_repository/ecore_hsi_toe.h

   1 /*
   2 * CDDL HEADER START
   3 *
   4 * The contents of this file are subject to the terms of the
   5 * Common Development and Distribution License, v.1,  (the "License").
   6 * You may not use this file except in compliance with the License.
   7 *
   8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9 * or http://opensource.org/licenses/CDDL-1.0.
  10 * See the License for the specific language governing permissions
  11 * and limitations under the License.
  12 *
  13 * When distributing Covered Code, include this CDDL HEADER in each
  14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15 * If applicable, add the following below this CDDL HEADER, with the
  16 * fields enclosed by brackets "[]" replaced with your own identifying
  17 * information: Portions Copyright [yyyy] [name of copyright owner]
  18 *
  19 * CDDL HEADER END
  20 */
  21
  22 /*
  23 * Copyright 2014-2017 Cavium, Inc.
  24 * The contents of this file are subject to the terms of the Common Development
  25 * and Distribution License, v.1,  (the "License").
  26
  27 * You may not use this file except in compliance with the License.
  28
  29 * You can obtain a copy of the License at available
  30 * at http://opensource.org/licenses/CDDL-1.0
  31
  32 * See the License for the specific language governing permissions and
  33 * limitations under the License.
  34 */
  35
  36 #ifndef __ECORE_HSI_TOE__
  37 #define __ECORE_HSI_TOE__
  38 /************************************************************************/
  39 /* Add include to common TCP target */
  40 /************************************************************************/
  41 #include "tcp_common.h"
  42
  43 /********************/
  44 /* TOE FW CONSTANTS */
  45 /********************/
  46
  47 #define TOE_MAX_RAMROD_PER_PF                           8
  48 #define TOE_TX_PAGE_SIZE_BYTES                          4096
  49 #define TOE_GRQ_PAGE_SIZE_BYTES                         4096
  50 #define TOE_RX_CQ_PAGE_SIZE_BYTES                       4096
  51
  52 #define TOE_RX_MAX_RSS_CHAINS                           64
  53 #define TOE_TX_MAX_TSS_CHAINS                           64
  54 #define TOE_RSS_INDIRECTION_TABLE_SIZE          128
  55
  56
  57 /*
  58  * The toe storm context of Mstorm
  59  */
  60 struct mstorm_toe_conn_st_ctx
  61 {
  62         __le32 reserved[24];
  63 };
  64
  65
  66 /*
  67  * The toe storm context of Pstorm
  68  */
  69 struct pstorm_toe_conn_st_ctx
  70 {
  71         __le32 reserved[36];
  72 };
  73
  74
  75 /*
  76  * The toe storm context of Ystorm
  77  */
  78 struct ystorm_toe_conn_st_ctx
  79 {
  80         __le32 reserved[8];
  81 };
  82
  83 /*
  84  * The toe storm context of Xstorm
  85  */
  86 struct xstorm_toe_conn_st_ctx
  87 {
  88         __le32 reserved[44];
  89 };
  90
  91 struct e4_ystorm_toe_conn_ag_ctx
  92 {
  93         u8 byte0 /* cdu_validation */;
  94         u8 byte1 /* state */;
  95         u8 flags0;
  96 #define E4_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
  97 #define E4_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
  98 #define E4_YSTORM_TOE_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
  99 #define E4_YSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT                 1
 100 #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK          0x3 /* cf0 */
 101 #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT         2
 102 #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK     0x3 /* cf1 */
 103 #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_SHIFT    4
 104 #define E4_YSTORM_TOE_CONN_AG_CTX_CF2_MASK                   0x3 /* cf2 */
 105 #define E4_YSTORM_TOE_CONN_AG_CTX_CF2_SHIFT                  6
 106         u8 flags1;
 107 #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK       0x1 /* cf0en */
 108 #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT      0
 109 #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK  0x1 /* cf1en */
 110 #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_SHIFT 1
 111 #define E4_YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
 112 #define E4_YSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT                2
 113 #define E4_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK            0x1 /* rule0en */
 114 #define E4_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_SHIFT           3
 115 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
 116 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT              4
 117 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
 118 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT              5
 119 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
 120 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT              6
 121 #define E4_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK          0x1 /* rule4en */
 122 #define E4_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_SHIFT         7
 123         u8 completion_opcode /* byte2 */;
 124         u8 byte3 /* byte3 */;
 125         __le16 word0 /* word0 */;
 126         __le32 rel_seq /* reg0 */;
 127         __le32 rel_seq_threshold /* reg1 */;
 128         __le16 app_prod /* word1 */;
 129         __le16 app_cons /* word2 */;
 130         __le16 word3 /* word3 */;
 131         __le16 word4 /* word4 */;
 132         __le32 reg2 /* reg2 */;
 133         __le32 reg3 /* reg3 */;
 134 };
 135
 136 struct e4_xstorm_toe_conn_ag_ctx
 137 {
 138         u8 reserved0 /* cdu_validation */;
 139         u8 state /* state */;
 140         u8 flags0;
 141 #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
 142 #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
 143 #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK          0x1 /* exist_in_qm1 */
 144 #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_SHIFT         1
 145 #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK             0x1 /* exist_in_qm2 */
 146 #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED1_SHIFT            2
 147 #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK          0x1 /* exist_in_qm3 */
 148 #define E4_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT         3
 149 #define E4_XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK       0x1 /* bit4 */
 150 #define E4_XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_SHIFT      4
 151 #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK             0x1 /* cf_array_active */
 152 #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED2_SHIFT            5
 153 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT6_MASK                  0x1 /* bit6 */
 154 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT6_SHIFT                 6
 155 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT7_MASK                  0x1 /* bit7 */
 156 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT7_SHIFT                 7
 157         u8 flags1;
 158 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT8_MASK                  0x1 /* bit8 */
 159 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT                 0
 160 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT9_MASK                  0x1 /* bit9 */
 161 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT9_SHIFT                 1
 162 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT10_MASK                 0x1 /* bit10 */
 163 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT10_SHIFT                2
 164 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT11_MASK                 0x1 /* bit11 */
 165 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT11_SHIFT                3
 166 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT12_MASK                 0x1 /* bit12 */
 167 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT12_SHIFT                4
 168 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT13_MASK                 0x1 /* bit13 */
 169 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT13_SHIFT                5
 170 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT14_MASK                 0x1 /* bit14 */
 171 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT14_SHIFT                6
 172 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT15_MASK                 0x1 /* bit15 */
 173 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT15_SHIFT                7
 174         u8 flags2;
 175 #define E4_XSTORM_TOE_CONN_AG_CTX_CF0_MASK                   0x3 /* timer0cf */
 176 #define E4_XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT                  0
 177 #define E4_XSTORM_TOE_CONN_AG_CTX_CF1_MASK                   0x3 /* timer1cf */
 178 #define E4_XSTORM_TOE_CONN_AG_CTX_CF1_SHIFT                  2
 179 #define E4_XSTORM_TOE_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
 180 #define E4_XSTORM_TOE_CONN_AG_CTX_CF2_SHIFT                  4
 181 #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK        0x3 /* timer_stop_all */
 182 #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT       6
 183         u8 flags3;
 184 #define E4_XSTORM_TOE_CONN_AG_CTX_CF4_MASK                   0x3 /* cf4 */
 185 #define E4_XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT                  0
 186 #define E4_XSTORM_TOE_CONN_AG_CTX_CF5_MASK                   0x3 /* cf5 */
 187 #define E4_XSTORM_TOE_CONN_AG_CTX_CF5_SHIFT                  2
 188 #define E4_XSTORM_TOE_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
 189 #define E4_XSTORM_TOE_CONN_AG_CTX_CF6_SHIFT                  4
 190 #define E4_XSTORM_TOE_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
 191 #define E4_XSTORM_TOE_CONN_AG_CTX_CF7_SHIFT                  6
 192         u8 flags4;
 193 #define E4_XSTORM_TOE_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
 194 #define E4_XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT                  0
 195 #define E4_XSTORM_TOE_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
 196 #define E4_XSTORM_TOE_CONN_AG_CTX_CF9_SHIFT                  2
 197 #define E4_XSTORM_TOE_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
 198 #define E4_XSTORM_TOE_CONN_AG_CTX_CF10_SHIFT                 4
 199 #define E4_XSTORM_TOE_CONN_AG_CTX_CF11_MASK                  0x3 /* cf11 */
 200 #define E4_XSTORM_TOE_CONN_AG_CTX_CF11_SHIFT                 6
 201         u8 flags5;
 202 #define E4_XSTORM_TOE_CONN_AG_CTX_CF12_MASK                  0x3 /* cf12 */
 203 #define E4_XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT                 0
 204 #define E4_XSTORM_TOE_CONN_AG_CTX_CF13_MASK                  0x3 /* cf13 */
 205 #define E4_XSTORM_TOE_CONN_AG_CTX_CF13_SHIFT                 2
 206 #define E4_XSTORM_TOE_CONN_AG_CTX_CF14_MASK                  0x3 /* cf14 */
 207 #define E4_XSTORM_TOE_CONN_AG_CTX_CF14_SHIFT                 4
 208 #define E4_XSTORM_TOE_CONN_AG_CTX_CF15_MASK                  0x3 /* cf15 */
 209 #define E4_XSTORM_TOE_CONN_AG_CTX_CF15_SHIFT                 6
 210         u8 flags6;
 211 #define E4_XSTORM_TOE_CONN_AG_CTX_CF16_MASK                  0x3 /* cf16 */
 212 #define E4_XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT                 0
 213 #define E4_XSTORM_TOE_CONN_AG_CTX_CF17_MASK                  0x3 /* cf_array_cf */
 214 #define E4_XSTORM_TOE_CONN_AG_CTX_CF17_SHIFT                 2
 215 #define E4_XSTORM_TOE_CONN_AG_CTX_CF18_MASK                  0x3 /* cf18 */
 216 #define E4_XSTORM_TOE_CONN_AG_CTX_CF18_SHIFT                 4
 217 #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK              0x3 /* cf19 */
 218 #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_SHIFT             6
 219         u8 flags7;
 220 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK              0x3 /* cf20 */
 221 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT             0
 222 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK              0x3 /* cf21 */
 223 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_SHIFT             2
 224 #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK             0x3 /* cf22 */
 225 #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_SHIFT            4
 226 #define E4_XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK                 0x1 /* cf0en */
 227 #define E4_XSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT                6
 228 #define E4_XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK                 0x1 /* cf1en */
 229 #define E4_XSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT                7
 230         u8 flags8;
 231 #define E4_XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
 232 #define E4_XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT                0
 233 #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK     0x1 /* cf3en */
 234 #define E4_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT    1
 235 #define E4_XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK                 0x1 /* cf4en */
 236 #define E4_XSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT                2
 237 #define E4_XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK                 0x1 /* cf5en */
 238 #define E4_XSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT                3
 239 #define E4_XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
 240 #define E4_XSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT                4
 241 #define E4_XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
 242 #define E4_XSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT                5
 243 #define E4_XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
 244 #define E4_XSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT                6
 245 #define E4_XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
 246 #define E4_XSTORM_TOE_CONN_AG_CTX_CF9EN_SHIFT                7
 247         u8 flags9;
 248 #define E4_XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
 249 #define E4_XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT               0
 250 #define E4_XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK                0x1 /* cf11en */
 251 #define E4_XSTORM_TOE_CONN_AG_CTX_CF11EN_SHIFT               1
 252 #define E4_XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK                0x1 /* cf12en */
 253 #define E4_XSTORM_TOE_CONN_AG_CTX_CF12EN_SHIFT               2
 254 #define E4_XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK                0x1 /* cf13en */
 255 #define E4_XSTORM_TOE_CONN_AG_CTX_CF13EN_SHIFT               3
 256 #define E4_XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK                0x1 /* cf14en */
 257 #define E4_XSTORM_TOE_CONN_AG_CTX_CF14EN_SHIFT               4
 258 #define E4_XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK                0x1 /* cf15en */
 259 #define E4_XSTORM_TOE_CONN_AG_CTX_CF15EN_SHIFT               5
 260 #define E4_XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK                0x1 /* cf16en */
 261 #define E4_XSTORM_TOE_CONN_AG_CTX_CF16EN_SHIFT               6
 262 #define E4_XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK                0x1 /* cf_array_cf_en */
 263 #define E4_XSTORM_TOE_CONN_AG_CTX_CF17EN_SHIFT               7
 264         u8 flags10;
 265 #define E4_XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK                0x1 /* cf18en */
 266 #define E4_XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT               0
 267 #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK           0x1 /* cf19en */
 268 #define E4_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT          1
 269 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK           0x1 /* cf20en */
 270 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT          2
 271 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK           0x1 /* cf21en */
 272 #define E4_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT          3
 273 #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK          0x1 /* cf22en */
 274 #define E4_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT         4
 275 #define E4_XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK                0x1 /* cf23en */
 276 #define E4_XSTORM_TOE_CONN_AG_CTX_CF23EN_SHIFT               5
 277 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
 278 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT              6
 279 #define E4_XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK  0x1 /* rule1en */
 280 #define E4_XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
 281         u8 flags11;
 282 #define E4_XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK         0x1 /* rule2en */
 283 #define E4_XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT        0
 284 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
 285 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT              1
 286 #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK             0x1 /* rule4en */
 287 #define E4_XSTORM_TOE_CONN_AG_CTX_RESERVED3_SHIFT            2
 288 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
 289 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT              3
 290 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
 291 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT              4
 292 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
 293 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT              5
 294 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK          0x1 /* rule8en */
 295 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_SHIFT         6
 296 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK               0x1 /* rule9en */
 297 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE9EN_SHIFT              7
 298         u8 flags12;
 299 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK              0x1 /* rule10en */
 300 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT             0
 301 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK              0x1 /* rule11en */
 302 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE11EN_SHIFT             1
 303 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK          0x1 /* rule12en */
 304 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_SHIFT         2
 305 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK          0x1 /* rule13en */
 306 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_SHIFT         3
 307 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK              0x1 /* rule14en */
 308 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE14EN_SHIFT             4
 309 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK              0x1 /* rule15en */
 310 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE15EN_SHIFT             5
 311 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK              0x1 /* rule16en */
 312 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE16EN_SHIFT             6
 313 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK              0x1 /* rule17en */
 314 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE17EN_SHIFT             7
 315         u8 flags13;
 316 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK              0x1 /* rule18en */
 317 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT             0
 318 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK              0x1 /* rule19en */
 319 #define E4_XSTORM_TOE_CONN_AG_CTX_RULE19EN_SHIFT             1
 320 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK          0x1 /* rule20en */
 321 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_SHIFT         2
 322 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK          0x1 /* rule21en */
 323 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_SHIFT         3
 324 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK          0x1 /* rule22en */
 325 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_SHIFT         4
 326 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK          0x1 /* rule23en */
 327 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_SHIFT         5
 328 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK          0x1 /* rule24en */
 329 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_SHIFT         6
 330 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK          0x1 /* rule25en */
 331 #define E4_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_SHIFT         7
 332         u8 flags14;
 333 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT16_MASK                 0x1 /* bit16 */
 334 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT                0
 335 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT17_MASK                 0x1 /* bit17 */
 336 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT17_SHIFT                1
 337 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT18_MASK                 0x1 /* bit18 */
 338 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT18_SHIFT                2
 339 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT19_MASK                 0x1 /* bit19 */
 340 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT19_SHIFT                3
 341 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT20_MASK                 0x1 /* bit20 */
 342 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT20_SHIFT                4
 343 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT21_MASK                 0x1 /* bit21 */
 344 #define E4_XSTORM_TOE_CONN_AG_CTX_BIT21_SHIFT                5
 345 #define E4_XSTORM_TOE_CONN_AG_CTX_CF23_MASK                  0x3 /* cf23 */
 346 #define E4_XSTORM_TOE_CONN_AG_CTX_CF23_SHIFT                 6
 347         u8 byte2 /* byte2 */;
 348         __le16 physical_q0 /* physical_q0 */;
 349         __le16 physical_q1 /* physical_q1 */;
 350         __le16 word2 /* physical_q2 */;
 351         __le16 word3 /* word3 */;
 352         __le16 bd_prod /* word4 */;
 353         __le16 word5 /* word5 */;
 354         __le16 word6 /* conn_dpi */;
 355         u8 byte3 /* byte3 */;
 356         u8 byte4 /* byte4 */;
 357         u8 byte5 /* byte5 */;
 358         u8 byte6 /* byte6 */;
 359         __le32 reg0 /* reg0 */;
 360         __le32 reg1 /* reg1 */;
 361         __le32 reg2 /* reg2 */;
 362         __le32 more_to_send_seq /* reg3 */;
 363         __le32 local_adv_wnd_seq /* reg4 */;
 364         __le32 reg5 /* cf_array0 */;
 365         __le32 reg6 /* cf_array1 */;
 366         __le16 word7 /* word7 */;
 367         __le16 word8 /* word8 */;
 368         __le16 word9 /* word9 */;
 369         __le16 word10 /* word10 */;
 370         __le32 reg7 /* reg7 */;
 371         __le32 reg8 /* reg8 */;
 372         __le32 reg9 /* reg9 */;
 373         u8 byte7 /* byte7 */;
 374         u8 byte8 /* byte8 */;
 375         u8 byte9 /* byte9 */;
 376         u8 byte10 /* byte10 */;
 377         u8 byte11 /* byte11 */;
 378         u8 byte12 /* byte12 */;
 379         u8 byte13 /* byte13 */;
 380         u8 byte14 /* byte14 */;
 381         u8 byte15 /* byte15 */;
 382         u8 e5_reserved /* e5_reserved */;
 383         __le16 word11 /* word11 */;
 384         __le32 reg10 /* reg10 */;
 385         __le32 reg11 /* reg11 */;
 386         __le32 reg12 /* reg12 */;
 387         __le32 reg13 /* reg13 */;
 388         __le32 reg14 /* reg14 */;
 389         __le32 reg15 /* reg15 */;
 390         __le32 reg16 /* reg16 */;
 391         __le32 reg17 /* reg17 */;
 392 };
 393
 394 struct e4_tstorm_toe_conn_ag_ctx
 395 {
 396         u8 reserved0 /* cdu_validation */;
 397         u8 byte1 /* state */;
 398         u8 flags0;
 399 #define E4_TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
 400 #define E4_TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
 401 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT1_MASK               0x1 /* exist_in_qm1 */
 402 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT              1
 403 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT2_MASK               0x1 /* bit2 */
 404 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT2_SHIFT              2
 405 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT3_MASK               0x1 /* bit3 */
 406 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT3_SHIFT              3
 407 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT4_MASK               0x1 /* bit4 */
 408 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT4_SHIFT              4
 409 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT5_MASK               0x1 /* bit5 */
 410 #define E4_TSTORM_TOE_CONN_AG_CTX_BIT5_SHIFT              5
 411 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK         0x3 /* timer0cf */
 412 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_SHIFT        6
 413         u8 flags1;
 414 #define E4_TSTORM_TOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
 415 #define E4_TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT               0
 416 #define E4_TSTORM_TOE_CONN_AG_CTX_CF2_MASK                0x3 /* timer2cf */
 417 #define E4_TSTORM_TOE_CONN_AG_CTX_CF2_SHIFT               2
 418 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK     0x3 /* timer_stop_all */
 419 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT    4
 420 #define E4_TSTORM_TOE_CONN_AG_CTX_CF4_MASK                0x3 /* cf4 */
 421 #define E4_TSTORM_TOE_CONN_AG_CTX_CF4_SHIFT               6
 422         u8 flags2;
 423 #define E4_TSTORM_TOE_CONN_AG_CTX_CF5_MASK                0x3 /* cf5 */
 424 #define E4_TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT               0
 425 #define E4_TSTORM_TOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
 426 #define E4_TSTORM_TOE_CONN_AG_CTX_CF6_SHIFT               2
 427 #define E4_TSTORM_TOE_CONN_AG_CTX_CF7_MASK                0x3 /* cf7 */
 428 #define E4_TSTORM_TOE_CONN_AG_CTX_CF7_SHIFT               4
 429 #define E4_TSTORM_TOE_CONN_AG_CTX_CF8_MASK                0x3 /* cf8 */
 430 #define E4_TSTORM_TOE_CONN_AG_CTX_CF8_SHIFT               6
 431         u8 flags3;
 432 #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3 /* cf9 */
 433 #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
 434 #define E4_TSTORM_TOE_CONN_AG_CTX_CF10_MASK               0x3 /* cf10 */
 435 #define E4_TSTORM_TOE_CONN_AG_CTX_CF10_SHIFT              2
 436 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK      0x1 /* cf0en */
 437 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_SHIFT     4
 438 #define E4_TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
 439 #define E4_TSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT             5
 440 #define E4_TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
 441 #define E4_TSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT             6
 442 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK  0x1 /* cf3en */
 443 #define E4_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
 444         u8 flags4;
 445 #define E4_TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK              0x1 /* cf4en */
 446 #define E4_TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT             0
 447 #define E4_TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK              0x1 /* cf5en */
 448 #define E4_TSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT             1
 449 #define E4_TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
 450 #define E4_TSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT             2
 451 #define E4_TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK              0x1 /* cf7en */
 452 #define E4_TSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT             3
 453 #define E4_TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK              0x1 /* cf8en */
 454 #define E4_TSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT             4
 455 #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1 /* cf9en */
 456 #define E4_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       5
 457 #define E4_TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK             0x1 /* cf10en */
 458 #define E4_TSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT            6
 459 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
 460 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT           7
 461         u8 flags5;
 462 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
 463 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT           0
 464 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
 465 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT           1
 466 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
 467 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT           2
 468 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
 469 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT           3
 470 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
 471 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT           4
 472 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
 473 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT           5
 474 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
 475 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT           6
 476 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK            0x1 /* rule8en */
 477 #define E4_TSTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT           7
 478         __le32 reg0 /* reg0 */;
 479         __le32 reg1 /* reg1 */;
 480         __le32 reg2 /* reg2 */;
 481         __le32 reg3 /* reg3 */;
 482         __le32 reg4 /* reg4 */;
 483         __le32 reg5 /* reg5 */;
 484         __le32 reg6 /* reg6 */;
 485         __le32 reg7 /* reg7 */;
 486         __le32 reg8 /* reg8 */;
 487         u8 byte2 /* byte2 */;
 488         u8 byte3 /* byte3 */;
 489         __le16 word0 /* word0 */;
 490 };
 491
 492 struct e4_ustorm_toe_conn_ag_ctx
 493 {
 494         u8 reserved /* cdu_validation */;
 495         u8 byte1 /* state */;
 496         u8 flags0;
 497 #define E4_USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
 498 #define E4_USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
 499 #define E4_USTORM_TOE_CONN_AG_CTX_BIT1_MASK               0x1 /* exist_in_qm1 */
 500 #define E4_USTORM_TOE_CONN_AG_CTX_BIT1_SHIFT              1
 501 #define E4_USTORM_TOE_CONN_AG_CTX_CF0_MASK                0x3 /* timer0cf */
 502 #define E4_USTORM_TOE_CONN_AG_CTX_CF0_SHIFT               2
 503 #define E4_USTORM_TOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
 504 #define E4_USTORM_TOE_CONN_AG_CTX_CF1_SHIFT               4
 505 #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK      0x3 /* timer2cf */
 506 #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_SHIFT     6
 507         u8 flags1;
 508 #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK     0x3 /* timer_stop_all */
 509 #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT    0
 510 #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK       0x3 /* cf4 */
 511 #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT      2
 512 #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK              0x3 /* cf5 */
 513 #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_SHIFT             4
 514 #define E4_USTORM_TOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
 515 #define E4_USTORM_TOE_CONN_AG_CTX_CF6_SHIFT               6
 516         u8 flags2;
 517 #define E4_USTORM_TOE_CONN_AG_CTX_CF0EN_MASK              0x1 /* cf0en */
 518 #define E4_USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT             0
 519 #define E4_USTORM_TOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
 520 #define E4_USTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT             1
 521 #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK   0x1 /* cf2en */
 522 #define E4_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_SHIFT  2
 523 #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK  0x1 /* cf3en */
 524 #define E4_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 3
 525 #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK    0x1 /* cf4en */
 526 #define E4_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT   4
 527 #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1 /* cf5en */
 528 #define E4_USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_SHIFT          5
 529 #define E4_USTORM_TOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
 530 #define E4_USTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT             6
 531 #define E4_USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
 532 #define E4_USTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT           7
 533         u8 flags3;
 534 #define E4_USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
 535 #define E4_USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT           0
 536 #define E4_USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
 537 #define E4_USTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT           1
 538 #define E4_USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
 539 #define E4_USTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT           2
 540 #define E4_USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
 541 #define E4_USTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT           3
 542 #define E4_USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
 543 #define E4_USTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT           4
 544 #define E4_USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
 545 #define E4_USTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT           5
 546 #define E4_USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
 547 #define E4_USTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT           6
 548 #define E4_USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK            0x1 /* rule8en */
 549 #define E4_USTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT           7
 550         u8 byte2 /* byte2 */;
 551         u8 byte3 /* byte3 */;
 552         __le16 word0 /* conn_dpi */;
 553         __le16 word1 /* word1 */;
 554         __le32 reg0 /* reg0 */;
 555         __le32 reg1 /* reg1 */;
 556         __le32 reg2 /* reg2 */;
 557         __le32 reg3 /* reg3 */;
 558         __le16 word2 /* word2 */;
 559         __le16 word3 /* word3 */;
 560 };
 561
 562 /*
 563  * The toe storm context of Tstorm
 564  */
 565 struct tstorm_toe_conn_st_ctx
 566 {
 567         __le32 reserved[16];
 568 };
 569
 570 /*
 571  * The toe storm context of Ustorm
 572  */
 573 struct ustorm_toe_conn_st_ctx
 574 {
 575         __le32 reserved[52];
 576 };
 577
 578 /*
 579  * toe connection context
 580  */
 581 struct toe_conn_context
 582 {
 583         struct ystorm_toe_conn_st_ctx ystorm_st_context /* ystorm storm context */;
 584         struct pstorm_toe_conn_st_ctx pstorm_st_context /* pstorm storm context */;
 585         struct regpair pstorm_st_padding[2] /* padding */;
 586         struct xstorm_toe_conn_st_ctx xstorm_st_context /* xstorm storm context */;
 587         struct regpair xstorm_st_padding[2] /* padding */;
 588         struct e4_ystorm_toe_conn_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
 589         struct e4_xstorm_toe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */;
 590         struct e4_tstorm_toe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
 591         struct regpair tstorm_ag_padding[2] /* padding */;
 592         struct timers_context timer_context /* timer context */;
 593         struct e4_ustorm_toe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
 594         struct tstorm_toe_conn_st_ctx tstorm_st_context /* tstorm storm context */;
 595         struct mstorm_toe_conn_st_ctx mstorm_st_context /* mstorm storm context */;
 596         struct ustorm_toe_conn_st_ctx ustorm_st_context /* ustorm storm context */;
 597 };
 598
 599
 600 /*
 601  * toe init ramrod header
 602  */
 603 struct toe_init_ramrod_header
 604 {
 605         u8 first_rss /* First rss in PF */;
 606         u8 num_rss /* Num of rss ids in PF */;
 607         u8 reserved[6];
 608 };
 609
 610 /*
 611  * toe pf init parameters
 612  */
 613 struct toe_pf_init_params
 614 {
 615         __le32 push_timeout /* push timer timeout in miliseconds */;
 616         __le16 grq_buffer_size /* GRQ buffer size in bytes */;
 617         __le16 grq_sb_id /* GRQ status block id */;
 618         u8 grq_sb_index /* GRQ status block index */;
 619         u8 max_seg_retransmit /* Maximum number of retransmits for one segment */;
 620         u8 doubt_reachability /* Doubt reachability threshold */;
 621         u8 ll2_rx_queue_id /* Queue ID of the Light-L2 Rx Queue */;
 622         __le16 grq_fetch_threshold /* when passing this threshold, firmware will sync the driver with grq consumer */;
 623         u8 reserved1[2];
 624         struct regpair grq_page_addr /* Address of the first page in the grq ring */;
 625 };
 626
 627 /*
 628  * toe tss parameters
 629  */
 630 struct toe_tss_params
 631 {
 632         struct regpair curr_page_addr /* Address of the current page in the tx cq ring */;
 633         struct regpair next_page_addr /* Address of the next page in the tx cq ring */;
 634         u8 reserved0 /* Status block id */;
 635         u8 status_block_index /* Status block index */;
 636         __le16 status_block_id /* Status block id */;
 637         __le16 reserved1[2];
 638 };
 639
 640 /*
 641  * toe rss parameters
 642  */
 643 struct toe_rss_params
 644 {
 645         struct regpair curr_page_addr /* Address of the current page in the rx cq ring */;
 646         struct regpair next_page_addr /* Address of the next page in the rx cq ring */;
 647         u8 reserved0 /* Status block id */;
 648         u8 status_block_index /* Status block index */;
 649         __le16 status_block_id /* Status block id */;
 650         __le16 reserved1[2];
 651 };
 652
 653 /*
 654  * toe init ramrod data
 655  */
 656 struct toe_init_ramrod_data
 657 {
 658         struct toe_init_ramrod_header hdr;
 659         struct tcp_init_params tcp_params;
 660         struct toe_pf_init_params pf_params;
 661         struct toe_tss_params tss_params[TOE_TX_MAX_TSS_CHAINS];
 662         struct toe_rss_params rss_params[TOE_RX_MAX_RSS_CHAINS];
 663 };
 664
 665
 666
 667 /*
 668  * toe offload parameters
 669  */
 670 struct toe_offload_params
 671 {
 672         struct regpair tx_bd_page_addr /* Tx Bd page address */;
 673         struct regpair tx_app_page_addr /* Tx App page address */;
 674         struct regpair rx_bd_page_addr /* Rx Bd page address */;
 675         __le32 more_to_send_seq /* Last byte in bd prod (not including fin) */;
 676         __le16 tx_app_prod /* Producer of application buffer ring */;
 677         __le16 rcv_indication_size /* Recieve indication threshold */;
 678         __le16 reserved;
 679         u8 rss_tss_id /* RSS/TSS absolute id */;
 680         u8 ignore_grq_push;
 681         struct regpair rx_db_data_ptr;
 682         __le32 reserved1;
 683 };
 684
 685
 686 /*
 687  * TOE offload ramrod data - DMAed by firmware
 688  */
 689 struct toe_offload_ramrod_data
 690 {
 691         struct tcp_offload_params tcp_ofld_params;
 692         struct toe_offload_params toe_ofld_params;
 693 };
 694
 695
 696
 697 /*
 698  * TOE ramrod command IDs
 699  */
 700 enum toe_ramrod_cmd_id
 701 {
 702         TOE_RAMROD_UNUSED,
 703         TOE_RAMROD_FUNC_INIT,
 704         TOE_RAMROD_INITATE_OFFLOAD,
 705         TOE_RAMROD_FUNC_CLOSE,
 706         TOE_RAMROD_SEARCHER_DELETE,
 707         TOE_RAMROD_TERMINATE,
 708         TOE_RAMROD_QUERY,
 709         TOE_RAMROD_UPDATE,
 710         TOE_RAMROD_EMPTY,
 711         TOE_RAMROD_RESET_SEND,
 712         TOE_RAMROD_INVALIDATE,
 713         MAX_TOE_RAMROD_CMD_ID
 714 };
 715
 716
 717
 718 /*
 719  * Toe RQ buffer descriptor
 720  */
 721 struct toe_rx_bd
 722 {
 723         struct regpair addr /* Address of buffer */;
 724         __le16 size /* Size of buffer */;
 725         __le16 flags;
 726 #define TOE_RX_BD_START_MASK      0x1 /* this bd is the beginning of an application buffer */
 727 #define TOE_RX_BD_START_SHIFT     0
 728 #define TOE_RX_BD_END_MASK        0x1 /* this bd is the end of an application buffer */
 729 #define TOE_RX_BD_END_SHIFT       1
 730 #define TOE_RX_BD_NO_PUSH_MASK    0x1 /* this application buffer must not be partially completed */
 731 #define TOE_RX_BD_NO_PUSH_SHIFT   2
 732 #define TOE_RX_BD_SPLIT_MASK      0x1
 733 #define TOE_RX_BD_SPLIT_SHIFT     3
 734 #define TOE_RX_BD_RESERVED0_MASK  0xFFF
 735 #define TOE_RX_BD_RESERVED0_SHIFT 4
 736         __le32 reserved1;
 737 };
 738
 739
 740 /*
 741  * TOE RX completion queue opcodes (opcode 0 is illegal)
 742  */
 743 enum toe_rx_cmp_opcode
 744 {
 745         TOE_RX_CMP_OPCODE_GA=1,
 746         TOE_RX_CMP_OPCODE_GR=2,
 747         TOE_RX_CMP_OPCODE_GNI=3,
 748         TOE_RX_CMP_OPCODE_GAIR=4,
 749         TOE_RX_CMP_OPCODE_GAIL=5,
 750         TOE_RX_CMP_OPCODE_GRI=6,
 751         TOE_RX_CMP_OPCODE_GJ=7,
 752         TOE_RX_CMP_OPCODE_DGI=8,
 753         TOE_RX_CMP_OPCODE_CMP=9,
 754         TOE_RX_CMP_OPCODE_REL=10,
 755         TOE_RX_CMP_OPCODE_SKP=11,
 756         TOE_RX_CMP_OPCODE_URG=12,
 757         TOE_RX_CMP_OPCODE_RT_TO=13,
 758         TOE_RX_CMP_OPCODE_KA_TO=14,
 759         TOE_RX_CMP_OPCODE_MAX_RT=15,
 760         TOE_RX_CMP_OPCODE_DBT_RE=16,
 761         TOE_RX_CMP_OPCODE_SYN=17,
 762         TOE_RX_CMP_OPCODE_OPT_ERR=18,
 763         TOE_RX_CMP_OPCODE_FW2_TO=19,
 764         TOE_RX_CMP_OPCODE_2WY_CLS=20,
 765         TOE_RX_CMP_OPCODE_RST_RCV=21,
 766         TOE_RX_CMP_OPCODE_FIN_RCV=22,
 767         TOE_RX_CMP_OPCODE_FIN_UPL=23,
 768         TOE_RX_CMP_OPCODE_INIT=32,
 769         TOE_RX_CMP_OPCODE_RSS_UPDATE=33,
 770         TOE_RX_CMP_OPCODE_CLOSE=34,
 771         TOE_RX_CMP_OPCODE_INITIATE_OFFLOAD=80,
 772         TOE_RX_CMP_OPCODE_SEARCHER_DELETE=81,
 773         TOE_RX_CMP_OPCODE_TERMINATE=82,
 774         TOE_RX_CMP_OPCODE_QUERY=83,
 775         TOE_RX_CMP_OPCODE_RESET_SEND=84,
 776         TOE_RX_CMP_OPCODE_INVALIDATE=85,
 777         TOE_RX_CMP_OPCODE_EMPTY=86,
 778         TOE_RX_CMP_OPCODE_UPDATE=87,
 779         MAX_TOE_RX_CMP_OPCODE
 780 };
 781
 782
 783 /*
 784  * TOE rx ooo completion data
 785  */
 786 struct toe_rx_cqe_ooo_params
 787 {
 788         __le32 nbytes;
 789         __le16 grq_buff_id /* grq buffer identifier */;
 790         u8 isle_num;
 791         u8 reserved0;
 792 };
 793
 794 /*
 795  * TOE rx in order completion data
 796  */
 797 struct toe_rx_cqe_in_order_params
 798 {
 799         __le32 nbytes;
 800         __le16 grq_buff_id /* grq buffer identifier - applicable only for GA,GR opcodes */;
 801         __le16 reserved1;
 802 };
 803
 804 /*
 805  * Union for TOE rx completion data
 806  */
 807 union toe_rx_cqe_data_union
 808 {
 809         struct toe_rx_cqe_ooo_params ooo_params;
 810         struct toe_rx_cqe_in_order_params in_order_params;
 811         struct regpair raw_data;
 812 };
 813
 814 /*
 815  * TOE rx completion element
 816  */
 817 struct toe_rx_cqe
 818 {
 819         __le16 icid;
 820         u8 completion_opcode;
 821         u8 reserved0;
 822         __le32 reserved1;
 823         union toe_rx_cqe_data_union data;
 824 };
 825
 826
 827
 828
 829
 830 /*
 831  * toe RX doorbel data
 832  */
 833 struct toe_rx_db_data
 834 {
 835         __le32 local_adv_wnd_seq /* Sequence of the right edge of the local advertised window (receive window) */;
 836         __le32 reserved[3];
 837 };
 838
 839
 840 /*
 841  * Toe GRQ buffer descriptor
 842  */
 843 struct toe_rx_grq_bd
 844 {
 845         struct regpair addr /* Address of buffer */;
 846         __le16 buff_id /* buffer indentifier */;
 847         __le16 reserved0;
 848         __le32 reserved1;
 849 };
 850
 851
 852
 853 /*
 854  * Toe transmission application buffer descriptor
 855  */
 856 struct toe_tx_app_buff_desc
 857 {
 858         __le32 next_buffer_start_seq /* Tcp sequence of the first byte in the next application buffer */;
 859         __le32 reserved;
 860 };
 861
 862
 863 /*
 864  * Toe transmission application buffer descriptor page pointer
 865  */
 866 struct toe_tx_app_buff_page_pointer
 867 {
 868         struct regpair next_page_addr /* Address of next page */;
 869 };
 870
 871
 872 /*
 873  * Toe transmission buffer descriptor
 874  */
 875 struct toe_tx_bd
 876 {
 877         struct regpair addr /* Address of buffer */;
 878         __le16 size /* Size of buffer */;
 879         __le16 flags;
 880 #define TOE_TX_BD_PUSH_MASK      0x1 /* Push flag */
 881 #define TOE_TX_BD_PUSH_SHIFT     0
 882 #define TOE_TX_BD_NOTIFY_MASK    0x1 /* Notify flag */
 883 #define TOE_TX_BD_NOTIFY_SHIFT   1
 884 #define TOE_TX_BD_LARGE_IO_MASK  0x1 /* Large IO flag */
 885 #define TOE_TX_BD_LARGE_IO_SHIFT 2
 886 #define TOE_TX_BD_BD_CONS_MASK   0x1FFF /* 13 LSbits of the consumer of this bd for debugging */
 887 #define TOE_TX_BD_BD_CONS_SHIFT  3
 888         __le32 next_bd_start_seq /* Tcp sequence of the first byte in the next buffer */;
 889 };
 890
 891
 892 /*
 893  * TOE completion opcodes
 894  */
 895 enum toe_tx_cmp_opcode
 896 {
 897         TOE_TX_CMP_OPCODE_DATA,
 898         TOE_TX_CMP_OPCODE_TERMINATE,
 899         TOE_TX_CMP_OPCODE_EMPTY,
 900         TOE_TX_CMP_OPCODE_RESET_SEND,
 901         TOE_TX_CMP_OPCODE_INVALIDATE,
 902         TOE_TX_CMP_OPCODE_RST_RCV,
 903         MAX_TOE_TX_CMP_OPCODE
 904 };
 905
 906
 907 /*
 908  * Toe transmission completion element
 909  */
 910 struct toe_tx_cqe
 911 {
 912         __le16 icid /* Connection ID */;
 913         u8 opcode /* Completion opcode */;
 914         u8 reserved;
 915         __le32 size /* Size of completed data */;
 916 };
 917
 918
 919 /*
 920  * Toe transmission page pointer bd
 921  */
 922 struct toe_tx_page_pointer_bd
 923 {
 924         struct regpair next_page_addr /* Address of next page */;
 925         struct regpair prev_page_addr /* Address of previous page */;
 926 };
 927
 928
 929 /*
 930  * Toe transmission completion element page pointer
 931  */
 932 struct toe_tx_page_pointer_cqe
 933 {
 934         struct regpair next_page_addr /* Address of next page */;
 935 };
 936
 937
 938 /*
 939  * toe update parameters
 940  */
 941 struct toe_update_params
 942 {
 943         __le16 flags;
 944 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_MASK  0x1
 945 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 0
 946 #define TOE_UPDATE_PARAMS_RESERVED_MASK                     0x7FFF
 947 #define TOE_UPDATE_PARAMS_RESERVED_SHIFT                    1
 948         __le16 rcv_indication_size;
 949         __le16 reserved1[2];
 950 };
 951
 952
 953 /*
 954  * TOE update ramrod data - DMAed by firmware
 955  */
 956 struct toe_update_ramrod_data
 957 {
 958         struct tcp_update_params tcp_upd_params;
 959         struct toe_update_params toe_upd_params;
 960 };
 961
 962
 963
 964
 965
 966
 967 struct e4_mstorm_toe_conn_ag_ctx
 968 {
 969         u8 byte0 /* cdu_validation */;
 970         u8 byte1 /* state */;
 971         u8 flags0;
 972 #define E4_MSTORM_TOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 973 #define E4_MSTORM_TOE_CONN_AG_CTX_BIT0_SHIFT    0
 974 #define E4_MSTORM_TOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 975 #define E4_MSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT    1
 976 #define E4_MSTORM_TOE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 977 #define E4_MSTORM_TOE_CONN_AG_CTX_CF0_SHIFT     2
 978 #define E4_MSTORM_TOE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 979 #define E4_MSTORM_TOE_CONN_AG_CTX_CF1_SHIFT     4
 980 #define E4_MSTORM_TOE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 981 #define E4_MSTORM_TOE_CONN_AG_CTX_CF2_SHIFT     6
 982         u8 flags1;
 983 #define E4_MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 984 #define E4_MSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT   0
 985 #define E4_MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 986 #define E4_MSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT   1
 987 #define E4_MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 988 #define E4_MSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT   2
 989 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 990 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 3
 991 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 992 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 4
 993 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 994 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 5
 995 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 996 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 6
 997 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 998 #define E4_MSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 7
 999         __le16 word0 /* word0 */;
1000         __le16 word1 /* word1 */;
1001         __le32 reg0 /* reg0 */;
1002         __le32 reg1 /* reg1 */;
1003 };
1004
1005
1006
1007
1008
1009
1010 struct e5_mstorm_toe_conn_ag_ctx
1011 {
1012         u8 byte0 /* cdu_validation */;
1013         u8 byte1 /* state_and_core_id */;
1014         u8 flags0;
1015 #define E5_MSTORM_TOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1016 #define E5_MSTORM_TOE_CONN_AG_CTX_BIT0_SHIFT    0
1017 #define E5_MSTORM_TOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1018 #define E5_MSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT    1
1019 #define E5_MSTORM_TOE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1020 #define E5_MSTORM_TOE_CONN_AG_CTX_CF0_SHIFT     2
1021 #define E5_MSTORM_TOE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1022 #define E5_MSTORM_TOE_CONN_AG_CTX_CF1_SHIFT     4
1023 #define E5_MSTORM_TOE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1024 #define E5_MSTORM_TOE_CONN_AG_CTX_CF2_SHIFT     6
1025         u8 flags1;
1026 #define E5_MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1027 #define E5_MSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT   0
1028 #define E5_MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1029 #define E5_MSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT   1
1030 #define E5_MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1031 #define E5_MSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT   2
1032 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1033 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT 3
1034 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1035 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 4
1036 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1037 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT 5
1038 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1039 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT 6
1040 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1041 #define E5_MSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT 7
1042         __le16 word0 /* word0 */;
1043         __le16 word1 /* word1 */;
1044         __le32 reg0 /* reg0 */;
1045         __le32 reg1 /* reg1 */;
1046 };
1047
1048
1049 struct e5_tstorm_toe_conn_ag_ctx
1050 {
1051         u8 reserved0 /* cdu_validation */;
1052         u8 byte1 /* state_and_core_id */;
1053         u8 flags0;
1054 #define E5_TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
1055 #define E5_TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
1056 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT1_MASK               0x1 /* exist_in_qm1 */
1057 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT              1
1058 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT2_MASK               0x1 /* bit2 */
1059 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT2_SHIFT              2
1060 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT3_MASK               0x1 /* bit3 */
1061 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT3_SHIFT              3
1062 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT4_MASK               0x1 /* bit4 */
1063 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT4_SHIFT              4
1064 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT5_MASK               0x1 /* bit5 */
1065 #define E5_TSTORM_TOE_CONN_AG_CTX_BIT5_SHIFT              5
1066 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK         0x3 /* timer0cf */
1067 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_SHIFT        6
1068         u8 flags1;
1069 #define E5_TSTORM_TOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
1070 #define E5_TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT               0
1071 #define E5_TSTORM_TOE_CONN_AG_CTX_CF2_MASK                0x3 /* timer2cf */
1072 #define E5_TSTORM_TOE_CONN_AG_CTX_CF2_SHIFT               2
1073 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK     0x3 /* timer_stop_all */
1074 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT    4
1075 #define E5_TSTORM_TOE_CONN_AG_CTX_CF4_MASK                0x3 /* cf4 */
1076 #define E5_TSTORM_TOE_CONN_AG_CTX_CF4_SHIFT               6
1077         u8 flags2;
1078 #define E5_TSTORM_TOE_CONN_AG_CTX_CF5_MASK                0x3 /* cf5 */
1079 #define E5_TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT               0
1080 #define E5_TSTORM_TOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
1081 #define E5_TSTORM_TOE_CONN_AG_CTX_CF6_SHIFT               2
1082 #define E5_TSTORM_TOE_CONN_AG_CTX_CF7_MASK                0x3 /* cf7 */
1083 #define E5_TSTORM_TOE_CONN_AG_CTX_CF7_SHIFT               4
1084 #define E5_TSTORM_TOE_CONN_AG_CTX_CF8_MASK                0x3 /* cf8 */
1085 #define E5_TSTORM_TOE_CONN_AG_CTX_CF8_SHIFT               6
1086         u8 flags3;
1087 #define E5_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3 /* cf9 */
1088 #define E5_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
1089 #define E5_TSTORM_TOE_CONN_AG_CTX_CF10_MASK               0x3 /* cf10 */
1090 #define E5_TSTORM_TOE_CONN_AG_CTX_CF10_SHIFT              2
1091 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK      0x1 /* cf0en */
1092 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_SHIFT     4
1093 #define E5_TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
1094 #define E5_TSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT             5
1095 #define E5_TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
1096 #define E5_TSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT             6
1097 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK  0x1 /* cf3en */
1098 #define E5_TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
1099         u8 flags4;
1100 #define E5_TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK              0x1 /* cf4en */
1101 #define E5_TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT             0
1102 #define E5_TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK              0x1 /* cf5en */
1103 #define E5_TSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT             1
1104 #define E5_TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
1105 #define E5_TSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT             2
1106 #define E5_TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK              0x1 /* cf7en */
1107 #define E5_TSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT             3
1108 #define E5_TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK              0x1 /* cf8en */
1109 #define E5_TSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT             4
1110 #define E5_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1 /* cf9en */
1111 #define E5_TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       5
1112 #define E5_TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK             0x1 /* cf10en */
1113 #define E5_TSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT            6
1114 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
1115 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT           7
1116         u8 flags5;
1117 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
1118 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT           0
1119 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
1120 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT           1
1121 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
1122 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT           2
1123 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
1124 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT           3
1125 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
1126 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT           4
1127 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
1128 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT           5
1129 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
1130 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT           6
1131 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK            0x1 /* rule8en */
1132 #define E5_TSTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT           7
1133         u8 flags6;
1134 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED1_MASK       0x1 /* bit6 */
1135 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED1_SHIFT      0
1136 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED2_MASK       0x1 /* bit7 */
1137 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED2_SHIFT      1
1138 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED3_MASK       0x1 /* bit8 */
1139 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED3_SHIFT      2
1140 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED4_MASK       0x3 /* cf11 */
1141 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED4_SHIFT      3
1142 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED5_MASK       0x1 /* cf11en */
1143 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED5_SHIFT      5
1144 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED6_MASK       0x1 /* rule9en */
1145 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED6_SHIFT      6
1146 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED7_MASK       0x1 /* rule10en */
1147 #define E5_TSTORM_TOE_CONN_AG_CTX_E4_RESERVED7_SHIFT      7
1148         u8 byte2 /* byte2 */;
1149         __le16 word0 /* word0 */;
1150         __le32 reg0 /* reg0 */;
1151         __le32 reg1 /* reg1 */;
1152         __le32 reg2 /* reg2 */;
1153         __le32 reg3 /* reg3 */;
1154         __le32 reg4 /* reg4 */;
1155         __le32 reg5 /* reg5 */;
1156         __le32 reg6 /* reg6 */;
1157         __le32 reg7 /* reg7 */;
1158         __le32 reg8 /* reg8 */;
1159 };
1160
1161
1162 struct e5_ustorm_toe_conn_ag_ctx
1163 {
1164         u8 reserved /* cdu_validation */;
1165         u8 byte1 /* state_and_core_id */;
1166         u8 flags0;
1167 #define E5_USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
1168 #define E5_USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
1169 #define E5_USTORM_TOE_CONN_AG_CTX_BIT1_MASK               0x1 /* exist_in_qm1 */
1170 #define E5_USTORM_TOE_CONN_AG_CTX_BIT1_SHIFT              1
1171 #define E5_USTORM_TOE_CONN_AG_CTX_CF0_MASK                0x3 /* timer0cf */
1172 #define E5_USTORM_TOE_CONN_AG_CTX_CF0_SHIFT               2
1173 #define E5_USTORM_TOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
1174 #define E5_USTORM_TOE_CONN_AG_CTX_CF1_SHIFT               4
1175 #define E5_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK      0x3 /* timer2cf */
1176 #define E5_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_SHIFT     6
1177         u8 flags1;
1178 #define E5_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK     0x3 /* timer_stop_all */
1179 #define E5_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT    0
1180 #define E5_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK       0x3 /* cf4 */
1181 #define E5_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT      2
1182 #define E5_USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK              0x3 /* cf5 */
1183 #define E5_USTORM_TOE_CONN_AG_CTX_DQ_CF_SHIFT             4
1184 #define E5_USTORM_TOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
1185 #define E5_USTORM_TOE_CONN_AG_CTX_CF6_SHIFT               6
1186         u8 flags2;
1187 #define E5_USTORM_TOE_CONN_AG_CTX_CF0EN_MASK              0x1 /* cf0en */
1188 #define E5_USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT             0
1189 #define E5_USTORM_TOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
1190 #define E5_USTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT             1
1191 #define E5_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK   0x1 /* cf2en */
1192 #define E5_USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_SHIFT  2
1193 #define E5_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK  0x1 /* cf3en */
1194 #define E5_USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 3
1195 #define E5_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK    0x1 /* cf4en */
1196 #define E5_USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT   4
1197 #define E5_USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1 /* cf5en */
1198 #define E5_USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_SHIFT          5
1199 #define E5_USTORM_TOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
1200 #define E5_USTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT             6
1201 #define E5_USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
1202 #define E5_USTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT           7
1203         u8 flags3;
1204 #define E5_USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
1205 #define E5_USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT           0
1206 #define E5_USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
1207 #define E5_USTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT           1
1208 #define E5_USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
1209 #define E5_USTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT           2
1210 #define E5_USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
1211 #define E5_USTORM_TOE_CONN_AG_CTX_RULE4EN_SHIFT           3
1212 #define E5_USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
1213 #define E5_USTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT           4
1214 #define E5_USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
1215 #define E5_USTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT           5
1216 #define E5_USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
1217 #define E5_USTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT           6
1218 #define E5_USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK            0x1 /* rule8en */
1219 #define E5_USTORM_TOE_CONN_AG_CTX_RULE8EN_SHIFT           7
1220         u8 flags4;
1221 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED1_MASK       0x1 /* bit2 */
1222 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED1_SHIFT      0
1223 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED2_MASK       0x1 /* bit3 */
1224 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED2_SHIFT      1
1225 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED3_MASK       0x3 /* cf7 */
1226 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED3_SHIFT      2
1227 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED4_MASK       0x3 /* cf8 */
1228 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED4_SHIFT      4
1229 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED5_MASK       0x1 /* cf7en */
1230 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED5_SHIFT      6
1231 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED6_MASK       0x1 /* cf8en */
1232 #define E5_USTORM_TOE_CONN_AG_CTX_E4_RESERVED6_SHIFT      7
1233         u8 byte2 /* byte2 */;
1234         __le16 word0 /* conn_dpi */;
1235         __le16 word1 /* word1 */;
1236         __le32 reg0 /* reg0 */;
1237         __le32 reg1 /* reg1 */;
1238         __le32 reg2 /* reg2 */;
1239         __le32 reg3 /* reg3 */;
1240         __le16 word2 /* word2 */;
1241         __le16 word3 /* word3 */;
1242 };
1243
1244
1245 struct e5_xstorm_toe_conn_ag_ctx
1246 {
1247         u8 reserved0 /* cdu_validation */;
1248         u8 state_and_core_id /* state_and_core_id */;
1249         u8 flags0;
1250 #define E5_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
1251 #define E5_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
1252 #define E5_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK          0x1 /* exist_in_qm1 */
1253 #define E5_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_SHIFT         1
1254 #define E5_XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK             0x1 /* exist_in_qm2 */
1255 #define E5_XSTORM_TOE_CONN_AG_CTX_RESERVED1_SHIFT            2
1256 #define E5_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK          0x1 /* exist_in_qm3 */
1257 #define E5_XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT         3
1258 #define E5_XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK       0x1 /* bit4 */
1259 #define E5_XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_SHIFT      4
1260 #define E5_XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK             0x1 /* cf_array_active */
1261 #define E5_XSTORM_TOE_CONN_AG_CTX_RESERVED2_SHIFT            5
1262 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT6_MASK                  0x1 /* bit6 */
1263 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT6_SHIFT                 6
1264 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT7_MASK                  0x1 /* bit7 */
1265 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT7_SHIFT                 7
1266         u8 flags1;
1267 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT8_MASK                  0x1 /* bit8 */
1268 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT                 0
1269 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT9_MASK                  0x1 /* bit9 */
1270 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT9_SHIFT                 1
1271 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT10_MASK                 0x1 /* bit10 */
1272 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT10_SHIFT                2
1273 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT11_MASK                 0x1 /* bit11 */
1274 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT11_SHIFT                3
1275 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT12_MASK                 0x1 /* bit12 */
1276 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT12_SHIFT                4
1277 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT13_MASK                 0x1 /* bit13 */
1278 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT13_SHIFT                5
1279 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT14_MASK                 0x1 /* bit14 */
1280 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT14_SHIFT                6
1281 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT15_MASK                 0x1 /* bit15 */
1282 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT15_SHIFT                7
1283         u8 flags2;
1284 #define E5_XSTORM_TOE_CONN_AG_CTX_CF0_MASK                   0x3 /* timer0cf */
1285 #define E5_XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT                  0
1286 #define E5_XSTORM_TOE_CONN_AG_CTX_CF1_MASK                   0x3 /* timer1cf */
1287 #define E5_XSTORM_TOE_CONN_AG_CTX_CF1_SHIFT                  2
1288 #define E5_XSTORM_TOE_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
1289 #define E5_XSTORM_TOE_CONN_AG_CTX_CF2_SHIFT                  4
1290 #define E5_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK        0x3 /* timer_stop_all */
1291 #define E5_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT       6
1292         u8 flags3;
1293 #define E5_XSTORM_TOE_CONN_AG_CTX_CF4_MASK                   0x3 /* cf4 */
1294 #define E5_XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT                  0
1295 #define E5_XSTORM_TOE_CONN_AG_CTX_CF5_MASK                   0x3 /* cf5 */
1296 #define E5_XSTORM_TOE_CONN_AG_CTX_CF5_SHIFT                  2
1297 #define E5_XSTORM_TOE_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
1298 #define E5_XSTORM_TOE_CONN_AG_CTX_CF6_SHIFT                  4
1299 #define E5_XSTORM_TOE_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
1300 #define E5_XSTORM_TOE_CONN_AG_CTX_CF7_SHIFT                  6
1301         u8 flags4;
1302 #define E5_XSTORM_TOE_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
1303 #define E5_XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT                  0
1304 #define E5_XSTORM_TOE_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
1305 #define E5_XSTORM_TOE_CONN_AG_CTX_CF9_SHIFT                  2
1306 #define E5_XSTORM_TOE_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
1307 #define E5_XSTORM_TOE_CONN_AG_CTX_CF10_SHIFT                 4
1308 #define E5_XSTORM_TOE_CONN_AG_CTX_CF11_MASK                  0x3 /* cf11 */
1309 #define E5_XSTORM_TOE_CONN_AG_CTX_CF11_SHIFT                 6
1310         u8 flags5;
1311 #define E5_XSTORM_TOE_CONN_AG_CTX_CF12_MASK                  0x3 /* cf12 */
1312 #define E5_XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT                 0
1313 #define E5_XSTORM_TOE_CONN_AG_CTX_CF13_MASK                  0x3 /* cf13 */
1314 #define E5_XSTORM_TOE_CONN_AG_CTX_CF13_SHIFT                 2
1315 #define E5_XSTORM_TOE_CONN_AG_CTX_CF14_MASK                  0x3 /* cf14 */
1316 #define E5_XSTORM_TOE_CONN_AG_CTX_CF14_SHIFT                 4
1317 #define E5_XSTORM_TOE_CONN_AG_CTX_CF15_MASK                  0x3 /* cf15 */
1318 #define E5_XSTORM_TOE_CONN_AG_CTX_CF15_SHIFT                 6
1319         u8 flags6;
1320 #define E5_XSTORM_TOE_CONN_AG_CTX_CF16_MASK                  0x3 /* cf16 */
1321 #define E5_XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT                 0
1322 #define E5_XSTORM_TOE_CONN_AG_CTX_CF17_MASK                  0x3 /* cf_array_cf */
1323 #define E5_XSTORM_TOE_CONN_AG_CTX_CF17_SHIFT                 2
1324 #define E5_XSTORM_TOE_CONN_AG_CTX_CF18_MASK                  0x3 /* cf18 */
1325 #define E5_XSTORM_TOE_CONN_AG_CTX_CF18_SHIFT                 4
1326 #define E5_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK              0x3 /* cf19 */
1327 #define E5_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_SHIFT             6
1328         u8 flags7;
1329 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK              0x3 /* cf20 */
1330 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT             0
1331 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK              0x3 /* cf21 */
1332 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_SHIFT             2
1333 #define E5_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK             0x3 /* cf22 */
1334 #define E5_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_SHIFT            4
1335 #define E5_XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK                 0x1 /* cf0en */
1336 #define E5_XSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT                6
1337 #define E5_XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK                 0x1 /* cf1en */
1338 #define E5_XSTORM_TOE_CONN_AG_CTX_CF1EN_SHIFT                7
1339         u8 flags8;
1340 #define E5_XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
1341 #define E5_XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT                0
1342 #define E5_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK     0x1 /* cf3en */
1343 #define E5_XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT    1
1344 #define E5_XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK                 0x1 /* cf4en */
1345 #define E5_XSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT                2
1346 #define E5_XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK                 0x1 /* cf5en */
1347 #define E5_XSTORM_TOE_CONN_AG_CTX_CF5EN_SHIFT                3
1348 #define E5_XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
1349 #define E5_XSTORM_TOE_CONN_AG_CTX_CF6EN_SHIFT                4
1350 #define E5_XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
1351 #define E5_XSTORM_TOE_CONN_AG_CTX_CF7EN_SHIFT                5
1352 #define E5_XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
1353 #define E5_XSTORM_TOE_CONN_AG_CTX_CF8EN_SHIFT                6
1354 #define E5_XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
1355 #define E5_XSTORM_TOE_CONN_AG_CTX_CF9EN_SHIFT                7
1356         u8 flags9;
1357 #define E5_XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
1358 #define E5_XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT               0
1359 #define E5_XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK                0x1 /* cf11en */
1360 #define E5_XSTORM_TOE_CONN_AG_CTX_CF11EN_SHIFT               1
1361 #define E5_XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK                0x1 /* cf12en */
1362 #define E5_XSTORM_TOE_CONN_AG_CTX_CF12EN_SHIFT               2
1363 #define E5_XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK                0x1 /* cf13en */
1364 #define E5_XSTORM_TOE_CONN_AG_CTX_CF13EN_SHIFT               3
1365 #define E5_XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK                0x1 /* cf14en */
1366 #define E5_XSTORM_TOE_CONN_AG_CTX_CF14EN_SHIFT               4
1367 #define E5_XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK                0x1 /* cf15en */
1368 #define E5_XSTORM_TOE_CONN_AG_CTX_CF15EN_SHIFT               5
1369 #define E5_XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK                0x1 /* cf16en */
1370 #define E5_XSTORM_TOE_CONN_AG_CTX_CF16EN_SHIFT               6
1371 #define E5_XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK                0x1 /* cf_array_cf_en */
1372 #define E5_XSTORM_TOE_CONN_AG_CTX_CF17EN_SHIFT               7
1373         u8 flags10;
1374 #define E5_XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK                0x1 /* cf18en */
1375 #define E5_XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT               0
1376 #define E5_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK           0x1 /* cf19en */
1377 #define E5_XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT          1
1378 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK           0x1 /* cf20en */
1379 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT          2
1380 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK           0x1 /* cf21en */
1381 #define E5_XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT          3
1382 #define E5_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK          0x1 /* cf22en */
1383 #define E5_XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT         4
1384 #define E5_XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK                0x1 /* cf23en */
1385 #define E5_XSTORM_TOE_CONN_AG_CTX_CF23EN_SHIFT               5
1386 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
1387 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE0EN_SHIFT              6
1388 #define E5_XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK  0x1 /* rule1en */
1389 #define E5_XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
1390         u8 flags11;
1391 #define E5_XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK         0x1 /* rule2en */
1392 #define E5_XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT        0
1393 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
1394 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT              1
1395 #define E5_XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK             0x1 /* rule4en */
1396 #define E5_XSTORM_TOE_CONN_AG_CTX_RESERVED3_SHIFT            2
1397 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
1398 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE5EN_SHIFT              3
1399 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
1400 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE6EN_SHIFT              4
1401 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
1402 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE7EN_SHIFT              5
1403 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK          0x1 /* rule8en */
1404 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_SHIFT         6
1405 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK               0x1 /* rule9en */
1406 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE9EN_SHIFT              7
1407         u8 flags12;
1408 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK              0x1 /* rule10en */
1409 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT             0
1410 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK              0x1 /* rule11en */
1411 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE11EN_SHIFT             1
1412 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK          0x1 /* rule12en */
1413 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_SHIFT         2
1414 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK          0x1 /* rule13en */
1415 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_SHIFT         3
1416 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK              0x1 /* rule14en */
1417 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE14EN_SHIFT             4
1418 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK              0x1 /* rule15en */
1419 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE15EN_SHIFT             5
1420 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK              0x1 /* rule16en */
1421 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE16EN_SHIFT             6
1422 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK              0x1 /* rule17en */
1423 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE17EN_SHIFT             7
1424         u8 flags13;
1425 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK              0x1 /* rule18en */
1426 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT             0
1427 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK              0x1 /* rule19en */
1428 #define E5_XSTORM_TOE_CONN_AG_CTX_RULE19EN_SHIFT             1
1429 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK          0x1 /* rule20en */
1430 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_SHIFT         2
1431 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK          0x1 /* rule21en */
1432 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_SHIFT         3
1433 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK          0x1 /* rule22en */
1434 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_SHIFT         4
1435 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK          0x1 /* rule23en */
1436 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_SHIFT         5
1437 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK          0x1 /* rule24en */
1438 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_SHIFT         6
1439 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK          0x1 /* rule25en */
1440 #define E5_XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_SHIFT         7
1441         u8 flags14;
1442 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT16_MASK                 0x1 /* bit16 */
1443 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT                0
1444 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT17_MASK                 0x1 /* bit17 */
1445 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT17_SHIFT                1
1446 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT18_MASK                 0x1 /* bit18 */
1447 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT18_SHIFT                2
1448 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT19_MASK                 0x1 /* bit19 */
1449 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT19_SHIFT                3
1450 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT20_MASK                 0x1 /* bit20 */
1451 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT20_SHIFT                4
1452 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT21_MASK                 0x1 /* bit21 */
1453 #define E5_XSTORM_TOE_CONN_AG_CTX_BIT21_SHIFT                5
1454 #define E5_XSTORM_TOE_CONN_AG_CTX_CF23_MASK                  0x3 /* cf23 */
1455 #define E5_XSTORM_TOE_CONN_AG_CTX_CF23_SHIFT                 6
1456         u8 byte2 /* byte2 */;
1457         __le16 physical_q0 /* physical_q0 */;
1458         __le16 physical_q1 /* physical_q1 */;
1459         __le16 word2 /* physical_q2 */;
1460         __le16 word3 /* word3 */;
1461         __le16 bd_prod /* word4 */;
1462         __le16 word5 /* word5 */;
1463         __le16 word6 /* conn_dpi */;
1464         u8 byte3 /* byte3 */;
1465         u8 byte4 /* byte4 */;
1466         u8 byte5 /* byte5 */;
1467         u8 byte6 /* byte6 */;
1468         __le32 reg0 /* reg0 */;
1469         __le32 reg1 /* reg1 */;
1470         __le32 reg2 /* reg2 */;
1471         __le32 more_to_send_seq /* reg3 */;
1472         __le32 local_adv_wnd_seq /* reg4 */;
1473         __le32 reg5 /* cf_array0 */;
1474         __le32 reg6 /* cf_array1 */;
1475         u8 flags15;
1476 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED1_MASK          0x1 /* bit22 */
1477 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED1_SHIFT         0
1478 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED2_MASK          0x1 /* bit23 */
1479 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED2_SHIFT         1
1480 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED3_MASK          0x1 /* bit24 */
1481 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED3_SHIFT         2
1482 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED4_MASK          0x3 /* cf24 */
1483 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED4_SHIFT         3
1484 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED5_MASK          0x1 /* cf24en */
1485 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED5_SHIFT         5
1486 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED6_MASK          0x1 /* rule26en */
1487 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED6_SHIFT         6
1488 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED7_MASK          0x1 /* rule27en */
1489 #define E5_XSTORM_TOE_CONN_AG_CTX_E4_RESERVED7_SHIFT         7
1490         u8 byte7 /* byte7 */;
1491         __le16 word7 /* word7 */;
1492         __le16 word8 /* word8 */;
1493         __le16 word9 /* word9 */;
1494         __le16 word10 /* word10 */;
1495         __le16 word11 /* word11 */;
1496         __le32 reg7 /* reg7 */;
1497         __le32 reg8 /* reg8 */;
1498         __le32 reg9 /* reg9 */;
1499         u8 byte8 /* byte8 */;
1500         u8 byte9 /* byte9 */;
1501         u8 byte10 /* byte10 */;
1502         u8 byte11 /* byte11 */;
1503         u8 byte12 /* byte12 */;
1504         u8 byte13 /* byte13 */;
1505         u8 byte14 /* byte14 */;
1506         u8 byte15 /* byte15 */;
1507         __le32 reg10 /* reg10 */;
1508         __le32 reg11 /* reg11 */;
1509         __le32 reg12 /* reg12 */;
1510         __le32 reg13 /* reg13 */;
1511         __le32 reg14 /* reg14 */;
1512         __le32 reg15 /* reg15 */;
1513         __le32 reg16 /* reg16 */;
1514         __le32 reg17 /* reg17 */;
1515 };
1516
1517
1518 struct e5_ystorm_toe_conn_ag_ctx
1519 {
1520         u8 byte0 /* cdu_validation */;
1521         u8 byte1 /* state_and_core_id */;
1522         u8 flags0;
1523 #define E5_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
1524 #define E5_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
1525 #define E5_YSTORM_TOE_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
1526 #define E5_YSTORM_TOE_CONN_AG_CTX_BIT1_SHIFT                 1
1527 #define E5_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK          0x3 /* cf0 */
1528 #define E5_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_SHIFT         2
1529 #define E5_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK     0x3 /* cf1 */
1530 #define E5_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_SHIFT    4
1531 #define E5_YSTORM_TOE_CONN_AG_CTX_CF2_MASK                   0x3 /* cf2 */
1532 #define E5_YSTORM_TOE_CONN_AG_CTX_CF2_SHIFT                  6
1533         u8 flags1;
1534 #define E5_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK       0x1 /* cf0en */
1535 #define E5_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT      0
1536 #define E5_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK  0x1 /* cf1en */
1537 #define E5_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_SHIFT 1
1538 #define E5_YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
1539 #define E5_YSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT                2
1540 #define E5_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK            0x1 /* rule0en */
1541 #define E5_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_SHIFT           3
1542 #define E5_YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
1543 #define E5_YSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT              4
1544 #define E5_YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
1545 #define E5_YSTORM_TOE_CONN_AG_CTX_RULE2EN_SHIFT              5
1546 #define E5_YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
1547 #define E5_YSTORM_TOE_CONN_AG_CTX_RULE3EN_SHIFT              6
1548 #define E5_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK          0x1 /* rule4en */
1549 #define E5_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_SHIFT         7
1550         u8 completion_opcode /* byte2 */;
1551         u8 byte3 /* byte3 */;
1552         __le16 word0 /* word0 */;
1553         __le32 rel_seq /* reg0 */;
1554         __le32 rel_seq_threshold /* reg1 */;
1555         __le16 app_prod /* word1 */;
1556         __le16 app_cons /* word2 */;
1557         __le16 word3 /* word3 */;
1558         __le16 word4 /* word4 */;
1559         __le32 reg2 /* reg2 */;
1560         __le32 reg3 /* reg3 */;
1561 };
1562
1563
1564 /*
1565  * TOE doorbell data
1566  */
1567 struct toe_db_data
1568 {
1569         u8 params;
1570 #define TOE_DB_DATA_DEST_MASK         0x3 /* destination of doorbell (use enum db_dest) */
1571 #define TOE_DB_DATA_DEST_SHIFT        0
1572 #define TOE_DB_DATA_AGG_CMD_MASK      0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */
1573 #define TOE_DB_DATA_AGG_CMD_SHIFT     2
1574 #define TOE_DB_DATA_BYPASS_EN_MASK    0x1 /* enable QM bypass */
1575 #define TOE_DB_DATA_BYPASS_EN_SHIFT   4
1576 #define TOE_DB_DATA_RESERVED_MASK     0x1
1577 #define TOE_DB_DATA_RESERVED_SHIFT    5
1578 #define TOE_DB_DATA_AGG_VAL_SEL_MASK  0x3 /* aggregative value selection */
1579 #define TOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
1580         u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */;
1581         __le16 bd_prod;
1582 };
1583
1584 #endif /* __ECORE_HSI_TOE__ */