usr/src/uts/common/io/qede/579xx/drivers/ecore/hsi_repository/ecore_hsi_fcoe.h

   1 /*
   2 * CDDL HEADER START
   3 *
   4 * The contents of this file are subject to the terms of the
   5 * Common Development and Distribution License, v.1,  (the "License").
   6 * You may not use this file except in compliance with the License.
   7 *
   8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9 * or http://opensource.org/licenses/CDDL-1.0.
  10 * See the License for the specific language governing permissions
  11 * and limitations under the License.
  12 *
  13 * When distributing Covered Code, include this CDDL HEADER in each
  14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15 * If applicable, add the following below this CDDL HEADER, with the
  16 * fields enclosed by brackets "[]" replaced with your own identifying
  17 * information: Portions Copyright [yyyy] [name of copyright owner]
  18 *
  19 * CDDL HEADER END
  20 */
  21
  22 /*
  23 * Copyright 2014-2017 Cavium, Inc.
  24 * The contents of this file are subject to the terms of the Common Development
  25 * and Distribution License, v.1,  (the "License").
  26
  27 * You may not use this file except in compliance with the License.
  28
  29 * You can obtain a copy of the License at available
  30 * at http://opensource.org/licenses/CDDL-1.0
  31
  32 * See the License for the specific language governing permissions and
  33 * limitations under the License.
  34 */
  35
  36 #ifndef __ECORE_HSI_FCOE__
  37 #define __ECORE_HSI_FCOE__
  38 /****************************************/
  39 /* Add include to common storage target */
  40 /****************************************/
  41 #include "storage_common.h"
  42
  43 /************************************************************************/
  44 /* Add include to common fcoe target for both eCore and protocol driver */
  45 /************************************************************************/
  46 #include "fcoe_common.h"
  47
  48
  49 /*
  50  * The fcoe storm context of Ystorm
  51  */
  52 struct ystorm_fcoe_conn_st_ctx
  53 {
  54         u8 func_mode /* Function mode */;
  55         u8 cos /* Transmission cos */;
  56         u8 conf_version /* Is dcb_version or vntag_version changed */;
  57         u8 eth_hdr_size /* Ethernet header size */;
  58         __le16 stat_ram_addr /* Statistics ram adderss */;
  59         __le16 mtu /* MTU limitation */;
  60         __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. 8 bytes aligned (required for protection fast-path) */;
  61         __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */;
  62         u8 fcp_cmd_size /* FCP cmd size. for performance reasons */;
  63         u8 fcp_rsp_size /* FCP RSP size. for performance reasons */;
  64         __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */;
  65         struct regpair reserved;
  66         __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header) */;
  67         u8 protection_info_flags;
  68 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK  0x1 /* Does this connection support protection (if couple of GOS share this connection it× â‚¬â„¢s enough that one of them support protection) */
  69 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
  70 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK               0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can× â‚¬â„¢t rely on this size × â‚¬â€œ it depends on vlan num) */
  71 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT              1
  72 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK           0x3F
  73 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT          2
  74         u8 dst_protection_per_mss /* Destination Protection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */;
  75         u8 src_protection_per_mss /* Source Protection data per mss (if we are not in perf mode it will be worse case). Source  is the data validated by the nic  (as opposed to destination which is data add/remove from the transmitted packet they might not be identical) */;
  76         u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */;
  77         u8 flags;
  78 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK     0x1 /* Inner Vlan flag */
  79 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT    0
  80 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK     0x1 /* Outer Vlan flag */
  81 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT    1
  82 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK                0x3F
  83 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT               2
  84         u8 fcp_xfer_size /* FCP xfer size. for performance reasons */;
  85 };
  86
  87 /*
  88  * FCoE 16-bits vlan structure
  89  */
  90 struct fcoe_vlan_fields
  91 {
  92         __le16 fields;
  93 #define FCOE_VLAN_FIELDS_VID_MASK  0xFFF
  94 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
  95 #define FCOE_VLAN_FIELDS_CLI_MASK  0x1
  96 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
  97 #define FCOE_VLAN_FIELDS_PRI_MASK  0x7
  98 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
  99 };
 100
 101 /*
 102  * FCoE 16-bits vlan union
 103  */
 104 union fcoe_vlan_field_union
 105 {
 106         struct fcoe_vlan_fields fields /* Parameters field */;
 107         __le16 val /* Global value */;
 108 };
 109
 110 /*
 111  * FCoE 16-bits vlan, vif union
 112  */
 113 union fcoe_vlan_vif_field_union
 114 {
 115         union fcoe_vlan_field_union vlan /* Vlan */;
 116         __le16 vif /* VIF */;
 117 };
 118
 119 /*
 120  * Ethernet context section
 121  */
 122 struct pstorm_fcoe_eth_context_section
 123 {
 124         u8 remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */;
 125         u8 remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */;
 126         u8 remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */;
 127         u8 remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */;
 128         u8 local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */;
 129         u8 local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */;
 130         u8 remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */;
 131         u8 remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */;
 132         u8 local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */;
 133         u8 local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */;
 134         u8 local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */;
 135         u8 local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */;
 136         union fcoe_vlan_vif_field_union vif_outer_vlan /* Union of VIF and outer vlan */;
 137         __le16 vif_outer_eth_type /* reserved place for Ethernet type */;
 138         union fcoe_vlan_vif_field_union inner_vlan /* inner vlan tag */;
 139         __le16 inner_eth_type /* reserved place for Ethernet type */;
 140 };
 141
 142 /*
 143  * The fcoe storm context of Pstorm
 144  */
 145 struct pstorm_fcoe_conn_st_ctx
 146 {
 147         u8 func_mode /* Function mode */;
 148         u8 cos /* Transmission cos */;
 149         u8 conf_version /* Is dcb_version or vntag_version changed */;
 150         u8 rsrv;
 151         __le16 stat_ram_addr /* Statistics ram adderss */;
 152         __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */;
 153         struct regpair abts_cleanup_addr /* Host addr of ABTS /Cleanup info. since we pass it  through session context, we pass only the addr to save space */;
 154         struct pstorm_fcoe_eth_context_section eth /* Source mac */;
 155         u8 sid_2 /* SID FC address - Third byte that is sent to NW via PBF For example is SID is 01:02:03 then sid_2 is 0x03 */;
 156         u8 sid_1 /* SID FC address - Second byte that is sent to NW via PBF */;
 157         u8 sid_0 /* SID FC address - First byte that is sent to NW via PBF */;
 158         u8 flags;
 159 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK          0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */
 160 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT         0
 161 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK  0x1 /* AreSupport rec_tov timer */
 162 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
 163 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK     0x1 /* Inner Vlan flag */
 164 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT    2
 165 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK     0x1 /* Outer Vlan flag */
 166 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT    3
 167 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK            0xF
 168 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT           4
 169         u8 did_2 /* DID FC address - Third byte that is sent to NW via PBF */;
 170         u8 did_1 /* DID FC address - Second byte that is sent to NW via PBF */;
 171         u8 did_0 /* DID FC address - First byte that is sent to NW via PBF */;
 172         u8 src_mac_index;
 173         __le16 rec_rr_tov_val /* REC_TOV value negotiated during PLOGI (in msec) */;
 174         u8 q_relative_offset /* CQ, RQ (and CMDQ) relative offset for connection */;
 175         u8 reserved1;
 176 };
 177
 178 /*
 179  * The fcoe storm context of Xstorm
 180  */
 181 struct xstorm_fcoe_conn_st_ctx
 182 {
 183         u8 func_mode /* Function mode */;
 184         u8 src_mac_index /* Index to the src_mac arr held in the xStorm RAM. Provided at the xStorm offload connection handler */;
 185         u8 conf_version /* Advance if vntag/dcb version advance */;
 186         u8 cached_wqes_avail /* Number of cached wqes available */;
 187         __le16 stat_ram_addr /* Statistics ram adderss */;
 188         u8 flags;
 189 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK             0x1 /* SQ deferred (happens when we wait for xfer wqe to complete cleanup/abts */
 190 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT            0
 191 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK         0x1 /* Inner vlan flag â€  for calculating eth header size */
 192 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT        1
 193 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK    0x1 /* Original vlan configuration. used when we switch from dcb enable to dcb disabled */
 194 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT   2
 195 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK      0x3
 196 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT     3
 197 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK                    0x7
 198 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT                   5
 199         u8 cached_wqes_offset /* Offset of first valid cached wqe */;
 200         u8 reserved2;
 201         u8 eth_hdr_size /* Ethernet header size */;
 202         u8 seq_id /* Sequence id */;
 203         u8 max_conc_seqs /* Max concurrent sequence id */;
 204         __le16 num_pages_in_pbl /* Num of pages in SQ/RESPQ/XFERQ Pbl */;
 205         __le16 reserved;
 206         struct regpair sq_pbl_addr /* SQ address */;
 207         struct regpair sq_curr_page_addr /* SQ current page address */;
 208         struct regpair sq_next_page_addr /* SQ next page address */;
 209         struct regpair xferq_pbl_addr /* XFERQ address */;
 210         struct regpair xferq_curr_page_addr /* XFERQ current page address */;
 211         struct regpair xferq_next_page_addr /* XFERQ next page address */;
 212         struct regpair respq_pbl_addr /* RESPQ address */;
 213         struct regpair respq_curr_page_addr /* RESPQ current page address */;
 214         struct regpair respq_next_page_addr /* RESPQ next page address */;
 215         __le16 mtu /* MTU limitation */;
 216         __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */;
 217         __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. Aligned to 4 bytes. */;
 218         __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header, excluding ETH CRC */;
 219         __le16 sq_pbl_next_index /* Next index of SQ Pbl */;
 220         __le16 respq_pbl_next_index /* Next index of RESPQ Pbl */;
 221         u8 fcp_cmd_byte_credit /* Pre-calculated byte credit that single FCP command can consume */;
 222         u8 fcp_rsp_byte_credit /* Pre-calculated byte credit that single FCP RSP can consume. */;
 223         __le16 protection_info;
 224 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK         0x1 /* Intend to accelerate the protection flows */
 225 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT        0
 226 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK      0x1 /* Does this connection support protection (if couple of GOS share this connection is enough that one of them support protection) */
 227 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT     1
 228 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK                   0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we canâ€™t rely on this size â€  it depends on vlan num) */
 229 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT                  2
 230 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK      0x1 /* Is size of tx_max_pay_len_prot can be aligned to protection intervals. This means that pure data in each frame is 2k exactly, and protection intervals are no bigger than 2k */
 231 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT     3
 232 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK               0xF
 233 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT              4
 234 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK  0xFF /* Destination Pro tection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */
 235 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
 236         __le16 xferq_pbl_next_index /* Next index of XFERQ Pbl */;
 237         __le16 page_size /* Page size (in bytes) */;
 238         u8 mid_seq /* Equals 1 for Middle sequence indication, otherwise 0 */;
 239         u8 fcp_xfer_byte_credit /* Pre-calculated byte credit that single FCP command can consume */;
 240         u8 reserved1[2];
 241         struct fcoe_wqe cached_wqes[16] /* cached wqe (8) = 8*8*8Bytes */;
 242 };
 243
 244 struct e4_xstorm_fcoe_conn_ag_ctx
 245 {
 246         u8 reserved0 /* cdu_validation */;
 247         u8 fcoe_state /* state */;
 248         u8 flags0;
 249 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
 250 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
 251 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK          0x1 /* exist_in_qm1 */
 252 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT         1
 253 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK          0x1 /* exist_in_qm2 */
 254 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT         2
 255 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK       0x1 /* exist_in_qm3 */
 256 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT      3
 257 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK          0x1 /* bit4 */
 258 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT         4
 259 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK          0x1 /* cf_array_active */
 260 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT         5
 261 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK          0x1 /* bit6 */
 262 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT         6
 263 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK          0x1 /* bit7 */
 264 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT         7
 265         u8 flags1;
 266 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK          0x1 /* bit8 */
 267 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT         0
 268 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK          0x1 /* bit9 */
 269 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT         1
 270 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK          0x1 /* bit10 */
 271 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT         2
 272 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK              0x1 /* bit11 */
 273 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT             3
 274 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK              0x1 /* bit12 */
 275 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT             4
 276 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK              0x1 /* bit13 */
 277 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT             5
 278 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK              0x1 /* bit14 */
 279 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT             6
 280 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK              0x1 /* bit15 */
 281 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT             7
 282         u8 flags2;
 283 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK                0x3 /* timer0cf */
 284 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT               0
 285 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
 286 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT               2
 287 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK                0x3 /* timer2cf */
 288 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT               4
 289 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK                0x3 /* timer_stop_all */
 290 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT               6
 291         u8 flags3;
 292 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK                0x3 /* cf4 */
 293 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT               0
 294 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK                0x3 /* cf5 */
 295 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT               2
 296 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
 297 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT               4
 298 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK                0x3 /* cf7 */
 299 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT               6
 300         u8 flags4;
 301 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK                0x3 /* cf8 */
 302 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT               0
 303 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK                0x3 /* cf9 */
 304 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT               2
 305 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK               0x3 /* cf10 */
 306 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT              4
 307 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK               0x3 /* cf11 */
 308 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT              6
 309         u8 flags5;
 310 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK               0x3 /* cf12 */
 311 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT              0
 312 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK               0x3 /* cf13 */
 313 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT              2
 314 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK               0x3 /* cf14 */
 315 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT              4
 316 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK               0x3 /* cf15 */
 317 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT              6
 318         u8 flags6;
 319 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK               0x3 /* cf16 */
 320 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT              0
 321 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK               0x3 /* cf_array_cf */
 322 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT              2
 323 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK               0x3 /* cf18 */
 324 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT              4
 325 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK              0x3 /* cf19 */
 326 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT             6
 327         u8 flags7;
 328 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3 /* cf20 */
 329 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
 330 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK         0x3 /* cf21 */
 331 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT        2
 332 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK          0x3 /* cf22 */
 333 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT         4
 334 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK              0x1 /* cf0en */
 335 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT             6
 336 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
 337 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT             7
 338         u8 flags8;
 339 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
 340 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT             0
 341 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK              0x1 /* cf3en */
 342 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT             1
 343 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK              0x1 /* cf4en */
 344 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT             2
 345 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK              0x1 /* cf5en */
 346 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT             3
 347 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
 348 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT             4
 349 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK              0x1 /* cf7en */
 350 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT             5
 351 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK              0x1 /* cf8en */
 352 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT             6
 353 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK              0x1 /* cf9en */
 354 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT             7
 355         u8 flags9;
 356 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK             0x1 /* cf10en */
 357 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT            0
 358 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK             0x1 /* cf11en */
 359 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT            1
 360 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK             0x1 /* cf12en */
 361 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT            2
 362 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK             0x1 /* cf13en */
 363 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT            3
 364 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK             0x1 /* cf14en */
 365 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT            4
 366 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK             0x1 /* cf15en */
 367 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT            5
 368 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK             0x1 /* cf16en */
 369 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT            6
 370 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK             0x1 /* cf_array_cf_en */
 371 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT            7
 372         u8 flags10;
 373 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK             0x1 /* cf18en */
 374 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT            0
 375 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1 /* cf19en */
 376 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT          1
 377 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1 /* cf20en */
 378 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       2
 379 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK         0x1 /* cf21en */
 380 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT        3
 381 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK       0x1 /* cf22en */
 382 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT      4
 383 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK             0x1 /* cf23en */
 384 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT            5
 385 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK         0x1 /* rule0en */
 386 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT        6
 387 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK         0x1 /* rule1en */
 388 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT        7
 389         u8 flags11;
 390 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK         0x1 /* rule2en */
 391 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT        0
 392 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK         0x1 /* rule3en */
 393 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT        1
 394 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK         0x1 /* rule4en */
 395 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT        2
 396 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
 397 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT           3
 398 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
 399 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT           4
 400 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
 401 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT           5
 402 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK       0x1 /* rule8en */
 403 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT      6
 404 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK  0x1 /* rule9en */
 405 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
 406         u8 flags12;
 407 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK     0x1 /* rule10en */
 408 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT    0
 409 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK           0x1 /* rule11en */
 410 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT          1
 411 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK       0x1 /* rule12en */
 412 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT      2
 413 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK       0x1 /* rule13en */
 414 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT      3
 415 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK           0x1 /* rule14en */
 416 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT          4
 417 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK           0x1 /* rule15en */
 418 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT          5
 419 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK           0x1 /* rule16en */
 420 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT          6
 421 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK           0x1 /* rule17en */
 422 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT          7
 423         u8 flags13;
 424 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK  0x1 /* rule18en */
 425 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
 426 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK           0x1 /* rule19en */
 427 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT          1
 428 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK       0x1 /* rule20en */
 429 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT      2
 430 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK       0x1 /* rule21en */
 431 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT      3
 432 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK       0x1 /* rule22en */
 433 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT      4
 434 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK       0x1 /* rule23en */
 435 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT      5
 436 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK       0x1 /* rule24en */
 437 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT      6
 438 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK       0x1 /* rule25en */
 439 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT      7
 440         u8 flags14;
 441 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK              0x1 /* bit16 */
 442 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT             0
 443 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK              0x1 /* bit17 */
 444 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT             1
 445 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK              0x1 /* bit18 */
 446 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT             2
 447 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK              0x1 /* bit19 */
 448 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT             3
 449 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK              0x1 /* bit20 */
 450 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT             4
 451 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK              0x1 /* bit21 */
 452 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT             5
 453 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK               0x3 /* cf23 */
 454 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT              6
 455         u8 byte2 /* byte2 */;
 456         __le16 physical_q0 /* physical_q0 */;
 457         __le16 word1 /* physical_q1 */;
 458         __le16 word2 /* physical_q2 */;
 459         __le16 sq_cons /* word3 */;
 460         __le16 sq_prod /* word4 */;
 461         __le16 xferq_prod /* word5 */;
 462         __le16 xferq_cons /* conn_dpi */;
 463         u8 byte3 /* byte3 */;
 464         u8 byte4 /* byte4 */;
 465         u8 byte5 /* byte5 */;
 466         u8 byte6 /* byte6 */;
 467         __le32 remain_io /* reg0 */;
 468         __le32 reg1 /* reg1 */;
 469         __le32 reg2 /* reg2 */;
 470         __le32 reg3 /* reg3 */;
 471         __le32 reg4 /* reg4 */;
 472         __le32 reg5 /* cf_array0 */;
 473         __le32 reg6 /* cf_array1 */;
 474         __le16 respq_prod /* word7 */;
 475         __le16 respq_cons /* word8 */;
 476         __le16 word9 /* word9 */;
 477         __le16 word10 /* word10 */;
 478         __le32 reg7 /* reg7 */;
 479         __le32 reg8 /* reg8 */;
 480 };
 481
 482 /*
 483  * The fcoe storm context of Ustorm
 484  */
 485 struct ustorm_fcoe_conn_st_ctx
 486 {
 487         struct regpair respq_pbl_addr /* RespQ Pbl base address */;
 488         __le16 num_pages_in_pbl /* Number of RespQ pbl pages (both have same wqe size) */;
 489         u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */;
 490         u8 log_page_size;
 491         __le16 respq_prod /* RespQ producer */;
 492         u8 reserved[2];
 493 };
 494
 495 struct e4_tstorm_fcoe_conn_ag_ctx
 496 {
 497         u8 reserved0 /* cdu_validation */;
 498         u8 fcoe_state /* state */;
 499         u8 flags0;
 500 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
 501 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
 502 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
 503 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT                 1
 504 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK                  0x1 /* bit2 */
 505 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT                 2
 506 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK                  0x1 /* bit3 */
 507 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT                 3
 508 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK                  0x1 /* bit4 */
 509 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT                 4
 510 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK                  0x1 /* bit5 */
 511 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT                 5
 512 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK        0x3 /* timer0cf */
 513 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT       6
 514         u8 flags1;
 515 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3 /* timer1cf */
 516 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          0
 517 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
 518 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT                  2
 519 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3 /* timer_stop_all */
 520 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
 521 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK                   0x3 /* cf4 */
 522 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT                  6
 523         u8 flags2;
 524 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK                   0x3 /* cf5 */
 525 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT                  0
 526 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
 527 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT                  2
 528 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
 529 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT                  4
 530 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
 531 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT                  6
 532         u8 flags3;
 533 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
 534 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT                  0
 535 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
 536 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT                 2
 537 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK     0x1 /* cf0en */
 538 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT    4
 539 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1 /* cf1en */
 540 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       5
 541 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
 542 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT                6
 543 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1 /* cf3en */
 544 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
 545         u8 flags4;
 546 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK                 0x1 /* cf4en */
 547 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT                0
 548 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK                 0x1 /* cf5en */
 549 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT                1
 550 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
 551 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT                2
 552 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
 553 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT                3
 554 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
 555 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT                4
 556 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
 557 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT                5
 558 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
 559 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT               6
 560 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
 561 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT              7
 562         u8 flags5;
 563 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
 564 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT              0
 565 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
 566 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT              1
 567 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
 568 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT              2
 569 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK               0x1 /* rule4en */
 570 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT              3
 571 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
 572 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT              4
 573 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
 574 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT              5
 575 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
 576 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT              6
 577 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK               0x1 /* rule8en */
 578 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT              7
 579         __le32 reg0 /* reg0 */;
 580         __le32 reg1 /* reg1 */;
 581 };
 582
 583 struct e4_ustorm_fcoe_conn_ag_ctx
 584 {
 585         u8 byte0 /* cdu_validation */;
 586         u8 byte1 /* state */;
 587         u8 flags0;
 588 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 589 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT    0
 590 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 591 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT    1
 592 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK      0x3 /* timer0cf */
 593 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT     2
 594 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK      0x3 /* timer1cf */
 595 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT     4
 596 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK      0x3 /* timer2cf */
 597 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT     6
 598         u8 flags1;
 599 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
 600 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT     0
 601 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK      0x3 /* cf4 */
 602 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT     2
 603 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK      0x3 /* cf5 */
 604 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT     4
 605 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK      0x3 /* cf6 */
 606 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT     6
 607         u8 flags2;
 608 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 609 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT   0
 610 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 611 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT   1
 612 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 613 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT   2
 614 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
 615 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT   3
 616 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
 617 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT   4
 618 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
 619 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT   5
 620 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
 621 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT   6
 622 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 623 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
 624         u8 flags3;
 625 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 626 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
 627 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 628 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
 629 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 630 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
 631 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 632 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
 633 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
 634 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
 635 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK  0x1 /* rule6en */
 636 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
 637 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK  0x1 /* rule7en */
 638 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
 639 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK  0x1 /* rule8en */
 640 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
 641         u8 byte2 /* byte2 */;
 642         u8 byte3 /* byte3 */;
 643         __le16 word0 /* conn_dpi */;
 644         __le16 word1 /* word1 */;
 645         __le32 reg0 /* reg0 */;
 646         __le32 reg1 /* reg1 */;
 647         __le32 reg2 /* reg2 */;
 648         __le32 reg3 /* reg3 */;
 649         __le16 word2 /* word2 */;
 650         __le16 word3 /* word3 */;
 651 };
 652
 653 /*
 654  * The fcoe storm context of Tstorm
 655  */
 656 struct tstorm_fcoe_conn_st_ctx
 657 {
 658         __le16 stat_ram_addr /* Statistics ram adderss */;
 659         __le16 rx_max_fc_payload_len /* Max rx fc payload length. provided in ramrod */;
 660         __le16 e_d_tov_val /* E_D_TOV value negotiated during PLOGI (in msec) */;
 661         u8 flags;
 662 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK   0x1 /* Does the target support increment sequence counter */
 663 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT  0
 664 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK  0x1 /* Does the connection support CONF REQ transmission */
 665 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
 666 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK     0x3F /* Default queue index the connection associated to */
 667 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT    2
 668         u8 timers_cleanup_invocation_cnt /* This variable is incremented each time the tStorm handler for timers cleanup is invoked within the same timers cleanup flow */;
 669         __le32 reserved1[2];
 670         __le32 dstMacAddressBytes0To3 /* destination MAC address: Bytes 0-3. */;
 671         __le16 dstMacAddressBytes4To5 /* destination MAC address: Bytes 4-5. */;
 672         __le16 ramrodEcho /* Saved ramrod echo - needed for 2nd round of terminate_conn (flush Q0) */;
 673         u8 flags1;
 674 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK          0x3 /* Indicate the mode of the connection: Target or Initiator, use enum fcoe_mode_type */
 675 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT         0
 676 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK      0x3F
 677 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT     2
 678         u8 q_relative_offset /* CQ, RQ and CMDQ relative offset for connection */;
 679         u8 bdq_resource_id /* The BDQ resource ID to which this function is mapped */;
 680         u8 reserved0[5] /* Alignment to 128b */;
 681 };
 682
 683 struct e4_mstorm_fcoe_conn_ag_ctx
 684 {
 685         u8 byte0 /* cdu_validation */;
 686         u8 byte1 /* state */;
 687         u8 flags0;
 688 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 689 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT    0
 690 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 691 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT    1
 692 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 693 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT     2
 694 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 695 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT     4
 696 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 697 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT     6
 698         u8 flags1;
 699 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 700 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT   0
 701 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 702 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT   1
 703 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 704 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT   2
 705 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 706 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
 707 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 708 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
 709 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 710 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
 711 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 712 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
 713 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 714 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
 715         __le16 word0 /* word0 */;
 716         __le16 word1 /* word1 */;
 717         __le32 reg0 /* reg0 */;
 718         __le32 reg1 /* reg1 */;
 719 };
 720
 721 /*
 722  * Fast path part of the fcoe storm context of Mstorm
 723  */
 724 struct fcoe_mstorm_fcoe_conn_st_ctx_fp
 725 {
 726         __le16 xfer_prod /* XferQ producer */;
 727         __le16 reserved1;
 728         u8 protection_info;
 729 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK  0x1 /* Does this connection support protection (if couple of GOS share this connection it is enough that one of them support protection) */
 730 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
 731 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK               0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss â€  this is critical since if line mss restrict us we canâ€™t rely on this size â€  it depends on vlan num) */
 732 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT              1
 733 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK           0x3F
 734 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT          2
 735         u8 q_relative_offset /* CQ, RQ and CMDQ relative offset for connection */;
 736         u8 reserved2[2];
 737 };
 738
 739 /*
 740  * Non fast path part of the fcoe storm context of Mstorm
 741  */
 742 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp
 743 {
 744         __le16 conn_id /* Driver connection ID. To be used by slowpaths to fill EQ placement params */;
 745         __le16 stat_ram_addr /* Statistics ram adderss */;
 746         __le16 num_pages_in_pbl /* Number of XferQ/RespQ pbl pages (both have same wqe size) */;
 747         u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */;
 748         u8 log_page_size;
 749         __le16 unsolicited_cq_count /* Counts number of CQs done due to unsolicited packets on this connection */;
 750         __le16 cmdq_count /* Counts number of CMDQs done on this connection */;
 751         u8 bdq_resource_id /* BDQ Resource ID */;
 752         u8 reserved0[3] /* Padding bytes for 2nd RegPair */;
 753         struct regpair xferq_pbl_addr /* XferQ Pbl base address */;
 754         struct regpair reserved1;
 755         struct regpair reserved2[3];
 756 };
 757
 758 /*
 759  * The fcoe storm context of Mstorm
 760  */
 761 struct mstorm_fcoe_conn_st_ctx
 762 {
 763         struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp /* Fast path part of the fcoe storm context of Mstorm */;
 764         struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp /* Non fast path part of the fcoe storm context of Mstorm */;
 765 };
 766
 767 /*
 768  * fcoe connection context
 769  */
 770 struct fcoe_conn_context
 771 {
 772         struct ystorm_fcoe_conn_st_ctx ystorm_st_context /* ystorm storm context */;
 773         struct pstorm_fcoe_conn_st_ctx pstorm_st_context /* pstorm storm context */;
 774         struct regpair pstorm_st_padding[2] /* padding */;
 775         struct xstorm_fcoe_conn_st_ctx xstorm_st_context /* xstorm storm context */;
 776         struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */;
 777         struct regpair xstorm_ag_padding[6] /* padding */;
 778         struct ustorm_fcoe_conn_st_ctx ustorm_st_context /* ustorm storm context */;
 779         struct regpair ustorm_st_padding[2] /* padding */;
 780         struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
 781         struct regpair tstorm_ag_padding[2] /* padding */;
 782         struct timers_context timer_context /* timer context */;
 783         struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
 784         struct tstorm_fcoe_conn_st_ctx tstorm_st_context /* tstorm storm context */;
 785         struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
 786         struct mstorm_fcoe_conn_st_ctx mstorm_st_context /* mstorm storm context */;
 787 };
 788
 789
 790 /*
 791  * FCoE connection offload params passed by driver to FW in FCoE offload ramrod
 792  */
 793 struct fcoe_conn_offload_ramrod_params
 794 {
 795         struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
 796 };
 797
 798
 799 /*
 800  * FCoE connection terminate params passed by driver to FW in FCoE terminate conn ramrod
 801  */
 802 struct fcoe_conn_terminate_ramrod_params
 803 {
 804         struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
 805 };
 806
 807
 808 /*
 809  * FCoE event type
 810  */
 811 enum fcoe_event_type
 812 {
 813         FCOE_EVENT_INIT_FUNC /* Slowpath completion on INIT_FUNC ramrod */,
 814         FCOE_EVENT_DESTROY_FUNC /* Slowpath completion on DESTROY_FUNC ramrod */,
 815         FCOE_EVENT_STAT_FUNC /* Slowpath completion on STAT_FUNC ramrod */,
 816         FCOE_EVENT_OFFLOAD_CONN /* Slowpath completion on OFFLOAD_CONN ramrod */,
 817         FCOE_EVENT_TERMINATE_CONN /* Slowpath completion on TERMINATE_CONN ramrod */,
 818         FCOE_EVENT_ERROR /* Error event */,
 819         MAX_FCOE_EVENT_TYPE
 820 };
 821
 822
 823 /*
 824  * FCoE init params passed by driver to FW in FCoE init ramrod
 825  */
 826 struct fcoe_init_ramrod_params
 827 {
 828         struct fcoe_init_func_ramrod_data init_ramrod_data;
 829 };
 830
 831
 832
 833
 834 /*
 835  * FCoE ramrod Command IDs
 836  */
 837 enum fcoe_ramrod_cmd_id
 838 {
 839         FCOE_RAMROD_CMD_ID_INIT_FUNC /* FCoE function init ramrod */,
 840         FCOE_RAMROD_CMD_ID_DESTROY_FUNC /* FCoE function destroy ramrod */,
 841         FCOE_RAMROD_CMD_ID_STAT_FUNC /* FCoE statistics ramrod */,
 842         FCOE_RAMROD_CMD_ID_OFFLOAD_CONN /* FCoE connection offload ramrod */,
 843         FCOE_RAMROD_CMD_ID_TERMINATE_CONN /* FCoE connection offload ramrod. Command ID known only to FW and VBD */,
 844         MAX_FCOE_RAMROD_CMD_ID
 845 };
 846
 847
 848 /*
 849  * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod
 850  */
 851 struct fcoe_stat_ramrod_params
 852 {
 853         struct fcoe_stat_ramrod_data stat_ramrod_data;
 854 };
 855
 856
 857
 858
 859
 860
 861
 862
 863
 864
 865
 866
 867
 868
 869
 870
 871 struct e4_ystorm_fcoe_conn_ag_ctx
 872 {
 873         u8 byte0 /* cdu_validation */;
 874         u8 byte1 /* state */;
 875         u8 flags0;
 876 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 877 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT    0
 878 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 879 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT    1
 880 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 881 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT     2
 882 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 883 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT     4
 884 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 885 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT     6
 886         u8 flags1;
 887 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 888 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT   0
 889 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 890 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT   1
 891 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 892 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT   2
 893 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 894 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
 895 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 896 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
 897 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 898 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
 899 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 900 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
 901 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 902 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
 903         u8 byte2 /* byte2 */;
 904         u8 byte3 /* byte3 */;
 905         __le16 word0 /* word0 */;
 906         __le32 reg0 /* reg0 */;
 907         __le32 reg1 /* reg1 */;
 908         __le16 word1 /* word1 */;
 909         __le16 word2 /* word2 */;
 910         __le16 word3 /* word3 */;
 911         __le16 word4 /* word4 */;
 912         __le32 reg2 /* reg2 */;
 913         __le32 reg3 /* reg3 */;
 914 };
 915
 916
 917 struct e5_mstorm_fcoe_conn_ag_ctx
 918 {
 919         u8 byte0 /* cdu_validation */;
 920         u8 byte1 /* state_and_core_id */;
 921         u8 flags0;
 922 #define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 923 #define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT    0
 924 #define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 925 #define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT    1
 926 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 927 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT     2
 928 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 929 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT     4
 930 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 931 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT     6
 932         u8 flags1;
 933 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 934 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT   0
 935 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 936 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT   1
 937 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 938 #define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT   2
 939 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 940 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
 941 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 942 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
 943 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 944 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
 945 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 946 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
 947 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 948 #define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
 949         __le16 word0 /* word0 */;
 950         __le16 word1 /* word1 */;
 951         __le32 reg0 /* reg0 */;
 952         __le32 reg1 /* reg1 */;
 953 };
 954
 955
 956 struct e5_tstorm_fcoe_conn_ag_ctx
 957 {
 958         u8 reserved0 /* cdu_validation */;
 959         u8 state_and_core_id /* state_and_core_id */;
 960         u8 flags0;
 961 #define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1 /* exist_in_qm0 */
 962 #define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
 963 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK                  0x1 /* exist_in_qm1 */
 964 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT                 1
 965 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK                  0x1 /* bit2 */
 966 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT                 2
 967 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK                  0x1 /* bit3 */
 968 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT                 3
 969 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK                  0x1 /* bit4 */
 970 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT                 4
 971 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK                  0x1 /* bit5 */
 972 #define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT                 5
 973 #define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK        0x3 /* timer0cf */
 974 #define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT       6
 975         u8 flags1;
 976 #define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3 /* timer1cf */
 977 #define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          0
 978 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK                   0x3 /* timer2cf */
 979 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT                  2
 980 #define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3 /* timer_stop_all */
 981 #define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
 982 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK                   0x3 /* cf4 */
 983 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT                  6
 984         u8 flags2;
 985 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK                   0x3 /* cf5 */
 986 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT                  0
 987 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK                   0x3 /* cf6 */
 988 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT                  2
 989 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK                   0x3 /* cf7 */
 990 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT                  4
 991 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK                   0x3 /* cf8 */
 992 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT                  6
 993         u8 flags3;
 994 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK                   0x3 /* cf9 */
 995 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT                  0
 996 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK                  0x3 /* cf10 */
 997 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT                 2
 998 #define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK     0x1 /* cf0en */
 999 #define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT    4
1000 #define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1 /* cf1en */
1001 #define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       5
1002 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK                 0x1 /* cf2en */
1003 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT                6
1004 #define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1 /* cf3en */
1005 #define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
1006         u8 flags4;
1007 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK                 0x1 /* cf4en */
1008 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT                0
1009 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK                 0x1 /* cf5en */
1010 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT                1
1011 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK                 0x1 /* cf6en */
1012 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT                2
1013 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK                 0x1 /* cf7en */
1014 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT                3
1015 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK                 0x1 /* cf8en */
1016 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT                4
1017 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK                 0x1 /* cf9en */
1018 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT                5
1019 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK                0x1 /* cf10en */
1020 #define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT               6
1021 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK               0x1 /* rule0en */
1022 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT              7
1023         u8 flags5;
1024 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK               0x1 /* rule1en */
1025 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT              0
1026 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK               0x1 /* rule2en */
1027 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT              1
1028 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK               0x1 /* rule3en */
1029 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT              2
1030 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK               0x1 /* rule4en */
1031 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT              3
1032 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK               0x1 /* rule5en */
1033 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT              4
1034 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK               0x1 /* rule6en */
1035 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT              5
1036 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK               0x1 /* rule7en */
1037 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT              6
1038 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK               0x1 /* rule8en */
1039 #define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT              7
1040         u8 flags6;
1041 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK          0x1 /* bit6 */
1042 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT         0
1043 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK          0x1 /* bit7 */
1044 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT         1
1045 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK          0x1 /* bit8 */
1046 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT         2
1047 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK          0x3 /* cf11 */
1048 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT         3
1049 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK          0x1 /* cf11en */
1050 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT         5
1051 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK          0x1 /* rule9en */
1052 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT         6
1053 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK          0x1 /* rule10en */
1054 #define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT         7
1055         u8 byte2 /* byte2 */;
1056         __le16 word0 /* word0 */;
1057         __le32 reg0 /* reg0 */;
1058 };
1059
1060
1061 struct e5_ustorm_fcoe_conn_ag_ctx
1062 {
1063         u8 byte0 /* cdu_validation */;
1064         u8 byte1 /* state_and_core_id */;
1065         u8 flags0;
1066 #define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK          0x1 /* exist_in_qm0 */
1067 #define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT         0
1068 #define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK          0x1 /* exist_in_qm1 */
1069 #define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT         1
1070 #define E5_USTORM_FCOE_CONN_AG_CTX_CF0_MASK           0x3 /* timer0cf */
1071 #define E5_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT          2
1072 #define E5_USTORM_FCOE_CONN_AG_CTX_CF1_MASK           0x3 /* timer1cf */
1073 #define E5_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT          4
1074 #define E5_USTORM_FCOE_CONN_AG_CTX_CF2_MASK           0x3 /* timer2cf */
1075 #define E5_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT          6
1076         u8 flags1;
1077 #define E5_USTORM_FCOE_CONN_AG_CTX_CF3_MASK           0x3 /* timer_stop_all */
1078 #define E5_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT          0
1079 #define E5_USTORM_FCOE_CONN_AG_CTX_CF4_MASK           0x3 /* cf4 */
1080 #define E5_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT          2
1081 #define E5_USTORM_FCOE_CONN_AG_CTX_CF5_MASK           0x3 /* cf5 */
1082 #define E5_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT          4
1083 #define E5_USTORM_FCOE_CONN_AG_CTX_CF6_MASK           0x3 /* cf6 */
1084 #define E5_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT          6
1085         u8 flags2;
1086 #define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK         0x1 /* cf0en */
1087 #define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT        0
1088 #define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK         0x1 /* cf1en */
1089 #define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT        1
1090 #define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK         0x1 /* cf2en */
1091 #define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT        2
1092 #define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK         0x1 /* cf3en */
1093 #define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT        3
1094 #define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK         0x1 /* cf4en */
1095 #define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT        4
1096 #define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK         0x1 /* cf5en */
1097 #define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT        5
1098 #define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK         0x1 /* cf6en */
1099 #define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT        6
1100 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK       0x1 /* rule0en */
1101 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT      7
1102         u8 flags3;
1103 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK       0x1 /* rule1en */
1104 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT      0
1105 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK       0x1 /* rule2en */
1106 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT      1
1107 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK       0x1 /* rule3en */
1108 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT      2
1109 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK       0x1 /* rule4en */
1110 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT      3
1111 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK       0x1 /* rule5en */
1112 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT      4
1113 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK       0x1 /* rule6en */
1114 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT      5
1115 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK       0x1 /* rule7en */
1116 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT      6
1117 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK       0x1 /* rule8en */
1118 #define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT      7
1119         u8 flags4;
1120 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK  0x1 /* bit2 */
1121 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
1122 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK  0x1 /* bit3 */
1123 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
1124 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK  0x3 /* cf7 */
1125 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
1126 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK  0x3 /* cf8 */
1127 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
1128 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK  0x1 /* cf7en */
1129 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
1130 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK  0x1 /* cf8en */
1131 #define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
1132         u8 byte2 /* byte2 */;
1133         __le16 word0 /* conn_dpi */;
1134         __le16 word1 /* word1 */;
1135         __le32 reg0 /* reg0 */;
1136         __le32 reg1 /* reg1 */;
1137         __le32 reg2 /* reg2 */;
1138         __le32 reg3 /* reg3 */;
1139         __le16 word2 /* word2 */;
1140         __le16 word3 /* word3 */;
1141 };
1142
1143
1144 struct e5_xstorm_fcoe_conn_ag_ctx
1145 {
1146         u8 reserved0 /* cdu_validation */;
1147         u8 state_and_core_id /* state_and_core_id */;
1148         u8 flags0;
1149 #define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
1150 #define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT      0
1151 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK          0x1 /* exist_in_qm1 */
1152 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT         1
1153 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK          0x1 /* exist_in_qm2 */
1154 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT         2
1155 #define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK       0x1 /* exist_in_qm3 */
1156 #define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT      3
1157 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK          0x1 /* bit4 */
1158 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT         4
1159 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK          0x1 /* cf_array_active */
1160 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT         5
1161 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK          0x1 /* bit6 */
1162 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT         6
1163 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK          0x1 /* bit7 */
1164 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT         7
1165         u8 flags1;
1166 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK          0x1 /* bit8 */
1167 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT         0
1168 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK          0x1 /* bit9 */
1169 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT         1
1170 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK          0x1 /* bit10 */
1171 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT         2
1172 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK              0x1 /* bit11 */
1173 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT             3
1174 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK              0x1 /* bit12 */
1175 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT             4
1176 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK              0x1 /* bit13 */
1177 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT             5
1178 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK              0x1 /* bit14 */
1179 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT             6
1180 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK              0x1 /* bit15 */
1181 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT             7
1182         u8 flags2;
1183 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK                0x3 /* timer0cf */
1184 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT               0
1185 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK                0x3 /* timer1cf */
1186 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT               2
1187 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK                0x3 /* timer2cf */
1188 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT               4
1189 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK                0x3 /* timer_stop_all */
1190 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT               6
1191         u8 flags3;
1192 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK                0x3 /* cf4 */
1193 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT               0
1194 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK                0x3 /* cf5 */
1195 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT               2
1196 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK                0x3 /* cf6 */
1197 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT               4
1198 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK                0x3 /* cf7 */
1199 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT               6
1200         u8 flags4;
1201 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK                0x3 /* cf8 */
1202 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT               0
1203 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK                0x3 /* cf9 */
1204 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT               2
1205 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK               0x3 /* cf10 */
1206 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT              4
1207 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK               0x3 /* cf11 */
1208 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT              6
1209         u8 flags5;
1210 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK               0x3 /* cf12 */
1211 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT              0
1212 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK               0x3 /* cf13 */
1213 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT              2
1214 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK               0x3 /* cf14 */
1215 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT              4
1216 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK               0x3 /* cf15 */
1217 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT              6
1218         u8 flags6;
1219 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK               0x3 /* cf16 */
1220 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT              0
1221 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK               0x3 /* cf_array_cf */
1222 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT              2
1223 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK               0x3 /* cf18 */
1224 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT              4
1225 #define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK              0x3 /* cf19 */
1226 #define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT             6
1227         u8 flags7;
1228 #define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK           0x3 /* cf20 */
1229 #define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT          0
1230 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK         0x3 /* cf21 */
1231 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT        2
1232 #define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK          0x3 /* cf22 */
1233 #define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT         4
1234 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK              0x1 /* cf0en */
1235 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT             6
1236 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
1237 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT             7
1238         u8 flags8;
1239 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
1240 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT             0
1241 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK              0x1 /* cf3en */
1242 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT             1
1243 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK              0x1 /* cf4en */
1244 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT             2
1245 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK              0x1 /* cf5en */
1246 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT             3
1247 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK              0x1 /* cf6en */
1248 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT             4
1249 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK              0x1 /* cf7en */
1250 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT             5
1251 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK              0x1 /* cf8en */
1252 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT             6
1253 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK              0x1 /* cf9en */
1254 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT             7
1255         u8 flags9;
1256 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK             0x1 /* cf10en */
1257 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT            0
1258 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK             0x1 /* cf11en */
1259 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT            1
1260 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK             0x1 /* cf12en */
1261 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT            2
1262 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK             0x1 /* cf13en */
1263 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT            3
1264 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK             0x1 /* cf14en */
1265 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT            4
1266 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK             0x1 /* cf15en */
1267 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT            5
1268 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK             0x1 /* cf16en */
1269 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT            6
1270 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK             0x1 /* cf_array_cf_en */
1271 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT            7
1272         u8 flags10;
1273 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK             0x1 /* cf18en */
1274 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT            0
1275 #define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK           0x1 /* cf19en */
1276 #define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT          1
1277 #define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK        0x1 /* cf20en */
1278 #define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT       2
1279 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK         0x1 /* cf21en */
1280 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT        3
1281 #define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK       0x1 /* cf22en */
1282 #define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT      4
1283 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK             0x1 /* cf23en */
1284 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT            5
1285 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK         0x1 /* rule0en */
1286 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT        6
1287 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK         0x1 /* rule1en */
1288 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT        7
1289         u8 flags11;
1290 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK         0x1 /* rule2en */
1291 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT        0
1292 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK         0x1 /* rule3en */
1293 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT        1
1294 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK         0x1 /* rule4en */
1295 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT        2
1296 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK            0x1 /* rule5en */
1297 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT           3
1298 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
1299 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT           4
1300 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK            0x1 /* rule7en */
1301 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT           5
1302 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK       0x1 /* rule8en */
1303 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT      6
1304 #define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK  0x1 /* rule9en */
1305 #define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
1306         u8 flags12;
1307 #define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK     0x1 /* rule10en */
1308 #define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT    0
1309 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK           0x1 /* rule11en */
1310 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT          1
1311 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK       0x1 /* rule12en */
1312 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT      2
1313 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK       0x1 /* rule13en */
1314 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT      3
1315 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK           0x1 /* rule14en */
1316 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT          4
1317 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK           0x1 /* rule15en */
1318 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT          5
1319 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK           0x1 /* rule16en */
1320 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT          6
1321 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK           0x1 /* rule17en */
1322 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT          7
1323         u8 flags13;
1324 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK  0x1 /* rule18en */
1325 #define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
1326 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK           0x1 /* rule19en */
1327 #define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT          1
1328 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK       0x1 /* rule20en */
1329 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT      2
1330 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK       0x1 /* rule21en */
1331 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT      3
1332 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK       0x1 /* rule22en */
1333 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT      4
1334 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK       0x1 /* rule23en */
1335 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT      5
1336 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK       0x1 /* rule24en */
1337 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT      6
1338 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK       0x1 /* rule25en */
1339 #define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT      7
1340         u8 flags14;
1341 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK              0x1 /* bit16 */
1342 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT             0
1343 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK              0x1 /* bit17 */
1344 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT             1
1345 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK              0x1 /* bit18 */
1346 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT             2
1347 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK              0x1 /* bit19 */
1348 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT             3
1349 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK              0x1 /* bit20 */
1350 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT             4
1351 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK              0x1 /* bit21 */
1352 #define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT             5
1353 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK               0x3 /* cf23 */
1354 #define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT              6
1355         u8 byte2 /* byte2 */;
1356         __le16 physical_q0 /* physical_q0 */;
1357         __le16 word1 /* physical_q1 */;
1358         __le16 word2 /* physical_q2 */;
1359         __le16 sq_cons /* word3 */;
1360         __le16 sq_prod /* word4 */;
1361         __le16 xferq_prod /* word5 */;
1362         __le16 xferq_cons /* conn_dpi */;
1363         u8 byte3 /* byte3 */;
1364         u8 byte4 /* byte4 */;
1365         u8 byte5 /* byte5 */;
1366         u8 byte6 /* byte6 */;
1367         __le32 remain_io /* reg0 */;
1368         __le32 reg1 /* reg1 */;
1369         __le32 reg2 /* reg2 */;
1370         __le32 reg3 /* reg3 */;
1371         __le32 reg4 /* reg4 */;
1372         __le32 reg5 /* cf_array0 */;
1373         __le32 reg6 /* cf_array1 */;
1374         u8 flags15;
1375 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK       0x1 /* bit22 */
1376 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT      0
1377 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK       0x1 /* bit23 */
1378 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT      1
1379 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK       0x1 /* bit24 */
1380 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT      2
1381 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK       0x3 /* cf24 */
1382 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT      3
1383 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK       0x1 /* cf24en */
1384 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT      5
1385 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK       0x1 /* rule26en */
1386 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT      6
1387 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK       0x1 /* rule27en */
1388 #define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT      7
1389         u8 byte7 /* byte7 */;
1390         __le16 respq_prod /* word7 */;
1391         __le16 respq_cons /* word8 */;
1392         __le16 word9 /* word9 */;
1393         __le16 word10 /* word10 */;
1394         __le16 word11 /* word11 */;
1395         __le32 reg7 /* reg7 */;
1396 };
1397
1398
1399 struct e5_ystorm_fcoe_conn_ag_ctx
1400 {
1401         u8 byte0 /* cdu_validation */;
1402         u8 byte1 /* state_and_core_id */;
1403         u8 flags0;
1404 #define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1405 #define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT    0
1406 #define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1407 #define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT    1
1408 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1409 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT     2
1410 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1411 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT     4
1412 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1413 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT     6
1414         u8 flags1;
1415 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1416 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT   0
1417 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1418 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT   1
1419 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1420 #define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT   2
1421 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1422 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
1423 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1424 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
1425 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1426 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
1427 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1428 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
1429 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1430 #define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
1431         u8 byte2 /* byte2 */;
1432         u8 byte3 /* byte3 */;
1433         __le16 word0 /* word0 */;
1434         __le32 reg0 /* reg0 */;
1435         __le32 reg1 /* reg1 */;
1436         __le16 word1 /* word1 */;
1437         __le16 word2 /* word2 */;
1438         __le16 word3 /* word3 */;
1439         __le16 word4 /* word4 */;
1440         __le32 reg2 /* reg2 */;
1441         __le32 reg3 /* reg3 */;
1442 };
1443
1444 #endif /* __ECORE_HSI_FCOE__ */