usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_sp_commands.h

   1 /*
   2 * CDDL HEADER START
   3 *
   4 * The contents of this file are subject to the terms of the
   5 * Common Development and Distribution License, v.1,  (the "License").
   6 * You may not use this file except in compliance with the License.
   7 *
   8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9 * or http://opensource.org/licenses/CDDL-1.0.
  10 * See the License for the specific language governing permissions
  11 * and limitations under the License.
  12 *
  13 * When distributing Covered Code, include this CDDL HEADER in each
  14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15 * If applicable, add the following below this CDDL HEADER, with the
  16 * fields enclosed by brackets "[]" replaced with your own identifying
  17 * information: Portions Copyright [yyyy] [name of copyright owner]
  18 *
  19 * CDDL HEADER END
  20 */
  21
  22 /*
  23 * Copyright 2014-2017 Cavium, Inc.
  24 * The contents of this file are subject to the terms of the Common Development
  25 * and Distribution License, v.1,  (the "License").
  26
  27 * You may not use this file except in compliance with the License.
  28
  29 * You can obtain a copy of the License at available
  30 * at http://opensource.org/licenses/CDDL-1.0
  31
  32 * See the License for the specific language governing permissions and
  33 * limitations under the License.
  34 */
  35
  36 #ifndef __ECORE_SP_COMMANDS_H__
  37 #define __ECORE_SP_COMMANDS_H__
  38
  39 #include "ecore.h"
  40 #include "ecore_spq.h"
  41 #include "ecore_sp_api.h"
  42
  43 #define ECORE_SP_EQ_COMPLETION  0x01
  44 #define ECORE_SP_CQE_COMPLETION 0x02
  45
  46 struct ecore_sp_init_data {
  47         /* The CID and FID aren't necessarily derived from hwfn,
  48          * e.g., in IOV scenarios. CID might defer between SPQ and
  49          * other elements.
  50          */
  51         u32                             cid;
  52         u16                             opaque_fid;
  53
  54         /* Information regarding operation upon sending & completion */
  55         enum spq_mode                   comp_mode;
  56         struct ecore_spq_comp_cb        *p_comp_data;
  57
  58 };
  59
  60 /**
  61  * @brief Acquire and initialize and SPQ entry for a given ramrod.
  62  *
  63  * @param p_hwfn
  64  * @param pp_ent - will be filled with a pointer to an entry upon success
  65  * @param cmd - dependent upon protocol
  66  * @param protocol
  67  * @param p_data - various configuration required for ramrod
  68  *
  69  * @return ECORE_SUCCESS upon success, otherwise failure.
  70  */
  71 enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
  72                                            struct ecore_spq_entry **pp_ent,
  73                                            u8 cmd,
  74                                            u8 protocol,
  75                                            struct ecore_sp_init_data *p_data);
  76
  77 /**
  78  * @brief ecore_sp_pf_start - PF Function Start Ramrod
  79  *
  80  * This ramrod is sent to initialize a physical function (PF). It will
  81  * configure the function related parameters and write its completion to the
  82  * event ring specified in the parameters.
  83  *
  84  * Ramrods complete on the common event ring for the PF. This ring is
  85  * allocated by the driver on host memory and its parameters are written
  86  * to the internal RAM of the UStorm by the Function Start Ramrod.
  87  *
  88  * @param p_hwfn
  89  * @param p_tunn - pf start tunneling configuration
  90  * @param mode
  91  * @param allow_npar_tx_switch - npar tx switching to be used
  92  *        for vports configured for tx-switching.
  93  *
  94  * @return enum _ecore_status_t
  95  */
  96
  97 enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
  98                                        struct ecore_tunnel_info *p_tunn,
  99                                        enum ecore_mf_mode mode,
 100                                        bool allow_npar_tx_switch);
 101
 102 /**
 103  * @brief ecore_sp_pf_update - PF Function Update Ramrod
 104  *
 105  * This ramrod updates function-related parameters. Every parameter can be
 106  * updated independently, according to configuration flags.
 107  *
 108  * @note Final phase API.
 109  *
 110  * @param p_hwfn
 111  *
 112  * @return enum _ecore_status_t
 113  */
 114
 115 enum _ecore_status_t ecore_sp_pf_update_dcbx(struct ecore_hwfn *p_hwfn);
 116
 117 /**
 118  * @brief ecore_sp_pf_stop - PF Function Stop Ramrod
 119  *
 120  * This ramrod is sent to close a Physical Function (PF). It is the last ramrod
 121  * sent and the last completion written to the PFs Event Ring. This ramrod also
 122  * deletes the context for the Slowhwfn connection on this PF.
 123  *
 124  * @note Not required for first packet.
 125  *
 126  * @param p_hwfn
 127  *
 128  * @return enum _ecore_status_t
 129  */
 130
 131 enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn);
 132
 133 /**
 134  * @brief ecore_sp_heartbeat_ramrod - Send empty Ramrod
 135  *
 136  * @param p_hwfn
 137  *
 138  * @return enum _ecore_status_t
 139  */
 140
 141 enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn);
 142
 143 struct ecore_rl_update_params {
 144         u8 qcn_update_param_flg;
 145         u8 dcqcn_update_param_flg;
 146         u8 rl_init_flg;
 147         u8 rl_start_flg;
 148         u8 rl_stop_flg;
 149         u8 rl_id_first;
 150         u8 rl_id_last;
 151         u8 rl_dc_qcn_flg; /* If set, RL will used for DCQCN */
 152         u32 rl_bc_rate; /* Byte Counter Limit */
 153         u16 rl_max_rate; /* Maximum rate in 1.6 Mbps resolution */
 154         u16 rl_r_ai; /* Active increase rate */
 155         u16 rl_r_hai; /* Hyper active increase rate */
 156         u16 dcqcn_g; /* DCQCN Alpha update gain in 1/64K resolution */
 157         u32 dcqcn_k_us; /* DCQCN Alpha update interval */
 158         u32 dcqcn_timeuot_us;
 159         u32 qcn_timeuot_us;
 160 };
 161
 162 /**
 163  * @brief ecore_sp_rl_update - Update rate limiters
 164  *
 165  * @param p_hwfn
 166  * @param params
 167  *
 168  * @return enum _ecore_status_t
 169  */
 170 enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
 171                                         struct ecore_rl_update_params *params);
 172
 173 /**
 174  * @brief ecore_sp_pf_update_stag - PF STAG value update Ramrod
 175  *
 176  * @param p_hwfn
 177  *
 178  * @return enum _ecore_status_t
 179  */
 180
 181 enum _ecore_status_t ecore_sp_pf_update_stag(struct ecore_hwfn *p_hwfn);
 182
 183 #endif /*__ECORE_SP_COMMANDS_H__*/