usr/src/uts/common/io/qede/579xx/drivers/ecore/ecore_hsi_roce.h

   1 /*
   2 * CDDL HEADER START
   3 *
   4 * The contents of this file are subject to the terms of the
   5 * Common Development and Distribution License, v.1,  (the "License").
   6 * You may not use this file except in compliance with the License.
   7 *
   8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9 * or http://opensource.org/licenses/CDDL-1.0.
  10 * See the License for the specific language governing permissions
  11 * and limitations under the License.
  12 *
  13 * When distributing Covered Code, include this CDDL HEADER in each
  14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15 * If applicable, add the following below this CDDL HEADER, with the
  16 * fields enclosed by brackets "[]" replaced with your own identifying
  17 * information: Portions Copyright [yyyy] [name of copyright owner]
  18 *
  19 * CDDL HEADER END
  20 */
  21
  22 /*
  23 * Copyright 2014-2017 Cavium, Inc.
  24 * The contents of this file are subject to the terms of the Common Development
  25 * and Distribution License, v.1,  (the "License").
  26
  27 * You may not use this file except in compliance with the License.
  28
  29 * You can obtain a copy of the License at available
  30 * at http://opensource.org/licenses/CDDL-1.0
  31
  32 * See the License for the specific language governing permissions and
  33 * limitations under the License.
  34 */
  35
  36 #ifndef __ECORE_HSI_ROCE__
  37 #define __ECORE_HSI_ROCE__
  38 /************************************************************************/
  39 /* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */
  40 /************************************************************************/
  41 #include "ecore_hsi_rdma.h"
  42 /************************************************************************/
  43 /* Add include to common roce target for both eCore and protocol roce driver */
  44 /************************************************************************/
  45 #include "roce_common.h"
  46
  47 /*
  48  * The roce storm context of Mstorm
  49  */
  50 struct mstorm_roce_conn_st_ctx
  51 {
  52         struct regpair temp[6];
  53 };
  54
  55
  56 /*
  57  * The roce storm context of Mstorm
  58  */
  59 struct pstorm_roce_conn_st_ctx
  60 {
  61         struct regpair temp[16];
  62 };
  63
  64
  65 /*
  66  * The roce storm context of Ystorm
  67  */
  68 struct ystorm_roce_conn_st_ctx
  69 {
  70         struct regpair temp[2];
  71 };
  72
  73 /*
  74  * The roce storm context of Xstorm
  75  */
  76 struct xstorm_roce_conn_st_ctx
  77 {
  78         struct regpair temp[24];
  79 };
  80
  81 /*
  82  * The roce storm context of Tstorm
  83  */
  84 struct tstorm_roce_conn_st_ctx
  85 {
  86         struct regpair temp[30];
  87 };
  88
  89 /*
  90  * The roce storm context of Ystorm
  91  */
  92 struct ustorm_roce_conn_st_ctx
  93 {
  94         struct regpair temp[12];
  95 };
  96
  97 /*
  98  * roce connection context
  99  */
 100 struct roce_conn_context
 101 {
 102         struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */;
 103         struct regpair ystorm_st_padding[2] /* padding */;
 104         struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */;
 105         struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */;
 106         struct regpair xstorm_st_padding[2] /* padding */;
 107         struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */;
 108         struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
 109         struct timers_context timer_context /* timer context */;
 110         struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
 111         struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */;
 112         struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */;
 113         struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */;
 114         struct regpair ustorm_st_padding[2] /* padding */;
 115 };
 116
 117
 118 /*
 119  * roce create qp requester ramrod data
 120  */
 121 struct roce_create_qp_req_ramrod_data
 122 {
 123         __le16 flags;
 124 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK          0x3 /* Use roce_flavor enum */
 125 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT         0
 126 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK  0x1
 127 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
 128 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK        0x1
 129 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT       3
 130 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK                  0x7
 131 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT                 4
 132 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK             0x1
 133 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT            7
 134 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK        0xF
 135 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT       8
 136 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK          0xF
 137 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT         12
 138         u8 max_ord;
 139         u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */;
 140         u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */;
 141         u8 orq_num_pages;
 142         __le16 p_key;
 143         __le32 flow_label;
 144         __le32 dst_qp_id;
 145         __le32 ack_timeout_val;
 146         __le32 initial_psn;
 147         __le16 mtu;
 148         __le16 pd;
 149         __le16 sq_num_pages;
 150         __le16 low_latency_phy_queue;
 151         struct regpair sq_pbl_addr;
 152         struct regpair orq_pbl_addr;
 153         __le16 local_mac_addr[3] /* BE order */;
 154         __le16 remote_mac_addr[3] /* BE order */;
 155         __le16 vlan_id;
 156         __le16 udp_src_port /* Only relevant in RRoCE */;
 157         __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */;
 158         __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */;
 159         struct regpair qp_handle_for_cqe;
 160         struct regpair qp_handle_for_async;
 161         u8 stats_counter_id /* Statistics counter ID to use */;
 162         u8 reserved3[7];
 163         __le32 cq_cid;
 164         __le16 regular_latency_phy_queue;
 165         __le16 dpi;
 166 };
 167
 168
 169 /*
 170  * roce create qp responder ramrod data
 171  */
 172 struct roce_create_qp_resp_ramrod_data
 173 {
 174         __le16 flags;
 175 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK          0x3 /* Use roce_flavor enum */
 176 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT         0
 177 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK           0x1
 178 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT          2
 179 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK           0x1
 180 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT          3
 181 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK            0x1
 182 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT           4
 183 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK              0x1
 184 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT             5
 185 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK  0x1
 186 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
 187 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK      0x1
 188 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT     7
 189 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK                  0x7
 190 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT                 8
 191 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK    0x1F
 192 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT   11
 193         u8 max_ird;
 194         u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */;
 195         u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */;
 196         u8 irq_num_pages;
 197         __le16 p_key;
 198         __le32 flow_label;
 199         __le32 dst_qp_id;
 200         u8 stats_counter_id /* Statistics counter ID to use */;
 201         u8 reserved1;
 202         __le16 mtu;
 203         __le32 initial_psn;
 204         __le16 pd;
 205         __le16 rq_num_pages;
 206         struct rdma_srq_id srq_id;
 207         struct regpair rq_pbl_addr;
 208         struct regpair irq_pbl_addr;
 209         __le16 local_mac_addr[3] /* BE order */;
 210         __le16 remote_mac_addr[3] /* BE order */;
 211         __le16 vlan_id;
 212         __le16 udp_src_port /* Only relevant in RRoCE */;
 213         __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */;
 214         __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */;
 215         struct regpair qp_handle_for_cqe;
 216         struct regpair qp_handle_for_async;
 217         __le16 low_latency_phy_queue;
 218         u8 reserved2[6];
 219         __le32 cq_cid;
 220         __le16 regular_latency_phy_queue;
 221         __le16 dpi;
 222 };
 223
 224
 225 /*
 226  * RoCE destroy qp requester output params
 227  */
 228 struct roce_destroy_qp_req_output_params
 229 {
 230         __le32 num_bound_mw;
 231         __le32 cq_prod /* Completion producer value at destroy QP */;
 232 };
 233
 234
 235 /*
 236  * RoCE destroy qp requester ramrod data
 237  */
 238 struct roce_destroy_qp_req_ramrod_data
 239 {
 240         struct regpair output_params_addr;
 241 };
 242
 243
 244 /*
 245  * RoCE destroy qp responder output params
 246  */
 247 struct roce_destroy_qp_resp_output_params
 248 {
 249         __le32 num_invalidated_mw;
 250         __le32 cq_prod /* Completion producer value at destroy QP */;
 251 };
 252
 253
 254 /*
 255  * RoCE destroy qp responder ramrod data
 256  */
 257 struct roce_destroy_qp_resp_ramrod_data
 258 {
 259         struct regpair output_params_addr;
 260 };
 261
 262
 263 /*
 264  * roce func init ramrod data
 265  */
 266 struct roce_events_stats
 267 {
 268         __le16 silent_drops;
 269         __le16 rnr_naks_sent;
 270         __le32 retransmit_count;
 271         __le32 icrc_error_count;
 272         __le32 reserved;
 273 };
 274
 275
 276 /*
 277  * ROCE slow path EQ cmd IDs
 278  */
 279 enum roce_event_opcode
 280 {
 281         ROCE_EVENT_CREATE_QP=11,
 282         ROCE_EVENT_MODIFY_QP,
 283         ROCE_EVENT_QUERY_QP,
 284         ROCE_EVENT_DESTROY_QP,
 285         ROCE_EVENT_CREATE_UD_QP,
 286         ROCE_EVENT_DESTROY_UD_QP,
 287         MAX_ROCE_EVENT_OPCODE
 288 };
 289
 290
 291 /*
 292  * roce func init ramrod data
 293  */
 294 struct roce_init_func_params
 295 {
 296         u8 ll2_queue_id /* This ll2 queue ID is used for Unreliable Datagram QP */;
 297         u8 cnp_vlan_priority /* VLAN priority of DCQCN CNP packet */;
 298         u8 cnp_dscp /* The value of DSCP field in IP header for CNP packets */;
 299         u8 reserved;
 300         __le32 cnp_send_timeout /* The minimal difference of send time between CNP packets for specific QP. Units are in microseconds */;
 301 };
 302
 303
 304 /*
 305  * roce func init ramrod data
 306  */
 307 struct roce_init_func_ramrod_data
 308 {
 309         struct rdma_init_func_ramrod_data rdma;
 310         struct roce_init_func_params roce;
 311 };
 312
 313
 314 /*
 315  * roce modify qp requester ramrod data
 316  */
 317 struct roce_modify_qp_req_ramrod_data
 318 {
 319         __le16 flags;
 320 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK      0x1
 321 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT     0
 322 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK      0x1
 323 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT     1
 324 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK  0x1
 325 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
 326 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK            0x1
 327 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT           3
 328 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK   0x1
 329 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT  4
 330 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK          0x1
 331 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT         5
 332 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK      0x1
 333 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT     6
 334 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK    0x1
 335 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT   7
 336 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK      0x1
 337 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT     8
 338 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK              0x1
 339 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT             9
 340 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK                  0x7
 341 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT                 10
 342 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK            0x7
 343 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT           13
 344         u8 fields;
 345 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK        0xF
 346 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT       0
 347 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK          0xF
 348 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT         4
 349         u8 max_ord;
 350         u8 traffic_class;
 351         u8 hop_limit;
 352         __le16 p_key;
 353         __le32 flow_label;
 354         __le32 ack_timeout_val;
 355         __le16 mtu;
 356         __le16 reserved2;
 357         __le32 reserved3[3];
 358         __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
 359         __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
 360 };
 361
 362
 363 /*
 364  * roce modify qp responder ramrod data
 365  */
 366 struct roce_modify_qp_resp_ramrod_data
 367 {
 368         __le16 flags;
 369 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK        0x1
 370 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT       0
 371 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK             0x1
 372 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT            1
 373 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK             0x1
 374 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT            2
 375 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK              0x1
 376 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT             3
 377 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK              0x1
 378 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT             4
 379 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK     0x1
 380 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT    5
 381 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK            0x1
 382 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT           6
 383 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK                0x1
 384 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT               7
 385 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK  0x1
 386 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
 387 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK        0x1
 388 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT       9
 389 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK              0x3F
 390 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT             10
 391         u8 fields;
 392 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK                    0x7
 393 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT                   0
 394 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK      0x1F
 395 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT     3
 396         u8 max_ird;
 397         u8 traffic_class;
 398         u8 hop_limit;
 399         __le16 p_key;
 400         __le32 flow_label;
 401         __le16 mtu;
 402         __le16 reserved2;
 403         __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
 404         __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */;
 405 };
 406
 407
 408 /*
 409  * RoCE query qp requester output params
 410  */
 411 struct roce_query_qp_req_output_params
 412 {
 413         __le32 psn /* send next psn */;
 414         __le32 flags;
 415 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK          0x1
 416 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT         0
 417 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK  0x1
 418 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
 419 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK        0x3FFFFFFF
 420 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT       2
 421 };
 422
 423
 424 /*
 425  * RoCE query qp requester ramrod data
 426  */
 427 struct roce_query_qp_req_ramrod_data
 428 {
 429         struct regpair output_params_addr;
 430 };
 431
 432
 433 /*
 434  * RoCE query qp responder output params
 435  */
 436 struct roce_query_qp_resp_output_params
 437 {
 438         __le32 psn /* send next psn */;
 439         __le32 err_flag;
 440 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
 441 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
 442 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
 443 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
 444 };
 445
 446
 447 /*
 448  * RoCE query qp responder ramrod data
 449  */
 450 struct roce_query_qp_resp_ramrod_data
 451 {
 452         struct regpair output_params_addr;
 453 };
 454
 455
 456 /*
 457  * ROCE ramrod command IDs
 458  */
 459 enum roce_ramrod_cmd_id
 460 {
 461         ROCE_RAMROD_CREATE_QP=11,
 462         ROCE_RAMROD_MODIFY_QP,
 463         ROCE_RAMROD_QUERY_QP,
 464         ROCE_RAMROD_DESTROY_QP,
 465         ROCE_RAMROD_CREATE_UD_QP,
 466         ROCE_RAMROD_DESTROY_UD_QP,
 467         MAX_ROCE_RAMROD_CMD_ID
 468 };
 469
 470
 471
 472
 473
 474
 475 struct e4_mstorm_roce_req_conn_ag_ctx
 476 {
 477         u8 byte0 /* cdu_validation */;
 478         u8 byte1 /* state */;
 479         u8 flags0;
 480 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 481 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
 482 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 483 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
 484 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 485 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
 486 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 487 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
 488 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 489 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
 490         u8 flags1;
 491 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 492 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
 493 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 494 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
 495 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 496 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
 497 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 498 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
 499 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 500 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
 501 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 502 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
 503 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 504 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
 505 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 506 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
 507         __le16 word0 /* word0 */;
 508         __le16 word1 /* word1 */;
 509         __le32 reg0 /* reg0 */;
 510         __le32 reg1 /* reg1 */;
 511 };
 512
 513
 514 struct e4_mstorm_roce_resp_conn_ag_ctx
 515 {
 516         u8 byte0 /* cdu_validation */;
 517         u8 byte1 /* state */;
 518         u8 flags0;
 519 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 520 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
 521 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 522 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
 523 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
 524 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
 525 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
 526 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
 527 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
 528 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
 529         u8 flags1;
 530 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 531 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
 532 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 533 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
 534 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 535 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
 536 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 537 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
 538 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 539 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
 540 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 541 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
 542 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 543 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
 544 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 545 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
 546         __le16 word0 /* word0 */;
 547         __le16 word1 /* word1 */;
 548         __le32 reg0 /* reg0 */;
 549         __le32 reg1 /* reg1 */;
 550 };
 551
 552
 553 struct e4_tstorm_roce_req_conn_ag_ctx
 554 {
 555         u8 reserved0 /* cdu_validation */;
 556         u8 state /* state */;
 557         u8 flags0;
 558 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK                0x1 /* exist_in_qm0 */
 559 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT               0
 560 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK            0x1 /* exist_in_qm1 */
 561 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT           1
 562 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK        0x1 /* bit2 */
 563 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT       2
 564 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK                        0x1 /* bit3 */
 565 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT                       3
 566 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK                0x1 /* bit4 */
 567 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT               4
 568 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK                  0x1 /* bit5 */
 569 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT                 5
 570 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK                    0x3 /* timer0cf */
 571 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT                   6
 572         u8 flags1;
 573 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                         0x3 /* timer1cf */
 574 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                        0
 575 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK                 0x3 /* timer2cf */
 576 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT                2
 577 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK           0x3 /* timer_stop_all */
 578 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT          4
 579 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK                 0x3 /* cf4 */
 580 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT                6
 581         u8 flags2;
 582 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3 /* cf5 */
 583 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
 584 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK                0x3 /* cf6 */
 585 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT               2
 586 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK           0x3 /* cf7 */
 587 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT          4
 588 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK               0x3 /* cf8 */
 589 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT              6
 590         u8 flags3;
 591 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK     0x3 /* cf9 */
 592 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT    0
 593 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK       0x3 /* cf10 */
 594 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT      2
 595 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK                 0x1 /* cf0en */
 596 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT                4
 597 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK                       0x1 /* cf1en */
 598 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT                      5
 599 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK              0x1 /* cf2en */
 600 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT             6
 601 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK        0x1 /* cf3en */
 602 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT       7
 603         u8 flags4;
 604 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK              0x1 /* cf4en */
 605 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT             0
 606 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1 /* cf5en */
 607 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         1
 608 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK             0x1 /* cf6en */
 609 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT            2
 610 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK        0x1 /* cf7en */
 611 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT       3
 612 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK            0x1 /* cf8en */
 613 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT           4
 614 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK  0x1 /* cf9en */
 615 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
 616 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK    0x1 /* cf10en */
 617 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT   6
 618 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK                     0x1 /* rule0en */
 619 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT                    7
 620         u8 flags5;
 621 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK                     0x1 /* rule1en */
 622 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT                    0
 623 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK                     0x1 /* rule2en */
 624 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT                    1
 625 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK                     0x1 /* rule3en */
 626 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT                    2
 627 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK                     0x1 /* rule4en */
 628 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT                    3
 629 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK                     0x1 /* rule5en */
 630 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT                    4
 631 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK              0x1 /* rule6en */
 632 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT             5
 633 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK                     0x1 /* rule7en */
 634 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT                    6
 635 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK                     0x1 /* rule8en */
 636 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT                    7
 637         __le32 reg0 /* reg0 */;
 638         __le32 snd_nxt_psn /* reg1 */;
 639         __le32 snd_max_psn /* reg2 */;
 640         __le32 orq_prod /* reg3 */;
 641         __le32 reg4 /* reg4 */;
 642         __le32 reg5 /* reg5 */;
 643         __le32 reg6 /* reg6 */;
 644         __le32 reg7 /* reg7 */;
 645         __le32 reg8 /* reg8 */;
 646         u8 tx_cqe_error_type /* byte2 */;
 647         u8 orq_cache_idx /* byte3 */;
 648         __le16 snd_sq_cons_th /* word0 */;
 649         u8 byte4 /* byte4 */;
 650         u8 byte5 /* byte5 */;
 651         __le16 snd_sq_cons /* word1 */;
 652         __le16 word2 /* conn_dpi */;
 653         __le16 word3 /* word3 */;
 654         __le32 reg9 /* reg9 */;
 655         __le32 reg10 /* reg10 */;
 656 };
 657
 658
 659 struct e4_tstorm_roce_resp_conn_ag_ctx
 660 {
 661         u8 byte0 /* cdu_validation */;
 662         u8 state /* state */;
 663         u8 flags0;
 664 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK               0x1 /* exist_in_qm0 */
 665 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT              0
 666 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK  0x1 /* exist_in_qm1 */
 667 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
 668 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK                       0x1 /* bit2 */
 669 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT                      2
 670 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK                       0x1 /* bit3 */
 671 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT                      3
 672 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK               0x1 /* bit4 */
 673 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT              4
 674 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK                       0x1 /* bit5 */
 675 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT                      5
 676 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK                        0x3 /* timer0cf */
 677 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT                       6
 678         u8 flags1;
 679 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK                0x3 /* timer1cf */
 680 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT               0
 681 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK                0x3 /* timer2cf */
 682 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT               2
 683 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK                        0x3 /* timer_stop_all */
 684 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT                       4
 685 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK                0x3 /* cf4 */
 686 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT               6
 687         u8 flags2;
 688 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK            0x3 /* cf5 */
 689 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT           0
 690 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK                        0x3 /* cf6 */
 691 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT                       2
 692 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK                        0x3 /* cf7 */
 693 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT                       4
 694 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK                        0x3 /* cf8 */
 695 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT                       6
 696         u8 flags3;
 697 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK                        0x3 /* cf9 */
 698 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT                       0
 699 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK                       0x3 /* cf10 */
 700 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT                      2
 701 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK                      0x1 /* cf0en */
 702 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT                     4
 703 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK             0x1 /* cf1en */
 704 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT            5
 705 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK             0x1 /* cf2en */
 706 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT            6
 707 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK                      0x1 /* cf3en */
 708 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT                     7
 709         u8 flags4;
 710 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK             0x1 /* cf4en */
 711 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT            0
 712 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK         0x1 /* cf5en */
 713 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT        1
 714 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK                      0x1 /* cf6en */
 715 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT                     2
 716 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK                      0x1 /* cf7en */
 717 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT                     3
 718 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK                      0x1 /* cf8en */
 719 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT                     4
 720 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK                      0x1 /* cf9en */
 721 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT                     5
 722 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK                     0x1 /* cf10en */
 723 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT                    6
 724 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK                    0x1 /* rule0en */
 725 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT                   7
 726         u8 flags5;
 727 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK                    0x1 /* rule1en */
 728 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT                   0
 729 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK                    0x1 /* rule2en */
 730 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT                   1
 731 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK                    0x1 /* rule3en */
 732 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT                   2
 733 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK                    0x1 /* rule4en */
 734 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT                   3
 735 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK                    0x1 /* rule5en */
 736 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT                   4
 737 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK                 0x1 /* rule6en */
 738 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT                5
 739 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK                    0x1 /* rule7en */
 740 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT                   6
 741 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK                    0x1 /* rule8en */
 742 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT                   7
 743         __le32 psn_and_rxmit_id_echo /* reg0 */;
 744         __le32 reg1 /* reg1 */;
 745         __le32 reg2 /* reg2 */;
 746         __le32 reg3 /* reg3 */;
 747         __le32 reg4 /* reg4 */;
 748         __le32 reg5 /* reg5 */;
 749         __le32 reg6 /* reg6 */;
 750         __le32 reg7 /* reg7 */;
 751         __le32 reg8 /* reg8 */;
 752         u8 tx_async_error_type /* byte2 */;
 753         u8 byte3 /* byte3 */;
 754         __le16 rq_cons /* word0 */;
 755         u8 byte4 /* byte4 */;
 756         u8 byte5 /* byte5 */;
 757         __le16 rq_prod /* word1 */;
 758         __le16 conn_dpi /* conn_dpi */;
 759         __le16 irq_cons /* word3 */;
 760         __le32 num_invlidated_mw /* reg9 */;
 761         __le32 reg10 /* reg10 */;
 762 };
 763
 764
 765 struct e4_ustorm_roce_req_conn_ag_ctx
 766 {
 767         u8 byte0 /* cdu_validation */;
 768         u8 byte1 /* state */;
 769         u8 flags0;
 770 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 771 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
 772 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 773 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
 774 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3 /* timer0cf */
 775 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
 776 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3 /* timer1cf */
 777 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
 778 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3 /* timer2cf */
 779 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
 780         u8 flags1;
 781 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
 782 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT     0
 783 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK      0x3 /* cf4 */
 784 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT     2
 785 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK      0x3 /* cf5 */
 786 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT     4
 787 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK      0x3 /* cf6 */
 788 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT     6
 789         u8 flags2;
 790 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 791 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
 792 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 793 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
 794 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 795 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
 796 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
 797 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT   3
 798 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
 799 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT   4
 800 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
 801 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT   5
 802 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
 803 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT   6
 804 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 805 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
 806         u8 flags3;
 807 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 808 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
 809 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 810 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
 811 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 812 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
 813 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 814 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
 815 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
 816 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
 817 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK  0x1 /* rule6en */
 818 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
 819 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK  0x1 /* rule7en */
 820 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
 821 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK  0x1 /* rule8en */
 822 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
 823         u8 byte2 /* byte2 */;
 824         u8 byte3 /* byte3 */;
 825         __le16 word0 /* conn_dpi */;
 826         __le16 word1 /* word1 */;
 827         __le32 reg0 /* reg0 */;
 828         __le32 reg1 /* reg1 */;
 829         __le32 reg2 /* reg2 */;
 830         __le32 reg3 /* reg3 */;
 831         __le16 word2 /* word2 */;
 832         __le16 word3 /* word3 */;
 833 };
 834
 835
 836 struct e4_ustorm_roce_resp_conn_ag_ctx
 837 {
 838         u8 byte0 /* cdu_validation */;
 839         u8 byte1 /* state */;
 840         u8 flags0;
 841 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
 842 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
 843 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
 844 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
 845 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3 /* timer0cf */
 846 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
 847 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3 /* timer1cf */
 848 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
 849 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3 /* timer2cf */
 850 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
 851         u8 flags1;
 852 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK      0x3 /* timer_stop_all */
 853 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT     0
 854 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK      0x3 /* cf4 */
 855 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT     2
 856 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK      0x3 /* cf5 */
 857 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT     4
 858 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK      0x3 /* cf6 */
 859 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT     6
 860         u8 flags2;
 861 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
 862 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
 863 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
 864 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
 865 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
 866 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
 867 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK    0x1 /* cf3en */
 868 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT   3
 869 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK    0x1 /* cf4en */
 870 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT   4
 871 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK    0x1 /* cf5en */
 872 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT   5
 873 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK    0x1 /* cf6en */
 874 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT   6
 875 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
 876 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
 877         u8 flags3;
 878 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
 879 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
 880 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
 881 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
 882 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
 883 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
 884 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
 885 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
 886 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK  0x1 /* rule5en */
 887 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
 888 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK  0x1 /* rule6en */
 889 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
 890 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK  0x1 /* rule7en */
 891 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
 892 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK  0x1 /* rule8en */
 893 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
 894         u8 byte2 /* byte2 */;
 895         u8 byte3 /* byte3 */;
 896         __le16 word0 /* conn_dpi */;
 897         __le16 word1 /* word1 */;
 898         __le32 reg0 /* reg0 */;
 899         __le32 reg1 /* reg1 */;
 900         __le32 reg2 /* reg2 */;
 901         __le32 reg3 /* reg3 */;
 902         __le16 word2 /* word2 */;
 903         __le16 word3 /* word3 */;
 904 };
 905
 906
 907 struct e4_xstorm_roce_req_conn_ag_ctx
 908 {
 909         u8 reserved0 /* cdu_validation */;
 910         u8 state /* state */;
 911         u8 flags0;
 912 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
 913 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
 914 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK           0x1 /* exist_in_qm1 */
 915 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT          1
 916 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK           0x1 /* exist_in_qm2 */
 917 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT          2
 918 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK        0x1 /* exist_in_qm3 */
 919 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT       3
 920 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK           0x1 /* bit4 */
 921 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT          4
 922 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK           0x1 /* cf_array_active */
 923 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT          5
 924 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK           0x1 /* bit6 */
 925 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT          6
 926 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK           0x1 /* bit7 */
 927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT          7
 928         u8 flags1;
 929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK           0x1 /* bit8 */
 930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT          0
 931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK           0x1 /* bit9 */
 932 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT          1
 933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK               0x1 /* bit10 */
 934 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT              2
 935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK               0x1 /* bit11 */
 936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT              3
 937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK               0x1 /* bit12 */
 938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT              4
 939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK               0x1 /* bit13 */
 940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT              5
 941 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK         0x1 /* bit14 */
 942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT        6
 943 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK        0x1 /* bit15 */
 944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT       7
 945         u8 flags2;
 946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK                 0x3 /* timer0cf */
 947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT                0
 948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                 0x3 /* timer1cf */
 949 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                2
 950 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK                 0x3 /* timer2cf */
 951 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT                4
 952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK                 0x3 /* timer_stop_all */
 953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT                6
 954         u8 flags3;
 955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK         0x3 /* cf4 */
 956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT        0
 957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK         0x3 /* cf5 */
 958 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT        2
 959 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK        0x3 /* cf6 */
 960 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT       4
 961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK         0x3 /* cf7 */
 962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT        6
 963         u8 flags4;
 964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK                 0x3 /* cf8 */
 965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT                0
 966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK                 0x3 /* cf9 */
 967 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT                2
 968 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK                0x3 /* cf10 */
 969 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT               4
 970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK                0x3 /* cf11 */
 971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT               6
 972         u8 flags5;
 973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK                0x3 /* cf12 */
 974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT               0
 975 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK                0x3 /* cf13 */
 976 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT               2
 977 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK        0x3 /* cf14 */
 978 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT       4
 979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK                0x3 /* cf15 */
 980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT               6
 981         u8 flags6;
 982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK                0x3 /* cf16 */
 983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT               0
 984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK                0x3 /* cf_array_cf */
 985 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT               2
 986 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK                0x3 /* cf18 */
 987 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT               4
 988 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK                0x3 /* cf19 */
 989 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT               6
 990         u8 flags7;
 991 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK                0x3 /* cf20 */
 992 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT               0
 993 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK                0x3 /* cf21 */
 994 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT               2
 995 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK           0x3 /* cf22 */
 996 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT          4
 997 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK               0x1 /* cf0en */
 998 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT              6
 999 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK               0x1 /* cf1en */
1000 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT              7
1001         u8 flags8;
1002 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK               0x1 /* cf2en */
1003 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT              0
1004 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK               0x1 /* cf3en */
1005 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT              1
1006 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK      0x1 /* cf4en */
1007 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT     2
1008 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK      0x1 /* cf5en */
1009 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT     3
1010 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK     0x1 /* cf6en */
1011 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT    4
1012 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK      0x1 /* cf7en */
1013 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT     5
1014 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK               0x1 /* cf8en */
1015 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT              6
1016 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK               0x1 /* cf9en */
1017 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT              7
1018         u8 flags9;
1019 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK              0x1 /* cf10en */
1020 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT             0
1021 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK              0x1 /* cf11en */
1022 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT             1
1023 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK              0x1 /* cf12en */
1024 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT             2
1025 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK              0x1 /* cf13en */
1026 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT             3
1027 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK     0x1 /* cf14en */
1028 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT    4
1029 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK              0x1 /* cf15en */
1030 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT             5
1031 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK              0x1 /* cf16en */
1032 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT             6
1033 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK              0x1 /* cf_array_cf_en */
1034 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT             7
1035         u8 flags10;
1036 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK              0x1 /* cf18en */
1037 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT             0
1038 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK              0x1 /* cf19en */
1039 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT             1
1040 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK              0x1 /* cf20en */
1041 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT             2
1042 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK              0x1 /* cf21en */
1043 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT             3
1044 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK        0x1 /* cf22en */
1045 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT       4
1046 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK              0x1 /* cf23en */
1047 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT             5
1048 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK             0x1 /* rule0en */
1049 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT            6
1050 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK             0x1 /* rule1en */
1051 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT            7
1052         u8 flags11;
1053 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK             0x1 /* rule2en */
1054 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT            0
1055 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK             0x1 /* rule3en */
1056 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT            1
1057 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK             0x1 /* rule4en */
1058 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT            2
1059 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK             0x1 /* rule5en */
1060 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT            3
1061 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK             0x1 /* rule6en */
1062 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT            4
1063 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK  0x1 /* rule7en */
1064 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
1065 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK        0x1 /* rule8en */
1066 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT       6
1067 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK             0x1 /* rule9en */
1068 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT            7
1069         u8 flags12;
1070 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK          0x1 /* rule10en */
1071 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT         0
1072 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK            0x1 /* rule11en */
1073 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT           1
1074 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK        0x1 /* rule12en */
1075 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT       2
1076 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK        0x1 /* rule13en */
1077 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT       3
1078 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK   0x1 /* rule14en */
1079 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT  4
1080 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK            0x1 /* rule15en */
1081 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT           5
1082 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK   0x1 /* rule16en */
1083 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT  6
1084 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK     0x1 /* rule17en */
1085 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT    7
1086         u8 flags13;
1087 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK            0x1 /* rule18en */
1088 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT           0
1089 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK            0x1 /* rule19en */
1090 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT           1
1091 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK        0x1 /* rule20en */
1092 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT       2
1093 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK        0x1 /* rule21en */
1094 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT       3
1095 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK        0x1 /* rule22en */
1096 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT       4
1097 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK        0x1 /* rule23en */
1098 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT       5
1099 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK        0x1 /* rule24en */
1100 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT       6
1101 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK        0x1 /* rule25en */
1102 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT       7
1103         u8 flags14;
1104 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK      0x1 /* bit16 */
1105 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT     0
1106 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK               0x1 /* bit17 */
1107 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT              1
1108 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK        0x3 /* bit18 */
1109 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT       2
1110 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK            0x1 /* bit20 */
1111 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT           4
1112 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK    0x1 /* bit21 */
1113 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT   5
1114 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK                0x3 /* cf23 */
1115 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT               6
1116         u8 byte2 /* byte2 */;
1117         __le16 physical_q0 /* physical_q0 */;
1118         __le16 word1 /* physical_q1 */;
1119         __le16 sq_cmp_cons /* physical_q2 */;
1120         __le16 sq_cons /* word3 */;
1121         __le16 sq_prod /* word4 */;
1122         __le16 word5 /* word5 */;
1123         __le16 conn_dpi /* conn_dpi */;
1124         u8 byte3 /* byte3 */;
1125         u8 byte4 /* byte4 */;
1126         u8 byte5 /* byte5 */;
1127         u8 byte6 /* byte6 */;
1128         __le32 lsn /* reg0 */;
1129         __le32 ssn /* reg1 */;
1130         __le32 snd_una_psn /* reg2 */;
1131         __le32 snd_nxt_psn /* reg3 */;
1132         __le32 reg4 /* reg4 */;
1133         __le32 orq_cons_th /* cf_array0 */;
1134         __le32 orq_cons /* cf_array1 */;
1135 };
1136
1137
1138 struct e4_xstorm_roce_resp_conn_ag_ctx
1139 {
1140         u8 reserved0 /* cdu_validation */;
1141         u8 state /* state */;
1142         u8 flags0;
1143 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
1144 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
1145 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK         0x1 /* exist_in_qm1 */
1146 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT        1
1147 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK         0x1 /* exist_in_qm2 */
1148 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT        2
1149 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
1150 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
1151 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK         0x1 /* bit4 */
1152 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT        4
1153 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK         0x1 /* cf_array_active */
1154 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT        5
1155 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK         0x1 /* bit6 */
1156 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT        6
1157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK         0x1 /* bit7 */
1158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT        7
1159         u8 flags1;
1160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK         0x1 /* bit8 */
1161 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT        0
1162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK         0x1 /* bit9 */
1163 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT        1
1164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK             0x1 /* bit10 */
1165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT            2
1166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK             0x1 /* bit11 */
1167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT            3
1168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK             0x1 /* bit12 */
1169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT            4
1170 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK             0x1 /* bit13 */
1171 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT            5
1172 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK       0x1 /* bit14 */
1173 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT      6
1174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1 /* bit15 */
1175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
1176         u8 flags2;
1177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK               0x3 /* timer0cf */
1178 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT              0
1179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK               0x3 /* timer1cf */
1180 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT              2
1181 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK               0x3 /* timer2cf */
1182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT              4
1183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK               0x3 /* timer_stop_all */
1184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT              6
1185         u8 flags3;
1186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK          0x3 /* cf4 */
1187 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT         0
1188 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK       0x3 /* cf5 */
1189 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT      2
1190 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK      0x3 /* cf6 */
1191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT     4
1192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
1193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
1194         u8 flags4;
1195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK               0x3 /* cf8 */
1196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT              0
1197 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK               0x3 /* cf9 */
1198 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT              2
1199 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK              0x3 /* cf10 */
1200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT             4
1201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK              0x3 /* cf11 */
1202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT             6
1203         u8 flags5;
1204 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK              0x3 /* cf12 */
1205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT             0
1206 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK              0x3 /* cf13 */
1207 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT             2
1208 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK              0x3 /* cf14 */
1209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT             4
1210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK              0x3 /* cf15 */
1211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT             6
1212         u8 flags6;
1213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK              0x3 /* cf16 */
1214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT             0
1215 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK              0x3 /* cf_array_cf */
1216 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT             2
1217 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK              0x3 /* cf18 */
1218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT             4
1219 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK              0x3 /* cf19 */
1220 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT             6
1221         u8 flags7;
1222 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK              0x3 /* cf20 */
1223 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT             0
1224 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK              0x3 /* cf21 */
1225 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT             2
1226 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK         0x3 /* cf22 */
1227 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT        4
1228 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK             0x1 /* cf0en */
1229 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT            6
1230 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK             0x1 /* cf1en */
1231 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT            7
1232         u8 flags8;
1233 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK             0x1 /* cf2en */
1234 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT            0
1235 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK             0x1 /* cf3en */
1236 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT            1
1237 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK       0x1 /* cf4en */
1238 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT      2
1239 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK    0x1 /* cf5en */
1240 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT   3
1241 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK   0x1 /* cf6en */
1242 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT  4
1243 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
1244 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
1245 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK             0x1 /* cf8en */
1246 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT            6
1247 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK             0x1 /* cf9en */
1248 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT            7
1249         u8 flags9;
1250 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK            0x1 /* cf10en */
1251 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT           0
1252 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK            0x1 /* cf11en */
1253 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT           1
1254 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK            0x1 /* cf12en */
1255 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT           2
1256 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK            0x1 /* cf13en */
1257 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT           3
1258 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK            0x1 /* cf14en */
1259 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT           4
1260 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK            0x1 /* cf15en */
1261 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT           5
1262 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK            0x1 /* cf16en */
1263 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT           6
1264 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK            0x1 /* cf_array_cf_en */
1265 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT           7
1266         u8 flags10;
1267 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK            0x1 /* cf18en */
1268 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT           0
1269 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK            0x1 /* cf19en */
1270 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT           1
1271 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK            0x1 /* cf20en */
1272 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT           2
1273 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK            0x1 /* cf21en */
1274 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT           3
1275 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1 /* cf22en */
1276 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
1277 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK            0x1 /* cf23en */
1278 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT           5
1279 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK           0x1 /* rule0en */
1280 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT          6
1281 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK           0x1 /* rule1en */
1282 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT          7
1283         u8 flags11;
1284 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK           0x1 /* rule2en */
1285 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT          0
1286 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK           0x1 /* rule3en */
1287 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT          1
1288 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK           0x1 /* rule4en */
1289 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT          2
1290 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK           0x1 /* rule5en */
1291 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT          3
1292 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK           0x1 /* rule6en */
1293 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT          4
1294 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK           0x1 /* rule7en */
1295 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT          5
1296 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK      0x1 /* rule8en */
1297 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
1298 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK           0x1 /* rule9en */
1299 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT          7
1300         u8 flags12;
1301 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK          0x1 /* rule10en */
1302 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT         0
1303 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK  0x1 /* rule11en */
1304 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
1305 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK      0x1 /* rule12en */
1306 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
1307 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK      0x1 /* rule13en */
1308 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
1309 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK          0x1 /* rule14en */
1310 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT         4
1311 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK          0x1 /* rule15en */
1312 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT         5
1313 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK          0x1 /* rule16en */
1314 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT         6
1315 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK          0x1 /* rule17en */
1316 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT         7
1317         u8 flags13;
1318 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK          0x1 /* rule18en */
1319 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT         0
1320 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK          0x1 /* rule19en */
1321 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT         1
1322 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK      0x1 /* rule20en */
1323 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
1324 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK      0x1 /* rule21en */
1325 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
1326 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK      0x1 /* rule22en */
1327 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
1328 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK      0x1 /* rule23en */
1329 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
1330 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK      0x1 /* rule24en */
1331 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
1332 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK      0x1 /* rule25en */
1333 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
1334         u8 flags14;
1335 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK             0x1 /* bit16 */
1336 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT            0
1337 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK             0x1 /* bit17 */
1338 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT            1
1339 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK             0x1 /* bit18 */
1340 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT            2
1341 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK             0x1 /* bit19 */
1342 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT            3
1343 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK             0x1 /* bit20 */
1344 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT            4
1345 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK             0x1 /* bit21 */
1346 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT            5
1347 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK              0x3 /* cf23 */
1348 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT             6
1349         u8 byte2 /* byte2 */;
1350         __le16 physical_q0 /* physical_q0 */;
1351         __le16 word1 /* physical_q1 */;
1352         __le16 irq_prod /* physical_q2 */;
1353         __le16 word3 /* word3 */;
1354         __le16 word4 /* word4 */;
1355         __le16 e5_reserved1 /* word5 */;
1356         __le16 irq_cons /* conn_dpi */;
1357         u8 rxmit_opcode /* byte3 */;
1358         u8 byte4 /* byte4 */;
1359         u8 byte5 /* byte5 */;
1360         u8 byte6 /* byte6 */;
1361         __le32 rxmit_psn_and_id /* reg0 */;
1362         __le32 rxmit_bytes_length /* reg1 */;
1363         __le32 psn /* reg2 */;
1364         __le32 reg3 /* reg3 */;
1365         __le32 reg4 /* reg4 */;
1366         __le32 reg5 /* cf_array0 */;
1367         __le32 msn_and_syndrome /* cf_array1 */;
1368 };
1369
1370
1371 struct e4_ystorm_roce_req_conn_ag_ctx
1372 {
1373         u8 byte0 /* cdu_validation */;
1374         u8 byte1 /* state */;
1375         u8 flags0;
1376 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1377 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
1378 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1379 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
1380 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1381 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
1382 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1383 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
1384 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1385 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
1386         u8 flags1;
1387 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1388 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
1389 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1390 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
1391 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1392 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
1393 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1394 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
1395 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1396 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
1397 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1398 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
1399 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1400 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
1401 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1402 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
1403         u8 byte2 /* byte2 */;
1404         u8 byte3 /* byte3 */;
1405         __le16 word0 /* word0 */;
1406         __le32 reg0 /* reg0 */;
1407         __le32 reg1 /* reg1 */;
1408         __le16 word1 /* word1 */;
1409         __le16 word2 /* word2 */;
1410         __le16 word3 /* word3 */;
1411         __le16 word4 /* word4 */;
1412         __le32 reg2 /* reg2 */;
1413         __le32 reg3 /* reg3 */;
1414 };
1415
1416
1417 struct e4_ystorm_roce_resp_conn_ag_ctx
1418 {
1419         u8 byte0 /* cdu_validation */;
1420         u8 byte1 /* state */;
1421         u8 flags0;
1422 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1423 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
1424 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1425 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
1426 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1427 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
1428 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1429 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
1430 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1431 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
1432         u8 flags1;
1433 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1434 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
1435 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1436 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
1437 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1438 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
1439 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1440 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
1441 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1442 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
1443 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1444 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
1445 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1446 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
1447 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1448 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
1449         u8 byte2 /* byte2 */;
1450         u8 byte3 /* byte3 */;
1451         __le16 word0 /* word0 */;
1452         __le32 reg0 /* reg0 */;
1453         __le32 reg1 /* reg1 */;
1454         __le16 word1 /* word1 */;
1455         __le16 word2 /* word2 */;
1456         __le16 word3 /* word3 */;
1457         __le16 word4 /* word4 */;
1458         __le32 reg2 /* reg2 */;
1459         __le32 reg3 /* reg3 */;
1460 };
1461
1462
1463 struct E5XstormRoceConnAgCtxDqExtLdPart
1464 {
1465         u8 reserved0 /* cdu_validation */;
1466         u8 state_and_core_id /* state_and_core_id */;
1467         u8 flags0;
1468 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
1469 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT       0
1470 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_MASK           0x1 /* exist_in_qm1 */
1471 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_SHIFT          1
1472 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_MASK           0x1 /* exist_in_qm2 */
1473 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_SHIFT          2
1474 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK        0x1 /* exist_in_qm3 */
1475 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT       3
1476 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_MASK           0x1 /* bit4 */
1477 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_SHIFT          4
1478 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_MASK           0x1 /* cf_array_active */
1479 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_SHIFT          5
1480 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_MASK           0x1 /* bit6 */
1481 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_SHIFT          6
1482 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_MASK           0x1 /* bit7 */
1483 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_SHIFT          7
1484         u8 flags1;
1485 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_MASK           0x1 /* bit8 */
1486 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_SHIFT          0
1487 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_MASK           0x1 /* bit9 */
1488 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_SHIFT          1
1489 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK               0x1 /* bit10 */
1490 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT              2
1491 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK               0x1 /* bit11 */
1492 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT              3
1493 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK               0x1 /* bit12 */
1494 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT              4
1495 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK               0x1 /* bit13 */
1496 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT              5
1497 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_MASK         0x1 /* bit14 */
1498 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_SHIFT        6
1499 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK        0x1 /* bit15 */
1500 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT       7
1501         u8 flags2;
1502 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK                 0x3 /* timer0cf */
1503 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT                0
1504 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK                 0x3 /* timer1cf */
1505 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT                2
1506 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK                 0x3 /* timer2cf */
1507 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT                4
1508 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK                 0x3 /* timer_stop_all */
1509 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT                6
1510         u8 flags3;
1511 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_MASK         0x3 /* cf4 */
1512 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_SHIFT        0
1513 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_MASK         0x3 /* cf5 */
1514 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_SHIFT        2
1515 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_MASK        0x3 /* cf6 */
1516 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_SHIFT       4
1517 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK         0x3 /* cf7 */
1518 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT        6
1519         u8 flags4;
1520 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK                 0x3 /* cf8 */
1521 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT                0
1522 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK                 0x3 /* cf9 */
1523 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT                2
1524 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK                0x3 /* cf10 */
1525 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT               4
1526 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK                0x3 /* cf11 */
1527 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT               6
1528         u8 flags5;
1529 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK                0x3 /* cf12 */
1530 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT               0
1531 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK                0x3 /* cf13 */
1532 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT               2
1533 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_MASK        0x3 /* cf14 */
1534 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_SHIFT       4
1535 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK                0x3 /* cf15 */
1536 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT               6
1537         u8 flags6;
1538 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK                0x3 /* cf16 */
1539 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT               0
1540 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK                0x3 /* cf_array_cf */
1541 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT               2
1542 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK                0x3 /* cf18 */
1543 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT               4
1544 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK                0x3 /* cf19 */
1545 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT               6
1546         u8 flags7;
1547 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK                0x3 /* cf20 */
1548 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT               0
1549 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK                0x3 /* cf21 */
1550 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT               2
1551 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK           0x3 /* cf22 */
1552 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT          4
1553 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK               0x1 /* cf0en */
1554 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT              6
1555 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK               0x1 /* cf1en */
1556 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT              7
1557         u8 flags8;
1558 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK               0x1 /* cf2en */
1559 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT              0
1560 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK               0x1 /* cf3en */
1561 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT              1
1562 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_MASK      0x1 /* cf4en */
1563 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_SHIFT     2
1564 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_MASK      0x1 /* cf5en */
1565 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_SHIFT     3
1566 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_MASK     0x1 /* cf6en */
1567 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_SHIFT    4
1568 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK      0x1 /* cf7en */
1569 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT     5
1570 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK               0x1 /* cf8en */
1571 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT              6
1572 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK               0x1 /* cf9en */
1573 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT              7
1574         u8 flags9;
1575 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK              0x1 /* cf10en */
1576 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT             0
1577 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK              0x1 /* cf11en */
1578 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT             1
1579 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK              0x1 /* cf12en */
1580 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT             2
1581 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK              0x1 /* cf13en */
1582 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT             3
1583 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_MASK     0x1 /* cf14en */
1584 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_SHIFT    4
1585 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK              0x1 /* cf15en */
1586 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT             5
1587 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK              0x1 /* cf16en */
1588 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT             6
1589 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK              0x1 /* cf_array_cf_en */
1590 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT             7
1591         u8 flags10;
1592 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK              0x1 /* cf18en */
1593 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT             0
1594 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK              0x1 /* cf19en */
1595 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT             1
1596 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK              0x1 /* cf20en */
1597 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT             2
1598 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK              0x1 /* cf21en */
1599 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT             3
1600 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK        0x1 /* cf22en */
1601 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT       4
1602 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK              0x1 /* cf23en */
1603 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT             5
1604 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK             0x1 /* rule0en */
1605 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT            6
1606 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK             0x1 /* rule1en */
1607 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT            7
1608         u8 flags11;
1609 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK             0x1 /* rule2en */
1610 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT            0
1611 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK             0x1 /* rule3en */
1612 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT            1
1613 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK             0x1 /* rule4en */
1614 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT            2
1615 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK             0x1 /* rule5en */
1616 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT            3
1617 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK             0x1 /* rule6en */
1618 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT            4
1619 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_MASK  0x1 /* rule7en */
1620 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_SHIFT 5
1621 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK        0x1 /* rule8en */
1622 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT       6
1623 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK             0x1 /* rule9en */
1624 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT            7
1625         u8 flags12;
1626 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_MASK          0x1 /* rule10en */
1627 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_SHIFT         0
1628 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK            0x1 /* rule11en */
1629 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT           1
1630 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK        0x1 /* rule12en */
1631 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT       2
1632 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK        0x1 /* rule13en */
1633 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT       3
1634 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_MASK   0x1 /* rule14en */
1635 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_SHIFT  4
1636 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK            0x1 /* rule15en */
1637 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT           5
1638 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_MASK   0x1 /* rule16en */
1639 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_SHIFT  6
1640 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_MASK     0x1 /* rule17en */
1641 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_SHIFT    7
1642         u8 flags13;
1643 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK            0x1 /* rule18en */
1644 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT           0
1645 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK            0x1 /* rule19en */
1646 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT           1
1647 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK        0x1 /* rule20en */
1648 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT       2
1649 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK        0x1 /* rule21en */
1650 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT       3
1651 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK        0x1 /* rule22en */
1652 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT       4
1653 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK        0x1 /* rule23en */
1654 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT       5
1655 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK        0x1 /* rule24en */
1656 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT       6
1657 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK        0x1 /* rule25en */
1658 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT       7
1659         u8 flags14;
1660 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_MASK      0x1 /* bit16 */
1661 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_SHIFT     0
1662 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK               0x1 /* bit17 */
1663 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT              1
1664 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK        0x3 /* bit18 */
1665 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT       2
1666 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK            0x1 /* bit20 */
1667 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT           4
1668 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK    0x1 /* bit21 */
1669 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT   5
1670 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK                0x3 /* cf23 */
1671 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT               6
1672         u8 byte2 /* byte2 */;
1673         __le16 physical_q0 /* physical_q0 */;
1674         __le16 word1 /* physical_q1 */;
1675         __le16 sq_cmp_cons /* physical_q2 */;
1676         __le16 sq_cons /* word3 */;
1677         __le16 sq_prod /* word4 */;
1678         __le16 word5 /* word5 */;
1679         __le16 conn_dpi /* conn_dpi */;
1680         u8 byte3 /* byte3 */;
1681         u8 byte4 /* byte4 */;
1682         u8 byte5 /* byte5 */;
1683         u8 byte6 /* byte6 */;
1684         __le32 lsn /* reg0 */;
1685         __le32 ssn /* reg1 */;
1686         __le32 snd_una_psn /* reg2 */;
1687         __le32 snd_nxt_psn /* reg3 */;
1688         __le32 reg4 /* reg4 */;
1689         __le32 orq_cons_th /* cf_array0 */;
1690         __le32 orq_cons /* cf_array1 */;
1691         u8 flags15;
1692 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_MASK        0x1 /* bit22 */
1693 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_SHIFT       0
1694 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_MASK        0x1 /* bit23 */
1695 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_SHIFT       1
1696 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_MASK        0x1 /* bit24 */
1697 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_SHIFT       2
1698 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_MASK        0x3 /* cf24 */
1699 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_SHIFT       3
1700 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_MASK        0x1 /* cf24en */
1701 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_SHIFT       5
1702 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_MASK        0x1 /* rule26en */
1703 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_SHIFT       6
1704 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_MASK        0x1 /* rule27en */
1705 #define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_SHIFT       7
1706         u8 byte7 /* byte7 */;
1707         __le16 word7 /* word7 */;
1708         __le16 word8 /* word8 */;
1709         __le16 word9 /* word9 */;
1710         __le16 word10 /* word10 */;
1711         __le16 tx_rdma_edpm_usg_cnt /* word11 */;
1712         __le32 reg7 /* reg7 */;
1713         __le32 reg8 /* reg8 */;
1714         __le32 reg9 /* reg9 */;
1715         u8 byte8 /* byte8 */;
1716         u8 byte9 /* byte9 */;
1717         u8 byte10 /* byte10 */;
1718         u8 byte11 /* byte11 */;
1719         u8 byte12 /* byte12 */;
1720         u8 byte13 /* byte13 */;
1721         u8 byte14 /* byte14 */;
1722         u8 byte15 /* byte15 */;
1723         __le32 reg10 /* reg10 */;
1724         __le32 reg11 /* reg11 */;
1725         __le32 reg12 /* reg12 */;
1726         __le32 reg13 /* reg13 */;
1727 };
1728
1729
1730 struct e5_mstorm_roce_req_conn_ag_ctx
1731 {
1732         u8 byte0 /* cdu_validation */;
1733         u8 byte1 /* state_and_core_id */;
1734         u8 flags0;
1735 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1736 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
1737 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1738 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
1739 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1740 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
1741 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1742 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
1743 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1744 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
1745         u8 flags1;
1746 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1747 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
1748 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1749 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
1750 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1751 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
1752 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1753 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
1754 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1755 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
1756 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1757 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
1758 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1759 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
1760 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1761 #define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
1762         __le16 word0 /* word0 */;
1763         __le16 word1 /* word1 */;
1764         __le32 reg0 /* reg0 */;
1765         __le32 reg1 /* reg1 */;
1766 };
1767
1768
1769 struct e5_mstorm_roce_resp_conn_ag_ctx
1770 {
1771         u8 byte0 /* cdu_validation */;
1772         u8 byte1 /* state_and_core_id */;
1773         u8 flags0;
1774 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
1775 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
1776 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
1777 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
1778 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
1779 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
1780 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
1781 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
1782 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
1783 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
1784         u8 flags1;
1785 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
1786 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
1787 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
1788 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
1789 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
1790 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
1791 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
1792 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
1793 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
1794 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
1795 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
1796 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
1797 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
1798 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
1799 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
1800 #define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
1801         __le16 word0 /* word0 */;
1802         __le16 word1 /* word1 */;
1803         __le32 reg0 /* reg0 */;
1804         __le32 reg1 /* reg1 */;
1805 };
1806
1807
1808 struct e5_tstorm_roce_req_conn_ag_ctx
1809 {
1810         u8 reserved0 /* cdu_validation */;
1811         u8 state_and_core_id /* state_and_core_id */;
1812         u8 flags0;
1813 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK                0x1 /* exist_in_qm0 */
1814 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT               0
1815 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK            0x1 /* exist_in_qm1 */
1816 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT           1
1817 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK        0x1 /* bit2 */
1818 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT       2
1819 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK                        0x1 /* bit3 */
1820 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT                       3
1821 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK                0x1 /* bit4 */
1822 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT               4
1823 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK                  0x1 /* bit5 */
1824 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT                 5
1825 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK                    0x3 /* timer0cf */
1826 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT                   6
1827         u8 flags1;
1828 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                         0x3 /* timer1cf */
1829 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                        0
1830 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK                 0x3 /* timer2cf */
1831 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT                2
1832 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK           0x3 /* timer_stop_all */
1833 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT          4
1834 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK                 0x3 /* cf4 */
1835 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT                6
1836         u8 flags2;
1837 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3 /* cf5 */
1838 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
1839 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK                0x3 /* cf6 */
1840 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT               2
1841 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK           0x3 /* cf7 */
1842 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT          4
1843 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK               0x3 /* cf8 */
1844 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT              6
1845         u8 flags3;
1846 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK     0x3 /* cf9 */
1847 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT    0
1848 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK       0x3 /* cf10 */
1849 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT      2
1850 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK                 0x1 /* cf0en */
1851 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT                4
1852 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK                       0x1 /* cf1en */
1853 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT                      5
1854 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK              0x1 /* cf2en */
1855 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT             6
1856 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK        0x1 /* cf3en */
1857 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT       7
1858         u8 flags4;
1859 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK              0x1 /* cf4en */
1860 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT             0
1861 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1 /* cf5en */
1862 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         1
1863 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK             0x1 /* cf6en */
1864 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT            2
1865 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK        0x1 /* cf7en */
1866 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT       3
1867 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK            0x1 /* cf8en */
1868 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT           4
1869 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK  0x1 /* cf9en */
1870 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
1871 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK    0x1 /* cf10en */
1872 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT   6
1873 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK                     0x1 /* rule0en */
1874 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT                    7
1875         u8 flags5;
1876 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK                     0x1 /* rule1en */
1877 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT                    0
1878 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK                     0x1 /* rule2en */
1879 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT                    1
1880 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK                     0x1 /* rule3en */
1881 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT                    2
1882 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK                     0x1 /* rule4en */
1883 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT                    3
1884 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK                     0x1 /* rule5en */
1885 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT                    4
1886 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK              0x1 /* rule6en */
1887 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT             5
1888 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK                     0x1 /* rule7en */
1889 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT                    6
1890 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK                     0x1 /* rule8en */
1891 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT                    7
1892         u8 flags6;
1893 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK                0x1 /* bit6 */
1894 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT               0
1895 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK                0x1 /* bit7 */
1896 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT               1
1897 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK                0x1 /* bit8 */
1898 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT               2
1899 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK                0x3 /* cf11 */
1900 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT               3
1901 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK                0x1 /* cf11en */
1902 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT               5
1903 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK                0x1 /* rule9en */
1904 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT               6
1905 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_MASK                0x1 /* rule10en */
1906 #define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_SHIFT               7
1907         u8 tx_cqe_error_type /* byte2 */;
1908         __le16 snd_sq_cons_th /* word0 */;
1909         __le32 reg0 /* reg0 */;
1910         __le32 snd_nxt_psn /* reg1 */;
1911         __le32 snd_max_psn /* reg2 */;
1912         __le32 orq_prod /* reg3 */;
1913         __le32 reg4 /* reg4 */;
1914         __le32 reg5 /* reg5 */;
1915         __le32 reg6 /* reg6 */;
1916         __le32 reg7 /* reg7 */;
1917         __le32 reg8 /* reg8 */;
1918         u8 orq_cache_idx /* byte3 */;
1919         u8 byte4 /* byte4 */;
1920         u8 byte5 /* byte5 */;
1921         u8 e4_reserved8 /* byte6 */;
1922         __le16 snd_sq_cons /* word1 */;
1923         __le16 word2 /* conn_dpi */;
1924         __le32 reg9 /* reg9 */;
1925         __le16 word3 /* word3 */;
1926         __le16 e4_reserved9 /* word4 */;
1927 };
1928
1929
1930 struct e5_tstorm_roce_resp_conn_ag_ctx
1931 {
1932         u8 byte0 /* cdu_validation */;
1933         u8 state_and_core_id /* state_and_core_id */;
1934         u8 flags0;
1935 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
1936 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
1937 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK                0x1 /* exist_in_qm1 */
1938 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT               1
1939 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK                0x1 /* bit2 */
1940 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT               2
1941 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK                0x1 /* bit3 */
1942 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT               3
1943 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK        0x1 /* bit4 */
1944 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT       4
1945 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK                0x1 /* bit5 */
1946 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT               5
1947 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK                 0x3 /* timer0cf */
1948 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT                6
1949         u8 flags1;
1950 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK         0x3 /* timer1cf */
1951 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT        0
1952 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK         0x3 /* timer2cf */
1953 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT        2
1954 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK                 0x3 /* timer_stop_all */
1955 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT                4
1956 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK         0x3 /* cf4 */
1957 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT        6
1958         u8 flags2;
1959 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK     0x3 /* cf5 */
1960 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT    0
1961 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK                 0x3 /* cf6 */
1962 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT                2
1963 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK                 0x3 /* cf7 */
1964 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT                4
1965 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK                 0x3 /* cf8 */
1966 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT                6
1967         u8 flags3;
1968 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK                 0x3 /* cf9 */
1969 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT                0
1970 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK                0x3 /* cf10 */
1971 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT               2
1972 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK               0x1 /* cf0en */
1973 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT              4
1974 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK      0x1 /* cf1en */
1975 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT     5
1976 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK      0x1 /* cf2en */
1977 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT     6
1978 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK               0x1 /* cf3en */
1979 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT              7
1980         u8 flags4;
1981 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK      0x1 /* cf4en */
1982 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT     0
1983 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK  0x1 /* cf5en */
1984 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1
1985 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK               0x1 /* cf6en */
1986 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT              2
1987 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK               0x1 /* cf7en */
1988 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT              3
1989 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK               0x1 /* cf8en */
1990 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT              4
1991 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK               0x1 /* cf9en */
1992 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT              5
1993 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK              0x1 /* cf10en */
1994 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT             6
1995 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK             0x1 /* rule0en */
1996 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT            7
1997         u8 flags5;
1998 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK             0x1 /* rule1en */
1999 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT            0
2000 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK             0x1 /* rule2en */
2001 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT            1
2002 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK             0x1 /* rule3en */
2003 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT            2
2004 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK             0x1 /* rule4en */
2005 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT            3
2006 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK             0x1 /* rule5en */
2007 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT            4
2008 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK          0x1 /* rule6en */
2009 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT         5
2010 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK             0x1 /* rule7en */
2011 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT            6
2012 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK             0x1 /* rule8en */
2013 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT            7
2014         u8 flags6;
2015 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK        0x1 /* bit6 */
2016 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT       0
2017 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK        0x1 /* bit7 */
2018 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT       1
2019 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK        0x1 /* bit8 */
2020 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT       2
2021 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK        0x3 /* cf11 */
2022 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT       3
2023 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK        0x1 /* cf11en */
2024 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT       5
2025 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK        0x1 /* rule9en */
2026 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT       6
2027 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_MASK        0x1 /* rule10en */
2028 #define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_SHIFT       7
2029         u8 tx_async_error_type /* byte2 */;
2030         __le16 rq_cons /* word0 */;
2031         __le32 psn_and_rxmit_id_echo /* reg0 */;
2032         __le32 reg1 /* reg1 */;
2033         __le32 reg2 /* reg2 */;
2034         __le32 reg3 /* reg3 */;
2035         __le32 reg4 /* reg4 */;
2036         __le32 reg5 /* reg5 */;
2037         __le32 reg6 /* reg6 */;
2038         __le32 reg7 /* reg7 */;
2039         __le32 reg8 /* reg8 */;
2040         u8 byte3 /* byte3 */;
2041         u8 byte4 /* byte4 */;
2042         u8 byte5 /* byte5 */;
2043         u8 e4_reserved8 /* byte6 */;
2044         __le16 rq_prod /* word1 */;
2045         __le16 conn_dpi /* conn_dpi */;
2046         __le32 num_invlidated_mw /* reg9 */;
2047         __le16 irq_cons /* word3 */;
2048         __le16 e4_reserved9 /* word4 */;
2049 };
2050
2051
2052 struct e5_ustorm_roce_req_conn_ag_ctx
2053 {
2054         u8 byte0 /* cdu_validation */;
2055         u8 byte1 /* state_and_core_id */;
2056         u8 flags0;
2057 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK          0x1 /* exist_in_qm0 */
2058 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT         0
2059 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK          0x1 /* exist_in_qm1 */
2060 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT         1
2061 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK           0x3 /* timer0cf */
2062 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT          2
2063 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK           0x3 /* timer1cf */
2064 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT          4
2065 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK           0x3 /* timer2cf */
2066 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT          6
2067         u8 flags1;
2068 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK           0x3 /* timer_stop_all */
2069 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT          0
2070 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK           0x3 /* cf4 */
2071 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT          2
2072 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK           0x3 /* cf5 */
2073 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT          4
2074 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK           0x3 /* cf6 */
2075 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT          6
2076         u8 flags2;
2077 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK         0x1 /* cf0en */
2078 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT        0
2079 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK         0x1 /* cf1en */
2080 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT        1
2081 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK         0x1 /* cf2en */
2082 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT        2
2083 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK         0x1 /* cf3en */
2084 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT        3
2085 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK         0x1 /* cf4en */
2086 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT        4
2087 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK         0x1 /* cf5en */
2088 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT        5
2089 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK         0x1 /* cf6en */
2090 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT        6
2091 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK       0x1 /* rule0en */
2092 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT      7
2093         u8 flags3;
2094 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK       0x1 /* rule1en */
2095 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT      0
2096 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK       0x1 /* rule2en */
2097 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT      1
2098 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK       0x1 /* rule3en */
2099 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT      2
2100 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK       0x1 /* rule4en */
2101 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT      3
2102 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK       0x1 /* rule5en */
2103 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT      4
2104 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK       0x1 /* rule6en */
2105 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT      5
2106 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK       0x1 /* rule7en */
2107 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT      6
2108 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK       0x1 /* rule8en */
2109 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT      7
2110         u8 flags4;
2111 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK  0x1 /* bit2 */
2112 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
2113 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK  0x1 /* bit3 */
2114 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
2115 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK  0x3 /* cf7 */
2116 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
2117 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK  0x3 /* cf8 */
2118 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
2119 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK  0x1 /* cf7en */
2120 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
2121 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK  0x1 /* cf8en */
2122 #define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
2123         u8 byte2 /* byte2 */;
2124         __le16 word0 /* conn_dpi */;
2125         __le16 word1 /* word1 */;
2126         __le32 reg0 /* reg0 */;
2127         __le32 reg1 /* reg1 */;
2128         __le32 reg2 /* reg2 */;
2129         __le32 reg3 /* reg3 */;
2130         __le16 word2 /* word2 */;
2131         __le16 word3 /* word3 */;
2132 };
2133
2134
2135 struct e5_ustorm_roce_resp_conn_ag_ctx
2136 {
2137         u8 byte0 /* cdu_validation */;
2138         u8 byte1 /* state_and_core_id */;
2139         u8 flags0;
2140 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK          0x1 /* exist_in_qm0 */
2141 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT         0
2142 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK          0x1 /* exist_in_qm1 */
2143 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT         1
2144 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK           0x3 /* timer0cf */
2145 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT          2
2146 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK           0x3 /* timer1cf */
2147 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT          4
2148 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK           0x3 /* timer2cf */
2149 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT          6
2150         u8 flags1;
2151 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK           0x3 /* timer_stop_all */
2152 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT          0
2153 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK           0x3 /* cf4 */
2154 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT          2
2155 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK           0x3 /* cf5 */
2156 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT          4
2157 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK           0x3 /* cf6 */
2158 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT          6
2159         u8 flags2;
2160 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK         0x1 /* cf0en */
2161 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT        0
2162 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK         0x1 /* cf1en */
2163 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT        1
2164 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK         0x1 /* cf2en */
2165 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT        2
2166 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK         0x1 /* cf3en */
2167 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT        3
2168 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK         0x1 /* cf4en */
2169 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT        4
2170 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK         0x1 /* cf5en */
2171 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT        5
2172 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK         0x1 /* cf6en */
2173 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT        6
2174 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK       0x1 /* rule0en */
2175 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT      7
2176         u8 flags3;
2177 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK       0x1 /* rule1en */
2178 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT      0
2179 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK       0x1 /* rule2en */
2180 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT      1
2181 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK       0x1 /* rule3en */
2182 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT      2
2183 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK       0x1 /* rule4en */
2184 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT      3
2185 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK       0x1 /* rule5en */
2186 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT      4
2187 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK       0x1 /* rule6en */
2188 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT      5
2189 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK       0x1 /* rule7en */
2190 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT      6
2191 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK       0x1 /* rule8en */
2192 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT      7
2193         u8 flags4;
2194 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK  0x1 /* bit2 */
2195 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0
2196 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK  0x1 /* bit3 */
2197 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1
2198 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK  0x3 /* cf7 */
2199 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2
2200 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK  0x3 /* cf8 */
2201 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4
2202 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK  0x1 /* cf7en */
2203 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6
2204 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK  0x1 /* cf8en */
2205 #define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7
2206         u8 byte2 /* byte2 */;
2207         __le16 word0 /* conn_dpi */;
2208         __le16 word1 /* word1 */;
2209         __le32 reg0 /* reg0 */;
2210         __le32 reg1 /* reg1 */;
2211         __le32 reg2 /* reg2 */;
2212         __le32 reg3 /* reg3 */;
2213         __le16 word2 /* word2 */;
2214         __le16 word3 /* word3 */;
2215 };
2216
2217
2218 struct e5_xstorm_roce_req_conn_ag_ctx
2219 {
2220         u8 reserved0 /* cdu_validation */;
2221         u8 state_and_core_id /* state_and_core_id */;
2222         u8 flags0;
2223 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
2224 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT       0
2225 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK           0x1 /* exist_in_qm1 */
2226 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT          1
2227 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK           0x1 /* exist_in_qm2 */
2228 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT          2
2229 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK        0x1 /* exist_in_qm3 */
2230 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT       3
2231 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK           0x1 /* bit4 */
2232 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT          4
2233 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK           0x1 /* cf_array_active */
2234 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT          5
2235 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK           0x1 /* bit6 */
2236 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT          6
2237 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK           0x1 /* bit7 */
2238 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT          7
2239         u8 flags1;
2240 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK           0x1 /* bit8 */
2241 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT          0
2242 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK           0x1 /* bit9 */
2243 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT          1
2244 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK               0x1 /* bit10 */
2245 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT              2
2246 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK               0x1 /* bit11 */
2247 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT              3
2248 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK               0x1 /* bit12 */
2249 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT              4
2250 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK               0x1 /* bit13 */
2251 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT              5
2252 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK         0x1 /* bit14 */
2253 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT        6
2254 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK        0x1 /* bit15 */
2255 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT       7
2256         u8 flags2;
2257 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK                 0x3 /* timer0cf */
2258 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT                0
2259 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK                 0x3 /* timer1cf */
2260 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT                2
2261 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK                 0x3 /* timer2cf */
2262 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT                4
2263 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK                 0x3 /* timer_stop_all */
2264 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT                6
2265         u8 flags3;
2266 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK         0x3 /* cf4 */
2267 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT        0
2268 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK         0x3 /* cf5 */
2269 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT        2
2270 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK        0x3 /* cf6 */
2271 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT       4
2272 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK         0x3 /* cf7 */
2273 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT        6
2274         u8 flags4;
2275 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK                 0x3 /* cf8 */
2276 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT                0
2277 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK                 0x3 /* cf9 */
2278 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT                2
2279 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK                0x3 /* cf10 */
2280 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT               4
2281 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK                0x3 /* cf11 */
2282 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT               6
2283         u8 flags5;
2284 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK                0x3 /* cf12 */
2285 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT               0
2286 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK                0x3 /* cf13 */
2287 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT               2
2288 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK        0x3 /* cf14 */
2289 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT       4
2290 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK                0x3 /* cf15 */
2291 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT               6
2292         u8 flags6;
2293 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK                0x3 /* cf16 */
2294 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT               0
2295 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK                0x3 /* cf_array_cf */
2296 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT               2
2297 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK                0x3 /* cf18 */
2298 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT               4
2299 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK                0x3 /* cf19 */
2300 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT               6
2301         u8 flags7;
2302 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK                0x3 /* cf20 */
2303 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT               0
2304 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK                0x3 /* cf21 */
2305 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT               2
2306 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK           0x3 /* cf22 */
2307 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT          4
2308 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK               0x1 /* cf0en */
2309 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT              6
2310 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK               0x1 /* cf1en */
2311 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT              7
2312         u8 flags8;
2313 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK               0x1 /* cf2en */
2314 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT              0
2315 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK               0x1 /* cf3en */
2316 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT              1
2317 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK      0x1 /* cf4en */
2318 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT     2
2319 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK      0x1 /* cf5en */
2320 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT     3
2321 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK     0x1 /* cf6en */
2322 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT    4
2323 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK      0x1 /* cf7en */
2324 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT     5
2325 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK               0x1 /* cf8en */
2326 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT              6
2327 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK               0x1 /* cf9en */
2328 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT              7
2329         u8 flags9;
2330 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK              0x1 /* cf10en */
2331 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT             0
2332 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK              0x1 /* cf11en */
2333 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT             1
2334 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK              0x1 /* cf12en */
2335 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT             2
2336 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK              0x1 /* cf13en */
2337 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT             3
2338 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK     0x1 /* cf14en */
2339 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT    4
2340 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK              0x1 /* cf15en */
2341 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT             5
2342 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK              0x1 /* cf16en */
2343 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT             6
2344 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK              0x1 /* cf_array_cf_en */
2345 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT             7
2346         u8 flags10;
2347 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK              0x1 /* cf18en */
2348 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT             0
2349 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK              0x1 /* cf19en */
2350 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT             1
2351 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK              0x1 /* cf20en */
2352 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT             2
2353 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK              0x1 /* cf21en */
2354 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT             3
2355 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK        0x1 /* cf22en */
2356 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT       4
2357 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK              0x1 /* cf23en */
2358 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT             5
2359 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK             0x1 /* rule0en */
2360 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT            6
2361 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK             0x1 /* rule1en */
2362 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT            7
2363         u8 flags11;
2364 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK             0x1 /* rule2en */
2365 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT            0
2366 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK             0x1 /* rule3en */
2367 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT            1
2368 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK             0x1 /* rule4en */
2369 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT            2
2370 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK             0x1 /* rule5en */
2371 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT            3
2372 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK             0x1 /* rule6en */
2373 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT            4
2374 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK  0x1 /* rule7en */
2375 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
2376 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK        0x1 /* rule8en */
2377 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT       6
2378 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK             0x1 /* rule9en */
2379 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT            7
2380         u8 flags12;
2381 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK          0x1 /* rule10en */
2382 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT         0
2383 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK            0x1 /* rule11en */
2384 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT           1
2385 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK        0x1 /* rule12en */
2386 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT       2
2387 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK        0x1 /* rule13en */
2388 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT       3
2389 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK   0x1 /* rule14en */
2390 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT  4
2391 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK            0x1 /* rule15en */
2392 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT           5
2393 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK   0x1 /* rule16en */
2394 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT  6
2395 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK     0x1 /* rule17en */
2396 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT    7
2397         u8 flags13;
2398 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK            0x1 /* rule18en */
2399 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT           0
2400 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK            0x1 /* rule19en */
2401 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT           1
2402 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK        0x1 /* rule20en */
2403 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT       2
2404 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK        0x1 /* rule21en */
2405 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT       3
2406 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK        0x1 /* rule22en */
2407 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT       4
2408 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK        0x1 /* rule23en */
2409 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT       5
2410 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK        0x1 /* rule24en */
2411 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT       6
2412 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK        0x1 /* rule25en */
2413 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT       7
2414         u8 flags14;
2415 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK      0x1 /* bit16 */
2416 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT     0
2417 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK               0x1 /* bit17 */
2418 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT              1
2419 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK        0x3 /* bit18 */
2420 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT       2
2421 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK            0x1 /* bit20 */
2422 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT           4
2423 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK    0x1 /* bit21 */
2424 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT   5
2425 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK                0x3 /* cf23 */
2426 #define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT               6
2427         u8 byte2 /* byte2 */;
2428         __le16 physical_q0 /* physical_q0 */;
2429         __le16 word1 /* physical_q1 */;
2430         __le16 sq_cmp_cons /* physical_q2 */;
2431         __le16 sq_cons /* word3 */;
2432         __le16 sq_prod /* word4 */;
2433         __le16 word5 /* word5 */;
2434         __le16 conn_dpi /* conn_dpi */;
2435         u8 byte3 /* byte3 */;
2436         u8 byte4 /* byte4 */;
2437         u8 byte5 /* byte5 */;
2438         u8 byte6 /* byte6 */;
2439         __le32 lsn /* reg0 */;
2440         __le32 ssn /* reg1 */;
2441         __le32 snd_una_psn /* reg2 */;
2442         __le32 snd_nxt_psn /* reg3 */;
2443         __le32 reg4 /* reg4 */;
2444         __le32 orq_cons_th /* cf_array0 */;
2445         __le32 orq_cons /* cf_array1 */;
2446 };
2447
2448
2449 struct e5_xstorm_roce_resp_conn_ag_ctx
2450 {
2451         u8 reserved0 /* cdu_validation */;
2452         u8 state_and_core_id /* state_and_core_id */;
2453         u8 flags0;
2454 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1 /* exist_in_qm0 */
2455 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
2456 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK         0x1 /* exist_in_qm1 */
2457 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT        1
2458 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK         0x1 /* exist_in_qm2 */
2459 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT        2
2460 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1 /* exist_in_qm3 */
2461 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
2462 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK         0x1 /* bit4 */
2463 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT        4
2464 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK         0x1 /* cf_array_active */
2465 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT        5
2466 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK         0x1 /* bit6 */
2467 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT        6
2468 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK         0x1 /* bit7 */
2469 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT        7
2470         u8 flags1;
2471 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK         0x1 /* bit8 */
2472 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT        0
2473 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK         0x1 /* bit9 */
2474 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT        1
2475 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK             0x1 /* bit10 */
2476 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT            2
2477 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK             0x1 /* bit11 */
2478 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT            3
2479 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK             0x1 /* bit12 */
2480 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT            4
2481 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK             0x1 /* bit13 */
2482 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT            5
2483 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK       0x1 /* bit14 */
2484 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT      6
2485 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1 /* bit15 */
2486 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
2487         u8 flags2;
2488 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK               0x3 /* timer0cf */
2489 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT              0
2490 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK               0x3 /* timer1cf */
2491 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT              2
2492 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK               0x3 /* timer2cf */
2493 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT              4
2494 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK               0x3 /* timer_stop_all */
2495 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT              6
2496         u8 flags3;
2497 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK          0x3 /* cf4 */
2498 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT         0
2499 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK       0x3 /* cf5 */
2500 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT      2
2501 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK      0x3 /* cf6 */
2502 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT     4
2503 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3 /* cf7 */
2504 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
2505         u8 flags4;
2506 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK               0x3 /* cf8 */
2507 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT              0
2508 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK               0x3 /* cf9 */
2509 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT              2
2510 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK              0x3 /* cf10 */
2511 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT             4
2512 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK              0x3 /* cf11 */
2513 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT             6
2514         u8 flags5;
2515 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK              0x3 /* cf12 */
2516 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT             0
2517 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK              0x3 /* cf13 */
2518 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT             2
2519 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK              0x3 /* cf14 */
2520 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT             4
2521 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK              0x3 /* cf15 */
2522 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT             6
2523         u8 flags6;
2524 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK              0x3 /* cf16 */
2525 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT             0
2526 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK              0x3 /* cf_array_cf */
2527 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT             2
2528 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK              0x3 /* cf18 */
2529 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT             4
2530 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK              0x3 /* cf19 */
2531 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT             6
2532         u8 flags7;
2533 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK              0x3 /* cf20 */
2534 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT             0
2535 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK              0x3 /* cf21 */
2536 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT             2
2537 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK         0x3 /* cf22 */
2538 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT        4
2539 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK             0x1 /* cf0en */
2540 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT            6
2541 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK             0x1 /* cf1en */
2542 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT            7
2543         u8 flags8;
2544 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK             0x1 /* cf2en */
2545 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT            0
2546 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK             0x1 /* cf3en */
2547 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT            1
2548 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK       0x1 /* cf4en */
2549 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT      2
2550 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK    0x1 /* cf5en */
2551 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT   3
2552 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK   0x1 /* cf6en */
2553 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT  4
2554 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1 /* cf7en */
2555 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
2556 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK             0x1 /* cf8en */
2557 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT            6
2558 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK             0x1 /* cf9en */
2559 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT            7
2560         u8 flags9;
2561 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK            0x1 /* cf10en */
2562 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT           0
2563 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK            0x1 /* cf11en */
2564 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT           1
2565 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK            0x1 /* cf12en */
2566 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT           2
2567 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK            0x1 /* cf13en */
2568 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT           3
2569 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK            0x1 /* cf14en */
2570 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT           4
2571 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK            0x1 /* cf15en */
2572 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT           5
2573 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK            0x1 /* cf16en */
2574 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT           6
2575 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK            0x1 /* cf_array_cf_en */
2576 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT           7
2577         u8 flags10;
2578 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK            0x1 /* cf18en */
2579 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT           0
2580 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK            0x1 /* cf19en */
2581 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT           1
2582 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK            0x1 /* cf20en */
2583 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT           2
2584 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK            0x1 /* cf21en */
2585 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT           3
2586 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1 /* cf22en */
2587 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
2588 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK            0x1 /* cf23en */
2589 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT           5
2590 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK           0x1 /* rule0en */
2591 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT          6
2592 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK           0x1 /* rule1en */
2593 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT          7
2594         u8 flags11;
2595 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK           0x1 /* rule2en */
2596 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT          0
2597 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK           0x1 /* rule3en */
2598 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT          1
2599 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK           0x1 /* rule4en */
2600 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT          2
2601 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK           0x1 /* rule5en */
2602 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT          3
2603 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK           0x1 /* rule6en */
2604 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT          4
2605 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK           0x1 /* rule7en */
2606 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT          5
2607 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK      0x1 /* rule8en */
2608 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
2609 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK           0x1 /* rule9en */
2610 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT          7
2611         u8 flags12;
2612 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK          0x1 /* rule10en */
2613 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT         0
2614 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK  0x1 /* rule11en */
2615 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1
2616 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK      0x1 /* rule12en */
2617 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
2618 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK      0x1 /* rule13en */
2619 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
2620 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK          0x1 /* rule14en */
2621 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT         4
2622 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK          0x1 /* rule15en */
2623 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT         5
2624 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK          0x1 /* rule16en */
2625 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT         6
2626 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK          0x1 /* rule17en */
2627 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT         7
2628         u8 flags13;
2629 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK          0x1 /* rule18en */
2630 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT         0
2631 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK          0x1 /* rule19en */
2632 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT         1
2633 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK      0x1 /* rule20en */
2634 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
2635 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK      0x1 /* rule21en */
2636 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
2637 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK      0x1 /* rule22en */
2638 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
2639 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK      0x1 /* rule23en */
2640 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
2641 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK      0x1 /* rule24en */
2642 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
2643 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK      0x1 /* rule25en */
2644 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
2645         u8 flags14;
2646 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK             0x1 /* bit16 */
2647 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT            0
2648 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK             0x1 /* bit17 */
2649 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT            1
2650 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK             0x1 /* bit18 */
2651 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT            2
2652 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK             0x1 /* bit19 */
2653 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT            3
2654 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK             0x1 /* bit20 */
2655 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT            4
2656 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK             0x1 /* bit21 */
2657 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT            5
2658 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK              0x3 /* cf23 */
2659 #define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT             6
2660         u8 byte2 /* byte2 */;
2661         __le16 physical_q0 /* physical_q0 */;
2662         __le16 word1 /* physical_q1 */;
2663         __le16 irq_prod /* physical_q2 */;
2664         __le16 word3 /* word3 */;
2665         __le16 word4 /* word4 */;
2666         __le16 ack_cons /* word5 */;
2667         __le16 irq_cons /* conn_dpi */;
2668         u8 rxmit_opcode /* byte3 */;
2669         u8 byte4 /* byte4 */;
2670         u8 byte5 /* byte5 */;
2671         u8 byte6 /* byte6 */;
2672         __le32 rxmit_psn_and_id /* reg0 */;
2673         __le32 rxmit_bytes_length /* reg1 */;
2674         __le32 psn /* reg2 */;
2675         __le32 reg3 /* reg3 */;
2676         __le32 reg4 /* reg4 */;
2677         __le32 reg5 /* cf_array0 */;
2678         __le32 msn_and_syndrome /* cf_array1 */;
2679 };
2680
2681
2682 struct e5_ystorm_roce_req_conn_ag_ctx
2683 {
2684         u8 byte0 /* cdu_validation */;
2685         u8 byte1 /* state_and_core_id */;
2686         u8 flags0;
2687 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
2688 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT    0
2689 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
2690 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT    1
2691 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
2692 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT     2
2693 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
2694 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT     4
2695 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
2696 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT     6
2697         u8 flags1;
2698 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
2699 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT   0
2700 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
2701 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT   1
2702 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
2703 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT   2
2704 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
2705 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
2706 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
2707 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
2708 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
2709 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
2710 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
2711 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
2712 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
2713 #define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
2714         u8 byte2 /* byte2 */;
2715         u8 byte3 /* byte3 */;
2716         __le16 word0 /* word0 */;
2717         __le32 reg0 /* reg0 */;
2718         __le32 reg1 /* reg1 */;
2719         __le16 word1 /* word1 */;
2720         __le16 word2 /* word2 */;
2721         __le16 word3 /* word3 */;
2722         __le16 word4 /* word4 */;
2723         __le32 reg2 /* reg2 */;
2724         __le32 reg3 /* reg3 */;
2725 };
2726
2727
2728 struct e5_ystorm_roce_resp_conn_ag_ctx
2729 {
2730         u8 byte0 /* cdu_validation */;
2731         u8 byte1 /* state_and_core_id */;
2732         u8 flags0;
2733 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK     0x1 /* exist_in_qm0 */
2734 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT    0
2735 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK     0x1 /* exist_in_qm1 */
2736 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT    1
2737 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK      0x3 /* cf0 */
2738 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT     2
2739 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK      0x3 /* cf1 */
2740 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT     4
2741 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK      0x3 /* cf2 */
2742 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT     6
2743         u8 flags1;
2744 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK    0x1 /* cf0en */
2745 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT   0
2746 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK    0x1 /* cf1en */
2747 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT   1
2748 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK    0x1 /* cf2en */
2749 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT   2
2750 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK  0x1 /* rule0en */
2751 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
2752 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK  0x1 /* rule1en */
2753 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
2754 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK  0x1 /* rule2en */
2755 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
2756 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK  0x1 /* rule3en */
2757 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
2758 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK  0x1 /* rule4en */
2759 #define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
2760         u8 byte2 /* byte2 */;
2761         u8 byte3 /* byte3 */;
2762         __le16 word0 /* word0 */;
2763         __le32 reg0 /* reg0 */;
2764         __le32 reg1 /* reg1 */;
2765         __le16 word1 /* word1 */;
2766         __le16 word2 /* word2 */;
2767         __le16 word3 /* word3 */;
2768         __le16 word4 /* word4 */;
2769         __le32 reg2 /* reg2 */;
2770         __le32 reg3 /* reg3 */;
2771 };
2772
2773
2774 /*
2775  * Roce doorbell data
2776  */
2777 enum roce_flavor
2778 {
2779         PLAIN_ROCE /* RoCE v1 */,
2780         RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */,
2781         RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */,
2782         MAX_ROCE_FLAVOR
2783 };
2784
2785 #endif /* __ECORE_HSI_ROCE__ */