usr/src/uts/common/sys/sata/sata_defs.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
  24  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
  25  */
  26
  27 #ifndef _SATA_DEFS_H
  28 #define _SATA_DEFS_H
  29
  30 #ifdef  __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 #include <sys/scsi/generic/mode.h>
  35
  36 /*
  37  * Common ATA commands (subset)
  38  */
  39 #define SATAC_DIAG              0x90    /* diagnose command */
  40 #define SATAC_RECAL             0x10    /* restore cmd, 4 bits step rate */
  41 #define SATAC_FORMAT            0x50    /* format track command */
  42 #define SATAC_SET_FEATURES      0xef    /* set features */
  43 #define SATAC_IDLE_IM           0xe1    /* idle immediate */
  44 #define SATAC_STANDBY_IM        0xe0    /* standby immediate */
  45 #define SATAC_DOOR_LOCK         0xde    /* door lock */
  46 #define SATAC_DOOR_UNLOCK       0xdf    /* door unlock */
  47 #define SATAC_IDLE              0xe3    /* idle */
  48 #define SATAC_STANDBY           0xe2    /* standby */
  49
  50 /*
  51  * ATA/ATAPI disk commands (subset)
  52  */
  53 #define SATAC_DSM               0x06    /* Data Set Management */
  54 #define SATAC_DEVICE_RESET      0x08    /* ATAPI device reset */
  55 #define SATAC_DOWNLOAD_MICROCODE 0x92   /* Download microcode */
  56 #define SATAC_EJECT             0xed    /* media eject */
  57 #define SATAC_FLUSH_CACHE       0xe7    /* flush write-cache */
  58 #define SATAC_ID_DEVICE         0xec    /* IDENTIFY DEVICE */
  59 #define SATAC_ID_PACKET_DEVICE  0xa1    /* ATAPI identify packet device */
  60 #define SATAC_INIT_DEVPARMS     0x91    /* initialize device parameters */
  61 #define SATAC_PACKET            0xa0    /* ATAPI packet */
  62 #define SATAC_RDMULT            0xc4    /* read multiple w/DMA */
  63 #define SATAC_RDSEC             0x20    /* read sector */
  64 #define SATAC_RDVER             0x40    /* read verify */
  65 #define SATAC_READ_DMA          0xc8    /* read DMA */
  66 #define SATAC_SEEK              0x70    /* seek */
  67 #define SATAC_SERVICE           0xa2    /* queued/overlap service */
  68 #define SATAC_SETMULT           0xc6    /* set multiple mode */
  69 #define SATAC_WRITE_DMA         0xca    /* write (multiple) w/DMA */
  70 #define SATAC_WRMULT            0xc5    /* write multiple */
  71 #define SATAC_WRSEC             0x30    /* write sector */
  72 #define SATAC_RDSEC_EXT         0x24    /* read sector extended (LBA48) */
  73 #define SATAC_READ_DMA_EXT      0x25    /* read DMA extended (LBA48) */
  74 #define SATAC_RDMULT_EXT        0x29    /* read multiple extended (LBA48) */
  75 #define SATAC_WRSEC_EXT         0x34    /* read sector extended (LBA48) */
  76 #define SATAC_WRITE_DMA_EXT     0x35    /* read DMA extended (LBA48) */
  77 #define SATAC_WRMULT_EXT        0x39    /* read multiple extended (LBA48) */
  78
  79 #define SATAC_READ_DMA_QUEUED   0xc7    /* read DMA / may be queued */
  80 #define SATAC_READ_DMA_QUEUED_EXT 0x26  /* read DMA ext / may be queued */
  81 #define SATAC_WRITE_DMA_QUEUED  0xcc    /* read DMA / may be queued */
  82 #define SATAC_WRITE_DMA_QUEUED_EXT 0x36 /* read DMA ext / may be queued */
  83 #define SATAC_READ_PM_REG       0xe4    /* read port mult reg */
  84 #define SATAC_WRITE_PM_REG      0xe8    /* write port mult reg */
  85
  86 #define SATAC_READ_FPDMA_QUEUED 0x60    /* First-Party-DMA read queued */
  87 #define SATAC_WRITE_FPDMA_QUEUED 0x61   /* First-Party-DMA write queued */
  88
  89 #define SATAC_READ_LOG_EXT      0x2f    /* read log */
  90
  91 #define SATAC_SMART             0xb0    /* SMART */
  92
  93 #define SATA_LOG_PAGE_10        0x10    /* log page 0x10 - SATA error */
  94 /*
  95  * Port Multiplier Commands
  96  */
  97 #define SATAC_READ_PORTMULT     0xe4    /* read port multiplier */
  98 #define SATAC_WRITE_PORTMULT    0xe8    /* write port multiplier */
  99
 100 /*
 101  * Power Managment Commands (subset)
 102  */
 103 #define SATAC_CHECK_POWER_MODE  0xe5    /* check power mode */
 104
 105 #define SATA_PWRMODE_STANDBY            0       /* standby mode */
 106 #define SATA_PWRMODE_IDLE               0x80    /* idle mode */
 107 #define SATA_PWRMODE_ACTIVE_SPINDOWN    0x40    /* PM0 and spinning down */
 108 #define SATA_PWRMODE_ACTIVE_SPINUP      0x41    /* PM0 and spinning up */
 109 #define SATA_PWRMODE_ACTIVE             0xFF    /* active or idle mode */
 110
 111
 112 /*
 113  * SMART FEATURES Subcommands
 114  */
 115 #define SATA_SMART_READ_DATA            0xd0
 116 #define SATA_SMART_ATTR_AUTOSAVE        0xd2
 117 #define SATA_SMART_EXECUTE_OFFLINE_IMM  0xd4
 118 #define SATA_SMART_READ_LOG             0xd5
 119 #define SATA_SMART_WRITE_LOG            0xd6
 120 #define SATA_SMART_ENABLE_OPS           0xd8
 121 #define SATA_SMART_DISABLE_OPS          0xd9
 122 #define SATA_SMART_RETURN_STATUS        0xda
 123
 124 /*
 125  * SET FEATURES Subcommands
 126  */
 127 #define SATAC_SF_ENABLE_WRITE_CACHE     0x02
 128 #define SATAC_SF_TRANSFER_MODE          0x03
 129 #define SATAC_SF_DISABLE_RMSN           0x31
 130 #define SATAC_SF_ENABLE_ACOUSTIC        0x42
 131 #define SATAC_SF_DISABLE_READ_AHEAD     0x55
 132 #define SATAC_SF_DISABLE_WRITE_CACHE    0x82
 133 #define SATAC_SF_ENABLE_READ_AHEAD      0xaa
 134 #define SATAC_SF_DISABLE_ACOUSTIC       0xc2
 135 #define SATAC_SF_ENABLE_RMSN            0x95
 136
 137 /*
 138  * SET FEATURES transfer mode values
 139  */
 140 #define SATAC_TRANSFER_MODE_PIO_DEFAULT         0x00
 141 #define SATAC_TRANSFER_MODE_PIO_DISABLE_IODRY   0x01
 142 #define SATAC_TRANSFER_MODE_PIO_FLOW_CONTROL    0x08
 143 #define SATAC_TRANSFER_MODE_MULTI_WORD_DMA      0x20
 144 #define SATAC_TRANSFER_MODE_ULTRA_DMA           0x40
 145
 146 /*
 147  * Download microcode subcommands
 148  */
 149 #define SATA_DOWNLOAD_MCODE_TEMP        1       /* Revert on/ reset/pwr cycle */
 150 #define SATA_DOWNLOAD_MCODE_SAVE        7       /* No offset, keep mcode */
 151
 152
 153 /* Generic ATA definitions */
 154
 155 #define SATA_TAG_QUEUING_SHIFT 3
 156 #define SATA_TAG_QUEUING_MASK 0x1f
 157 /*
 158  * Identify Device data
 159  * Although both ATA and ATAPI devices' Identify Data have the same length,
 160  * some words have different meaning/content and/or are irrelevant for
 161  * other type of device.
 162  * Following is the ATA Device Identify data layout
 163  */
 164 typedef struct sata_id {
 165 /*                                      WORD                              */
 166 /*                                      OFFSET COMMENT                    */
 167         ushort_t  ai_config;       /*   0  general configuration bits     */
 168         ushort_t  ai_fixcyls;      /*   1  # of cylinders (obsolete)      */
 169         ushort_t  ai_resv0;        /*   2  # reserved                     */
 170         ushort_t  ai_heads;        /*   3  # of heads (obsolete)          */
 171         ushort_t  ai_trksiz;       /*   4  # of bytes/track (retired)     */
 172         ushort_t  ai_secsiz;       /*   5  # of bytes/sector (retired)    */
 173         ushort_t  ai_sectors;      /*   6  # of sectors/track (obsolete)  */
 174         ushort_t  ai_resv1[3];     /*   7  "Vendor Unique"                */
 175         char    ai_drvser[20];     /*  10  Serial number                  */
 176         ushort_t ai_buftype;       /*  20  Buffer type                    */
 177         ushort_t ai_bufsz;         /*  21  Buffer size in 512 byte incr   */
 178         ushort_t ai_ecc;           /*  22  # of ecc bytes avail on rd/wr  */
 179         char    ai_fw[8];          /*  23  Firmware revision              */
 180         char    ai_model[40];      /*  27  Model #                        */
 181         ushort_t ai_mult1;         /*  47  Multiple command flags         */
 182         ushort_t ai_dwcap;         /*  48  Doubleword capabilities        */
 183         ushort_t ai_cap;           /*  49  Capabilities                   */
 184         ushort_t ai_resv2;         /*  50  Reserved                       */
 185         ushort_t ai_piomode;       /*  51  PIO timing mode                */
 186         ushort_t ai_dmamode;       /*  52  DMA timing mode                */
 187         ushort_t ai_validinfo;     /*  53  bit0: wds 54-58, bit1: 64-70   */
 188         ushort_t ai_curcyls;       /*  54  # of current cylinders         */
 189         ushort_t ai_curheads;      /*  55  # of current heads             */
 190         ushort_t ai_cursectrk;     /*  56  # of current sectors/track     */
 191         ushort_t ai_cursccp[2];    /*  57  current sectors capacity       */
 192         ushort_t ai_mult2;         /*  59  multiple sectors info          */
 193         ushort_t ai_addrsec[2];    /*  60  LBA only: no of addr secs      */
 194         ushort_t ai_dirdma;        /*  62  valid in ATA/ATAPI7, DMADIR    */
 195         ushort_t ai_dworddma;      /*  63  multi word dma modes   */
 196         ushort_t ai_advpiomode;    /*  64  advanced PIO modes supported   */
 197         ushort_t ai_minmwdma;      /*  65  min multi-word dma cycle info  */
 198         ushort_t ai_recmwdma;      /*  66  rec multi-word dma cycle info  */
 199         ushort_t ai_minpio;        /*  67  min PIO cycle info             */
 200         ushort_t ai_minpioflow;    /*  68  min PIO cycle info w/flow ctl  */
 201         ushort_t ai_addsupported;  /*  69  additional supported           */
 202         ushort_t ai_resv3;         /*  70 reserved                        */
 203         ushort_t ai_typtime[2];    /* 71-72 timing                        */
 204         ushort_t ai_resv4[2];      /* 73-74 reserved                      */
 205         ushort_t ai_qdepth;        /*  75  queue depth                    */
 206         ushort_t ai_satacap;       /*  76  SATA capabilities              */
 207         ushort_t ai_resv5;         /*  77 reserved                        */
 208         ushort_t ai_satafsup;      /*  78 SATA features supported         */
 209         ushort_t ai_satafenbl;     /*  79 SATA features enabled           */
 210         ushort_t ai_majorversion;  /*  80  major versions supported       */
 211         ushort_t ai_minorversion;  /*  81  minor version number supported */
 212         ushort_t ai_cmdset82;      /*  82  command set supported          */
 213         ushort_t ai_cmdset83;      /*  83  more command sets supported    */
 214         ushort_t ai_cmdset84;      /*  84  more command sets supported    */
 215         ushort_t ai_features85;    /*  85 enabled features                */
 216         ushort_t ai_features86;    /*  86 enabled features                */
 217         ushort_t ai_features87;    /*  87 enabled features                */
 218         ushort_t ai_ultradma;      /*  88 Ultra DMA mode                  */
 219         ushort_t ai_erasetime;     /*  89 security erase time             */
 220         ushort_t ai_erasetimex;    /*  90 enhanced security erase time    */
 221         ushort_t ai_adv_pwr_mgmt;  /*  91 advanced power management time  */
 222         ushort_t ai_master_pwd;    /*  92 master password revision code   */
 223         ushort_t ai_hrdwre_reset;  /*  93 hardware reset result           */
 224         ushort_t ai_acoustic;      /*  94 accoustic management values     */
 225         ushort_t ai_stream_min_sz; /*  95 stream minimum request size     */
 226         ushort_t ai_stream_xfer_d; /*  96 streaming transfer time (DMA)   */
 227         ushort_t ai_stream_lat;    /*  97 streaming access latency        */
 228         ushort_t ai_streamperf[2]; /* 98-99 streaming performance gran.   */
 229         ushort_t ai_addrsecxt[4];  /* 100 extended max LBA sector         */
 230         ushort_t ai_stream_xfer_p; /* 104 streaming transfer time (PIO)   */
 231         ushort_t ai_maxcount;      /* 105 max count of 512-byte blocks of */
 232                                     /* LBA range entries                  */
 233         ushort_t ai_phys_sect_sz;  /* 106 physical sector size            */
 234         ushort_t ai_seek_delay;    /* 107 inter-seek delay time (usecs)   */
 235         ushort_t ai_naa_ieee_oui;  /* 108 NAA/IEEE OUI                    */
 236         ushort_t ai_ieee_oui_uid;  /* 109 IEEE OUT/unique id              */
 237         ushort_t ai_uid_mid;       /* 110 unique id (mid)                 */
 238         ushort_t ai_uid_low;       /* 111 unique id (low)                 */
 239         ushort_t ai_resv_wwn[4];   /* 112-115 reserved for WWN ext.       */
 240         ushort_t ai_incits;        /* 116 reserved for INCITS TR-37-2004  */
 241         ushort_t ai_words_lsec[2]; /* 117-118 words per logical sector    */
 242         ushort_t ai_cmdset119;     /* 119 more command sets supported     */
 243         ushort_t ai_features120;   /* 120 enabled features                */
 244         ushort_t ai_padding1[6];   /* pad to 126                          */
 245         ushort_t ai_rmsn;          /* 127 removable media notification    */
 246         ushort_t ai_securestatus;  /* 128 security status                 */
 247         ushort_t ai_vendor[31];    /* 129-159 vendor specific             */
 248         ushort_t ai_padding2[8];   /* 160 pad to 168                      */
 249         ushort_t ai_nomformfactor; /* 168 nominal form factor             */
 250         ushort_t ai_dsm;           /* 169 data set management             */
 251         ushort_t ai_padding3[6];   /* 170 pad to 176                      */
 252         ushort_t ai_curmedser[30]; /* 176-205 current media serial #      */
 253         ushort_t ai_sctsupport;    /* 206 SCT command transport           */
 254         ushort_t ai_padding4[10];  /* 207 pad to 217                      */
 255         ushort_t ai_medrotrate;    /* 217 nominal media rotation rate     */
 256         ushort_t ai_padding5[37];  /* 218 pad to 255                      */
 257         ushort_t ai_integrity;     /* 255 integrity word                  */
 258 } sata_id_t;
 259
 260
 261 /* Identify Device: general config bits  - word 0 */
 262
 263 #define SATA_ATA_TYPE_MASK      0x8001  /* ATA Device type mask */
 264 #define SATA_ATA_TYPE           0x0000  /* ATA device */
 265 #define SATA_REM_MEDIA          0x0080  /* Removable media */
 266 #define SATA_INCOMPLETE_DATA    0x0004  /* Incomplete Identify Device data */
 267 #define SATA_CFA_TYPE           0x848a  /* CFA feature set device */
 268
 269 #define SATA_ID_SERIAL_OFFSET   10
 270 #define SATA_ID_SERIAL_LEN      20
 271 #define SATA_ID_MODEL_OFFSET    27
 272 #define SATA_ID_MODEL_LEN       40
 273 #define SATA_ID_FW_LEN          8
 274 #define SATA_ID_BDC_LEN         0x3c
 275 #define SATA_ID_ATA_INFO_LEN    0x238
 276
 277 /* Identify Device: common capability bits - word 49 */
 278
 279 #define SATA_DMA_SUPPORT        0x0100
 280 #define SATA_LBA_SUPPORT        0x0200
 281 #define SATA_IORDY_DISABLE      0x0400
 282 #define SATA_IORDY_SUPPORT      0x0800
 283 #define SATA_STANDBYTIMER       0x2000
 284
 285 /* Identify Device: ai_validinfo (word 53) */
 286
 287 #define SATA_VALIDINFO_88       0x0004  /* word 88 supported fields valid */
 288 #define SATA_VALIDINFO_70_64    0x0004  /* words 70-64 fields valid */
 289
 290 /* Identify Device: ai_addsupported (word 69) */
 291
 292 #define SATA_DETERMINISTIC_READ 0x4000  /* word 69 deterministic read supp. */
 293 #define SATA_READ_ZERO          0x0020  /* word 69 read zero after TRIM supp. */
 294
 295 /* Identify Device: ai_majorversion (word 80) */
 296
 297 #define SATA_MAJVER_7           0x0080  /* ATA/ATAPI-7 version supported */
 298 #define SATA_MAJVER_654         0x0070  /* ATA/ATAPI-6,5 or 4 ver supported */
 299 #define SATA_MAJVER_6           0x0040  /* ATA/ATAPI-6 version supported */
 300 #define SATA_MAJVER_5           0x0020  /* ATA/ATAPI-7 version supported */
 301 #define SATA_MAJVER_4           0x0010  /* ATA/ATAPI-4 version supported */
 302
 303 /* Identify Device: command set supported/enabled bits - words 83 and 86 */
 304
 305 #define SATA_EXT48              0x0400  /* 48 bit address feature */
 306 #define SATA_PWRUP_IN_STANDBY   0x0020  /* Power-up in standby mode supp/en */
 307 #define SATA_RM_STATUS_NOTIFIC  0x0010  /* Removable Media Stat Notification */
 308 #define SATA_RW_DMA_QUEUED_CMD  0x0002  /* R/W DMA Queued supported */
 309 #define SATA_DWNLOAD_MCODE_CMD  0x0001  /* Download Microcode CMD supp/enbld */
 310 #define SATA_ACOUSTIC_MGMT      0x0200  /* Acoustic Management features */
 311
 312 /* Identify Device: command set supported/enabled bits - words 82 and 85 */
 313
 314 #define SATA_SMART_SUPPORTED    0x0001  /* SMART feature set is supported */
 315 #define SATA_WRITE_CACHE        0x0020  /* Write Cache supported/enabled */
 316 #define SATA_LOOK_AHEAD         0x0040  /* Look Ahead supported/enabled */
 317 #define SATA_DEVICE_RESET_CMD   0x0200  /* Device Reset CMD supported/enbld */
 318 #define SATA_READ_BUFFER_CMD    0x2000  /* Read Buffer CMD supported/enbld */
 319 #define SATA_WRITE_BUFFER_CMD   0x1000  /* Write Buffer CMD supported/enbld */
 320 #define SATA_SMART_ENABLED      0x0001  /* SMART feature set is enabled */
 321
 322 /* Identify Device: command set supported/enabled bits - words 84 & 87 */
 323 #define SATA_SMART_SELF_TEST_SUPPORTED  0x0002  /* SMART self-test supported */
 324 /* IDLE IMMEDIATE with UNLOAD FEATURE supported */
 325 #define SATA_IDLE_UNLOAD_SUPPORTED      0x2000
 326
 327 /* Identify Device: physical sector size - word 106 */
 328 #define SATA_L2PS_CHECK_BIT     0x4000  /* Set when this word valid */
 329 #define SATA_L2PS_HAS_MULT      0x2000  /* Multiple logical sectors per phys */
 330 #define SATA_L2PS_BIG_SECTORS   0x1000  /* Logical sector size > 512 */
 331 #define SATA_L2PS_EXP_MASK      0x000f  /* Logical sectors per phys exponent */
 332
 333 /* Identify (Packet) Device word 63,  ATA/ATAPI-6 & 7 */
 334 #define SATA_MDMA_SEL_MASK      0x0700  /* Multiword DMA selected */
 335 #define SATA_MDMA_2_SEL         0x0400  /* Multiword DMA mode 2 selected */
 336 #define SATA_MDMA_1_SEL         0x0200  /* Multiword DMA mode 1 selected */
 337 #define SATA_MDMA_0_SEL         0x0100  /* Multiword DMA mode 0 selected */
 338 #define SATA_MDMA_2_SUP         0x0004  /* Multiword DMA mode 2 supported */
 339 #define SATA_MDMA_1_SUP         0x0002  /* Multiword DMA mode 1 supported */
 340 #define SATA_MDMA_0_SUP         0x0001  /* Multiword DMA mode 0 supported */
 341 #define SATA_MDMA_SUP_MASK      0x0007  /* Multiword DMA supported */
 342
 343 /* Identify (Packet) Device Word 88 */
 344 #define SATA_UDMA_SUP_MASK              0x007f  /* UDMA modes supported */
 345 #define SATA_UDMA_SEL_MASK      0x7f00  /* UDMA modes selected */
 346
 347 /* Identify Device: command set supported/enabled bits - word 206 */
 348
 349 /* All are SCT Command Transport support */
 350 #define SATA_SCT_CMD_TRANS_SUP          0x0001  /* anything */
 351 #define SATA_SCT_CMD_TRANS_LNG_SECT_SUP 0x0002  /* Long Sector Access */
 352 #define SATA_SCT_CMD_TRANS_WR_SAME_SUP  0x0004  /* Write Same */
 353 #define SATA_SCT_CMD_TRANS_ERR_RCOV_SUP 0x0008  /* Error Recovery Control */
 354 #define SATA_SCT_CMD_TRANS_FEAT_CTL_SUP 0x0010  /* Features Control */
 355 #define SATA_SCT_CMD_TRANS_DATA_TBL_SUP 0x0020  /* Data Tables supported */
 356
 357 #define SATA_DISK_SECTOR_SIZE   512     /* HD physical sector size */
 358
 359 /* Identify Packet Device data definitions (ATAPI devices) */
 360
 361 /* Identify Packet Device: general config bits  - word 0 */
 362
 363 #define SATA_ATAPI_TYPE_MASK    0xc000
 364 #define SATA_ATAPI_TYPE         0x8000  /* ATAPI device */
 365 #define SATA_ATAPI_ID_PKT_SZ    0x0003  /* Packet size mask */
 366 #define SATA_ATAPI_ID_PKT_12B   0x0000  /* Packet size 12 bytes */
 367 #define SATA_ATAPI_ID_PKT_16B   0x0001  /* Packet size 16 bytes */
 368 #define SATA_ATAPI_ID_DRQ_TYPE  0x0060  /* DRQ asserted in 3ms after pkt */
 369 #define SATA_ATAPI_ID_DRQ_INTR  0x0020  /* Obsolete in ATA/ATAPI 7 */
 370
 371 #define SATA_ATAPI_ID_DEV_TYPE  0x1f00  /* device type/command set mask */
 372 #define SATA_ATAPI_ID_DEV_SHFT  8
 373 #define SATA_ATAPI_DIRACC_DEV   0x0000  /* Direct Access device */
 374 #define SATA_ATAPI_SQACC_DEV    0x0100  /* Sequential access dev (tape ?) */
 375 #define SATA_ATAPI_PROC_DEV     0x0300  /* Processor device */
 376 #define SATA_ATAPI_CDROM_DEV    0x0500  /* CD_ROM device */
 377
 378 /*
 379  * Status bits from ATAPI Interrupt reason register (AT_COUNT) register
 380  */
 381 #define SATA_ATAPI_I_COD        0x01    /* Command or Data */
 382 #define SATA_ATAPI_I_IO         0x02    /* IO direction */
 383 #define SATA_ATAPI_I_RELEASE    0x04    /* Release for ATAPI overlap */
 384
 385 /* ATAPI feature reg definitions */
 386
 387 #define SATA_ATAPI_F_DATA_DIR_READ 0x04 /* DMA transfer to the host */
 388 #define SATA_ATAPI_F_OVERLAP    0x02    /* Not used by Sun drivers */
 389 #define SATA_ATAPI_F_DMA        0x01    /* Packet DMA command */
 390
 391
 392 /* ATAPI IDENTIFY_DRIVE capabilities word (49) */
 393
 394 #define SATA_ATAPI_ID_CAP_DMA           0x0100 /* if zero, check word 62  */
 395 #define SATA_ATAPI_ID_CAP_OVERLAP       0x2000
 396
 397 /*
 398  * ATAPI Identify Packet Device word 62
 399  * Word 62 is not valid for ATA/ATAPI-6
 400  * Defs below are for ATA/ATAPI-7
 401  */
 402 #define SATA_ATAPI_ID_DMADIR_REQ        0x8000 /* DMA direction required */
 403 #define SATA_ATAPI_ID_DMA_SUP           0x0400 /* DMA is supported */
 404
 405 /*
 406  * ATAPI signature bits
 407  */
 408 #define SATA_ATAPI_SIG_HI       0xeb    /* in high cylinder register */
 409 #define SATA_ATAPI_SIG_LO       0x14    /* in low cylinder register */
 410
 411 /* These values are pre-set for CD_ROM/DVD ? */
 412
 413 #define SATA_ATAPI_SECTOR_SIZE          2048
 414 #define SATA_ATAPI_MAX_BYTES_PER_DRQ    0xf800 /* 16 bits - 2KB  ie 62KB */
 415 #define SATA_ATAPI_HEADS                64
 416 #define SATA_ATAPI_SECTORS_PER_TRK      32
 417
 418 /* SATA Capabilites bits (word 76) */
 419
 420 #define SATA_NCQ                0x100
 421 #define SATA_3_SPEED            0x008
 422 #define SATA_2_SPEED            0x004
 423 #define SATA_1_SPEED            0x002
 424
 425 /* SATA Features Supported (word 78) - not used */
 426
 427 /* SATA Features Enabled (word 79) - not used */
 428
 429 #define SATA_READ_AHEAD_SUPPORTED(x)    ((x).ai_cmdset82 & SATA_LOOK_AHEAD)
 430 #define SATA_READ_AHEAD_ENABLED(x)      ((x).ai_features85 & SATA_LOOK_AHEAD)
 431 #define SATA_WRITE_CACHE_SUPPORTED(x)   ((x).ai_cmdset82 & SATA_WRITE_CACHE)
 432 #define SATA_WRITE_CACHE_ENABLED(x)     ((x).ai_features85 & SATA_WRITE_CACHE)
 433 #define SATA_RM_NOTIFIC_SUPPORTED(x)    \
 434         ((x).ai_cmdset83 & SATA_RM_STATUS_NOTIFIC)
 435 #define SATA_RM_NOTIFIC_ENABLED(x)      \
 436         ((x).ai_features86 & SATA_RM_STATUS_NOTIFIC)
 437
 438 /*
 439  * Generic NCQ related defines
 440  */
 441
 442 #define NQ                      0x80    /* Not a queued cmd - tag not valid */
 443 #define NCQ_TAG_MASK            0x1f    /* NCQ command tag mask */
 444 #define FIS_TYPE_REG_H2D        0x27    /* Reg FIS - Host to Device */
 445 #define FIS_CMD_UPDATE          0x80
 446 /*
 447  * Status bits from AT_STATUS register
 448  */
 449 #define SATA_STATUS_BSY         0x80    /* controller busy */
 450 #define SATA_STATUS_DRDY        0x40    /* drive ready  */
 451 #define SATA_STATUS_DF          0x20    /* device fault */
 452 #define SATA_STATUS_DSC         0x10    /* seek operation complete */
 453 #define SATA_STATUS_DRQ         0x08    /* data request */
 454 #define SATA_STATUS_CORR        0x04    /* obsolete */
 455 #define SATA_STATUS_IDX         0x02    /* obsolete */
 456 #define SATA_STATUS_ERR         0x01    /* error flag */
 457
 458 /*
 459  * Status bits from AT_ERROR register
 460  */
 461 #define SATA_ERROR_ICRC         0x80    /* CRC data transfer error detected */
 462 #define SATA_ERROR_UNC          0x40    /* uncorrectable data error */
 463 #define SATA_ERROR_MC           0x20    /* Media change */
 464 #define SATA_ERROR_IDNF         0x10    /* ID/Address not found */
 465 #define SATA_ERROR_MCR          0x08    /* media change request */
 466 #define SATA_ERROR_ABORT        0x04    /* aborted command */
 467 #define SATA_ERROR_NM           0x02    /* no media */
 468 #define SATA_ERROR_EOM          0x02    /* end of media (Packet cmds) */
 469 #define SATA_ERROR_ILI          0x01    /* cmd sepcific */
 470
 471
 472 /*
 473  * Bits from the device control register
 474  */
 475 #define SATA_DEVCTL_NIEN        0x02    /* not interrupt enabled */
 476 #define SATA_DEVCTL_SRST        0x04    /* software reset */
 477 #define SATA_DEVCTL_HOB         0x80    /* high order bit */
 478
 479 /* device_reg */
 480 #define SATA_ADH_LBA            0x40    /* addressing in LBA mode not chs */
 481
 482 /* ATAPI transport version-in Inquiry data */
 483 #define SATA_ATAPI_TRANS_VERSION(inq) \
 484         (*((uint8_t *)(inq) + 3) >> 4)
 485
 486 #define SCSI_LOG_PAGE_HDR_LEN   4       /* # bytes of a SCSI log page header */
 487 #define SCSI_LOG_PARAM_HDR_LEN  4       /* # byttes of a SCSI log param hdr */
 488
 489 /* Number of log entries per extended selftest log block */
 490 #define ENTRIES_PER_EXT_SELFTEST_LOG_BLK        19
 491
 492 /* Number of entries per SCSI LOG SENSE SELFTEST RESULTS page */
 493 #define SCSI_ENTRIES_IN_LOG_SENSE_SELFTEST_RESULTS      20
 494
 495 /* Length of a SCSI LOG SENSE SELFTEST RESULTS parameter */
 496 #define SCSI_LOG_SENSE_SELFTEST_PARAM_LEN       0x10
 497
 498 #define DIAGNOSTIC_FAILURE_ON_COMPONENT 0x40
 499
 500 #define SCSI_COMPONENT_81       0x81
 501 #define SCSI_COMPONENT_82       0x82
 502 #define SCSI_COMPONENT_83       0x83
 503 #define SCSI_COMPONENT_84       0x84
 504 #define SCSI_COMPONENT_85       0x85
 505 #define SCSI_COMPONENT_86       0x86
 506 #define SCSI_COMPONENT_87       0x87
 507 #define SCSI_COMPONENT_88       0x88
 508
 509 #define SCSI_ASC_ATA_DEV_FEAT_NOT_ENABLED       0x67
 510 #define SCSI_ASCQ_ATA_DEV_FEAT_NOT_ENABLED      0x0b
 511
 512 #define SCSI_PREDICTED_FAILURE  0x5d
 513 #define SCSI_GENERAL_HD_FAILURE 0x10
 514
 515 #define SCSI_INFO_EXCEPTIONS_PARAM_LEN  4
 516
 517 #define READ_LOG_EXT_LOG_DIRECTORY      0
 518 #define READ_LOG_EXT_NCQ_ERROR_RECOVERY 0x10
 519 #define SMART_SELFTEST_LOG_PAGE         6
 520 #define EXT_SMART_SELFTEST_LOG_PAGE     7
 521
 522 /*
 523  * SATA NCQ error recovery page (0x10)
 524  */
 525 struct sata_ncq_error_recovery_page {
 526         uint8_t ncq_tag;
 527         uint8_t reserved1;
 528         uint8_t ncq_status;
 529         uint8_t ncq_error;
 530         uint8_t ncq_sector_number;
 531         uint8_t ncq_cyl_low;
 532         uint8_t ncq_cyl_high;
 533         uint8_t ncq_dev_head;
 534         uint8_t ncq_sector_number_ext;
 535         uint8_t ncq_cyl_low_ext;
 536         uint8_t ncq_cyl_high_ext;
 537         uint8_t reserved2;
 538         uint8_t ncq_sector_count;
 539         uint8_t ncq_sector_count_ext;
 540         uint8_t reserved3[242];
 541         uint8_t ncq_vendor_unique[255];
 542         uint8_t ncq_checksum;
 543 };
 544
 545 /* SMART attribute of Start/Stop Count */
 546 #define SMART_START_STOP_COUNT_ID       0x4
 547
 548 /*
 549  * SMART data structures
 550  */
 551 struct smart_data {
 552         uint8_t smart_vendor_specific[362];
 553         uint8_t smart_offline_data_collection_status;
 554         uint8_t smart_selftest_exec_status;
 555         uint8_t smart_secs_to_complete_offline_data[2];
 556         uint8_t smart_vendor_specific2;
 557         uint8_t smart_offline_data_collection_capability;
 558         uint8_t smart_capability[2];
 559         uint8_t smart_error_logging_capability;
 560         uint8_t smart_vendor_specific3;
 561         uint8_t smart_short_selftest_polling_time;
 562         uint8_t smart_extended_selftest_polling_time;
 563         uint8_t smart_conveyance_selftest_polling_time;
 564         uint8_t smart_reserved[11];
 565         uint8_t smart_vendor_specific4[125];
 566         uint8_t smart_checksum;
 567 };
 568
 569 struct smart_selftest_log_entry {
 570         uint8_t smart_selftest_log_lba_low;
 571         uint8_t smart_selftest_log_status;
 572         uint8_t smart_selftest_log_timestamp[2];
 573         uint8_t smart_selftest_log_checkpoint;
 574         uint8_t smart_selftest_log_failing_lba[4];      /* from LSB to MSB */
 575         uint8_t smart_selftest_log_vendor_specific[15];
 576 };
 577
 578 #define NUM_SMART_SELFTEST_LOG_ENTRIES  21
 579 struct smart_selftest_log {
 580         uint8_t smart_selftest_log_revision[2];
 581         struct  smart_selftest_log_entry
 582             smart_selftest_log_entries[NUM_SMART_SELFTEST_LOG_ENTRIES];
 583         uint8_t smart_selftest_log_vendor_specific[2];
 584         uint8_t smart_selftest_log_index;
 585         uint8_t smart_selftest_log_reserved[2];
 586         uint8_t smart_selftest_log_checksum;
 587 };
 588
 589 struct smart_ext_selftest_log_entry {
 590         uint8_t smart_ext_selftest_log_lba_low;
 591         uint8_t smart_ext_selftest_log_status;
 592         uint8_t smart_ext_selftest_log_timestamp[2];
 593         uint8_t smart_ext_selftest_log_checkpoint;
 594         uint8_t smart_ext_selftest_log_failing_lba[6];
 595         uint8_t smart_ext_selftest_log_vendor_specific[15];
 596 };
 597
 598 struct smart_ext_selftest_log {
 599         uint8_t smart_ext_selftest_log_rev;
 600         uint8_t smart_ext_selftest_log_reserved;
 601         uint8_t smart_ext_selftest_log_index[2];
 602         struct smart_ext_selftest_log_entry smart_ext_selftest_log_entries[19];
 603         uint8_t smart_ext_selftest_log_vendor_specific[2];
 604         uint8_t smart_ext_selftest_log_reserved2[11];
 605         uint8_t smart_ext_selftest_log_checksum;
 606 };
 607
 608 struct read_log_ext_directory {
 609         uint8_t read_log_ext_vers[2];   /* general purpose log version */
 610         uint8_t read_log_ext_nblks[255][2]; /* # of blks @ log addr index+1 */
 611 };
 612
 613 /*
 614  * The definition of CONTROL byte field in SCSI command
 615  * according to SAM 5
 616  */
 617 #define CTL_BYTE_VENDOR_MASK            0xc0
 618 #define CTL_BYTE_NACA_MASK              0x04
 619
 620 /*
 621  * The definition of mask in START STOP UNIT command
 622  */
 623 #define START_STOP_IMMED_MASK           0x01
 624 #define START_STOP_POWER_COND_MASK      0xF0
 625 #define START_STOP_START_MASK           0x01
 626 #define START_STOP_LOEJ_MASK            0x02
 627 #define START_STOP_NOFLUSH_MASK         0x04
 628 #define START_STOP_MODIFIER_MASK        0x0f
 629 #define START_STOP_POWER_COND_SHIFT     4
 630
 631 /*
 632  * SMART specific data
 633  * These eventually need to go to a generic scsi header file
 634  * for now they will reside here
 635  */
 636 #define PC_CUMULATIVE_VALUES                    0x01
 637 #define PAGE_CODE_GET_SUPPORTED_LOG_PAGES       0x00
 638 #define PAGE_CODE_SELF_TEST_RESULTS             0x10
 639 #define PAGE_CODE_INFORMATION_EXCEPTIONS        0x2f
 640 #define PAGE_CODE_SMART_READ_DATA               0x30
 641 #define PAGE_CODE_START_STOP_CYCLE_COUNTER      0x0e
 642
 643
 644 struct log_parameter {
 645         uint8_t param_code[2];          /* parameter dependant */
 646         uint8_t param_ctrl_flags;       /* see defines below */
 647         uint8_t param_len;              /* # of bytes following */
 648         uint8_t param_values[1];        /* # of bytes defined by param_len */
 649 };
 650
 651 /* param_ctrl_flag fields */
 652 #define LOG_CTRL_LP     0x01    /* list parameter */
 653 #define LOG_CTRL_LBIN   0x02    /* list is binary */
 654 #define LOG_CTRL_TMC    0x0c    /* threshold met criteria */
 655 #define LOG_CTRL_ETC    0x10    /* enable threshold comparison */
 656 #define LOG_CTRL_TSD    0x20    /* target save disable */
 657 #define LOG_CTRL_DS     0x40    /* disable save */
 658 #define LOG_CTRL_DU     0x80    /* disable update */
 659
 660 #define SMART_MAGIC_VAL_1       0x4f
 661 #define SMART_MAGIC_VAL_2       0xc2
 662 #define SMART_MAGIC_VAL_3       0xf4
 663 #define SMART_MAGIC_VAL_4       0x2c
 664
 665 #define SCT_STATUS_LOG_PAGE     0xe0
 666
 667 /*
 668  * Acoustic management
 669  */
 670
 671 struct mode_acoustic_management {
 672         struct mode_page        mode_page;      /* common mode page header */
 673         uchar_t acoustic_manag_enable;  /* Set to 1 enable, Set 0 disable */
 674         uchar_t acoustic_manag_level;   /* Acoustic management level      */
 675         uchar_t vendor_recommended_value; /* Vendor recommended value     */
 676 };
 677
 678 #define PAGELENGTH_DAD_MODE_ACOUSTIC_MANAGEMENT 3 /* Acoustic manag pg len */
 679 #define P_CNTRL_CURRENT         0
 680 #define P_CNTRL_CHANGEABLE      1
 681 #define P_CNTRL_DEFAULT         2
 682 #define P_CNTRL_SAVED           3
 683
 684 #define ACOUSTIC_DISABLED       0
 685 #define ACOUSTIC_ENABLED        1
 686
 687 #define MODEPAGE_ACOUSTIC_MANAG 0x30
 688
 689 /*
 690  * Port Multiplier registers' offsets
 691  */
 692 #define SATA_PMULT_GSCR0                0x0
 693 #define SATA_PMULT_GSCR1                0x1
 694 #define SATA_PMULT_GSCR2                0x2
 695 #define SATA_PMULT_GSCR32               0x20
 696 #define SATA_PMULT_GSCR33               0x21
 697 #define SATA_PMULT_GSCR64               0x40
 698 #define SATA_PMULT_GSCR96               0x60
 699
 700 #define SATA_PMULT_PORTNUM_MASK         0xf
 701
 702 #define SATA_PMULT_PSCR0                0x0
 703 #define SATA_PMULT_PSCR1                0x1
 704 #define SATA_PMULT_PSCR2                0x2
 705 #define SATA_PMULT_PSCR3                0x3
 706 #define SATA_PMULT_PSCR4                0x4
 707
 708 #define SATA_PMULT_REG_SSTS             (SATA_PMULT_PSCR0)
 709 #define SATA_PMULT_REG_SERR             (SATA_PMULT_PSCR1)
 710 #define SATA_PMULT_REG_SCTL             (SATA_PMULT_PSCR2)
 711 #define SATA_PMULT_REG_SACT             (SATA_PMULT_PSCR3)
 712 #define SATA_PMULT_REG_SNTF             (SATA_PMULT_PSCR4)
 713
 714 /*
 715  * Port Multiplier capabilities
 716  * (Indicated by GSCR64, and enabled by GSCR96)
 717  */
 718 #define SATA_PMULT_CAP_BIST             (1 << 0)
 719 #define SATA_PMULT_CAP_PMREQ            (1 << 1)
 720 #define SATA_PMULT_CAP_SSC              (1 << 2)
 721 #define SATA_PMULT_CAP_SNOTIF           (1 << 3)
 722 #define SATA_PMULT_CAP_PHYEVENT         (1 << 4)
 723
 724 /*
 725  * sstatus field definitions
 726  */
 727 #define SSTATUS_DET_SHIFT       0
 728 #define SSTATUS_SPD_SHIFT       4
 729 #define SSTATUS_IPM_SHIFT       8
 730
 731 #define SSTATUS_DET     (0xf << SSTATUS_DET_SHIFT)
 732 #define SSTATUS_SPD     (0xf << SSTATUS_SPD_SHIFT)
 733 #define SSTATUS_IPM     (0xf << SSTATUS_IPM_SHIFT)
 734
 735 /*
 736  * sstatus DET values
 737  */
 738 #define SSTATUS_DET_NODEV               0       /* No dev detected */
 739 #define SSTATUS_DET_DEVPRE_NOPHYCOM     1       /* dev detected */
 740 #define SSTATUS_DET_DEVPRE_PHYCOM       3       /* dev detected */
 741 #define SSTATUS_DET_PHYOFFLINE          4       /* PHY is in offline */
 742
 743 #define SSTATUS_GET_DET(x) \
 744         (x & SSTATUS_DET)
 745
 746 #define SSTATUS_SET_DET(x, new_val) \
 747         (x = (x & ~SSTATUS_DET) | (new_val & SSTATUS_DET))
 748
 749 #define SSTATUS_SPD_NODEV       0 /* No device present */
 750 #define SSTATUS_SPD_GEN1        1 /* Gen 1 rate negotiated */
 751 #define SSTATUS_SPD_GEN2        2 /* Gen 2 rate negotiated */
 752 #define SSTATUS_SPD_GEN3        3 /* Gen 3 rate negotiated */
 753
 754 /*
 755  * sstatus IPM values
 756  */
 757 #define SSTATUS_IPM_NODEV_NOPHYCOM      0x0 /* No dev, no PHY */
 758 #define SSTATUS_IPM_ACTIVE              0x1 /* Interface active */
 759 #define SSTATUS_IPM_POWERPARTIAL        0x2 /* partial power mgmnt */
 760 #define SSTATUS_IPM_POWERSLUMBER        0x6 /* slumber power mgmt */
 761
 762 #define SSTATUS_GET_IPM(x) \
 763         ((x & SSTATUS_IPM) >> SSTATUS_IPM_SHIFT)
 764
 765 #define SSTATUS_SET_IPM(x, new_val) \
 766         (x = (x & ~SSTATUS_IPM) | \
 767         ((new_val << SSTATUS_IPM_SHIFT) & SSTATUS_IPM))
 768
 769
 770 /*
 771  * serror register fields
 772  */
 773 #define SERROR_DATA_ERR_FIXED   (1 << 0) /* D integrity err */
 774 #define SERROR_COMM_ERR_FIXED   (1 << 1) /* comm err recov */
 775 #define SERROR_DATA_ERR         (1 << 8) /* D integrity err */
 776 #define SERROR_PERSISTENT_ERR   (1 << 9)  /* norecov com err */
 777 #define SERROR_PROTOCOL_ERR     (1 << 10) /* protocol err */
 778 #define SERROR_INT_ERR          (1 << 11) /* internal err */
 779 #define SERROR_PHY_RDY_CHG      (1 << 16) /* PHY state change */
 780 #define SERROR_PHY_INT_ERR      (1 << 17) /* PHY internal err */
 781 #define SERROR_COMM_WAKE        (1 << 18) /* COM wake */
 782 #define SERROR_10B_TO_8B_ERR    (1 << 19) /* 10B-to-8B decode */
 783 #define SERROR_DISPARITY_ERR    (1 << 20) /* disparity err */
 784 #define SERROR_CRC_ERR          (1 << 21) /* CRC err */
 785 #define SERROR_HANDSHAKE_ERR    (1 << 22) /* Handshake err */
 786 #define SERROR_LINK_SEQ_ERR     (1 << 23) /* Link seq err */
 787 #define SERROR_TRANS_ERR        (1 << 24) /* Tran state err */
 788 #define SERROR_FIS_TYPE         (1 << 25) /* FIS type err */
 789 #define SERROR_EXCHANGED_ERR    (1 << 26) /* Device exchanged */
 790
 791 /*
 792  * S-Control Bridge port x register fields
 793  */
 794 #define SCONTROL_DET_SHIFT      0
 795 #define SCONTROL_SPD_SHIFT      4
 796 #define SCONTROL_IPM_SHIFT      8
 797 #define SCONTROL_SPM_SHIFT      12
 798
 799 #define SCONTROL_DET            (0xf << SCONTROL_DET_SHIFT)
 800 #define SCONTROL_SPD            (0xf << SCONTROL_SPD_SHIFT)
 801 #define SCONTROL_IPM            (0xf << SCONTROL_IPM_SHIFT)
 802 #define SCONTROL_SPM            (0xf << SCONTROL_SPM_SHIFT)
 803
 804 #define SCONTROL_GET_DET(x)     \
 805         (x & SCONTROL_DET)
 806
 807 #define SCONTROL_SET_DET(x, new_val)    \
 808         (x = (x & ~SCONTROL_DET) | (new_val & SCONTROL_DET))
 809
 810 #define SCONTROL_DET_NOACTION   0 /* Do nothing to port */
 811 #define SCONTROL_DET_COMRESET   1 /* Re-initialize port */
 812 #define SCONTROL_DET_DISABLE    4 /* Disable port */
 813
 814 #define SCONTROL_SPD_NOLIMIT    0 /* No speed limit */
 815 #define SCONTROL_SPD_GEN1       1 /* Limit Gen 1 rate */
 816 #define SCONTROL_SPD_GEN2       2 /* Limit Gen 2 rate */
 817 #define SCONTROL_SPD_GEN3       3 /* Limit Gen 3 rate */
 818
 819 #define SCONTROL_GET_IPM(x)     \
 820         ((x & SCONTROL_IPM) >> SCONTROL_IPM_SHIFT)
 821
 822 #define SCONTROL_SET_IPM(x, new_val)    \
 823         (x = (x & ~SCONTROL_IPM) | \
 824         ((new_val << SCONTROL_IPM_SHIFT) & SCONTROL_IPM))
 825
 826 #define SCONTROL_IPM_NORESTRICT         0 /* No PM limit */
 827 #define SCONTROL_IPM_DISABLE_PARTIAL    1 /* Disable partial */
 828 #define SCONTROL_IPM_DISABLE_SLUMBER    2 /* Disable slumber */
 829 #define SCONTROL_IPM_DISABLE_BOTH       3 /* Disable both */
 830
 831 #define SCONTROL_SPM_NORESTRICT         0 /* No PM limits */
 832 #define SCONTROL_SPM_DO_PARTIAL         1 /* Go to partial */
 833 #define SCONTROL_SPM_DO_SLUMBER         2 /* Go to slumber */
 834 #define SCONTROL_SPM_DO_ACTIVE          4 /* Go to active */
 835
 836 #ifdef  __cplusplus
 837 }
 838 #endif
 839
 840 #endif /* _SATA_DEFS_H */