4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
22 * Copyright (c) 2012 Gary Mills
24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 * Copyright 2018 Joyent, Inc.
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
33 #include <sys/types.h>
34 #include <sys/sysmacros.h>
36 #include <sys/promif.h>
37 #include <sys/clock.h>
38 #include <sys/cpuvar.h>
39 #include <sys/stack.h>
42 #include <sys/reboot.h>
43 #include <sys/avintr.h>
44 #include <sys/vtrace.h>
46 #include <sys/thread.h>
47 #include <sys/cpupart.h>
49 #include <sys/copyops.h>
52 #include <sys/debug.h>
53 #include <sys/sunddi.h>
54 #include <sys/x86_archext.h>
55 #include <sys/privregs.h>
56 #include <sys/machsystm.h>
57 #include <sys/ontrap.h>
58 #include <sys/bootconf.h>
59 #include <sys/boot_console.h>
60 #include <sys/kdi_machimpl.h>
61 #include <sys/archsystm.h>
62 #include <sys/promif.h>
63 #include <sys/pci_cfgspace.h>
64 #include <sys/bootvfs.h>
67 #include <sys/hypervisor.h>
69 #include <sys/xpv_support.h>
73 * some globals for patching the result of cpuid
74 * to solve problems w/ creative cpu vendors
77 extern uint32_t cpuid_feature_ecx_include
;
78 extern uint32_t cpuid_feature_ecx_exclude
;
79 extern uint32_t cpuid_feature_edx_include
;
80 extern uint32_t cpuid_feature_edx_exclude
;
86 set_console_mode(uint8_t val
)
88 struct bop_regs rp
= {0};
94 BOP_DOINT(bootops
, 0x10, &rp
);
99 * Setup routine called right before main(). Interposing this function
100 * before main() allows us to call it in a machine-independent fashion.
103 mlsetup(struct regs
*rp
)
105 u_longlong_t prop_value
;
106 extern struct classfuncs sys_classfuncs
;
107 extern disp_t cpu0_disp
;
108 extern char t0stack
[];
109 extern int post_fastreboot
;
110 extern uint64_t plat_dr_options
;
112 ASSERT_STACK_ALIGNED();
115 * initialize cpu_self
117 cpu
[0]->cpu_self
= cpu
[0];
121 * Point at the hypervisor's virtual cpu structure
123 cpu
[0]->cpu_m
.mcpu_vcpu_info
= &HYPERVISOR_shared_info
->vcpu_info
[0];
127 * check if we've got special bits to clear or set
128 * when checking cpu features
131 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value
) != 0)
132 cpuid_feature_ecx_include
= 0;
134 cpuid_feature_ecx_include
= (uint32_t)prop_value
;
136 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value
) != 0)
137 cpuid_feature_ecx_exclude
= 0;
139 cpuid_feature_ecx_exclude
= (uint32_t)prop_value
;
141 if (bootprop_getval("cpuid_feature_edx_include", &prop_value
) != 0)
142 cpuid_feature_edx_include
= 0;
144 cpuid_feature_edx_include
= (uint32_t)prop_value
;
146 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value
) != 0)
147 cpuid_feature_edx_exclude
= 0;
149 cpuid_feature_edx_exclude
= (uint32_t)prop_value
;
153 * Check to see if KPTI has been explicitly enabled or disabled.
154 * We have to check this before init_desctbls().
156 if (bootprop_getval("kpti", &prop_value
) == 0) {
157 kpti_enable
= (uint64_t)(prop_value
== 1);
158 prom_printf("unix: forcing kpti to %s due to boot argument\n",
159 (kpti_enable
== 1) ? "ON" : "OFF");
164 if (bootprop_getval("pcid", &prop_value
) == 0 && prop_value
== 0) {
165 prom_printf("unix: forcing pcid to OFF due to boot argument\n");
167 } else if (kpti_enable
!= 1) {
173 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
178 * lgrp_init() and possibly cpuid_pass1() need PCI config
182 if (DOMAIN_IS_INITDOMAIN(xen_info
))
187 * Initialize the platform type from CPU 0 to ensure that
188 * determine_platform() is only ever called once.
190 determine_platform();
194 * The first lightweight pass (pass0) through the cpuid data
195 * was done in locore before mlsetup was called. Do the next
198 * The x86_featureset is initialized here based on the capabilities
199 * of the boot CPU. Note that if we choose to support CPUs that have
200 * different feature sets (at which point we would almost certainly
201 * want to set the feature bits to correspond to the feature
202 * minimum) this value may be altered.
204 cpuid_pass1(cpu
[0], x86_featureset
);
207 if ((get_hwenv() & HW_XEN_HVM
) != 0)
211 * Before we do anything with the TSCs, we need to work around
212 * Intel erratum BT81. On some CPUs, warm reset does not
213 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
214 * here. Other CPUs will clear it when we boot them later, and the
215 * resulting skew will be handled by tsc_sync_master()/_slave();
216 * note that such skew already exists and has to be handled anyway.
218 * We do this only on metal. This same problem can occur with a
219 * hypervisor that does not happen to virtualise a TSC that starts from
220 * zero, regardless of CPU type; however, we do not expect hypervisors
221 * that do not virtualise TSC that way to handle writes to TSC
224 if (get_hwenv() == HW_NATIVE
&&
225 cpuid_getvendor(CPU
) == X86_VENDOR_Intel
&&
226 cpuid_getfamily(CPU
) == 6 &&
227 (cpuid_getmodel(CPU
) == 0x2d || cpuid_getmodel(CPU
) == 0x3e) &&
228 is_x86_feature(x86_featureset
, X86FSET_TSC
)) {
229 (void) wrmsr(REG_TSC
, 0UL);
233 * Patch the tsc_read routine with appropriate set of instructions,
234 * depending on the processor family and architecure, to read the
235 * time-stamp counter while ensuring no out-of-order execution.
236 * Patch it while the kernel text is still writable.
238 * Note: tsc_read is not patched for intel processors whose family
239 * is >6 and for amd whose family >f (in case they don't support rdtscp
240 * instruction, unlikely). By default tsc_read will use cpuid for
241 * serialization in such cases. The following code needs to be
242 * revisited if intel processors of family >= f retains the
243 * instruction serialization nature of mfence instruction.
244 * Note: tsc_read is not patched for x86 processors which do
245 * not support "mfence". By default tsc_read will use cpuid for
246 * serialization in such cases.
248 * The Xen hypervisor does not correctly report whether rdtscp is
249 * supported or not, so we must assume that it is not.
251 if ((get_hwenv() & HW_XEN_HVM
) == 0 &&
252 is_x86_feature(x86_featureset
, X86FSET_TSCP
))
253 patch_tsc_read(TSC_TSCP
);
254 else if (cpuid_getvendor(CPU
) == X86_VENDOR_AMD
&&
255 cpuid_getfamily(CPU
) <= 0xf &&
256 is_x86_feature(x86_featureset
, X86FSET_SSE2
))
257 patch_tsc_read(TSC_RDTSC_MFENCE
);
258 else if (cpuid_getvendor(CPU
) == X86_VENDOR_Intel
&&
259 cpuid_getfamily(CPU
) <= 6 &&
260 is_x86_feature(x86_featureset
, X86FSET_SSE2
))
261 patch_tsc_read(TSC_RDTSC_LFENCE
);
265 #if defined(__i386) && !defined(__xpv)
267 * Some i386 processors do not implement the rdtsc instruction,
268 * or at least they do not implement it correctly. Patch them to
271 if (!is_x86_feature(x86_featureset
, X86FSET_TSC
))
272 patch_tsc_read(TSC_NONE
);
273 #endif /* __i386 && !__xpv */
275 #if defined(__amd64) && !defined(__xpv)
276 patch_memops(cpuid_getvendor(CPU
));
277 #endif /* __amd64 && !__xpv */
280 /* XXPV what, if anything, should be dorked with here under xen? */
283 * While we're thinking about the TSC, let's set up %cr4 so that
284 * userland can issue rdtsc, and initialize the TSC_AUX value
285 * (the cpuid) for the rdtscp instruction on appropriately
288 if (is_x86_feature(x86_featureset
, X86FSET_TSC
))
289 setcr4(getcr4() & ~CR4_TSD
);
291 if (is_x86_feature(x86_featureset
, X86FSET_TSCP
))
292 (void) wrmsr(MSR_AMD_TSCAUX
, 0);
295 * Let's get the other %cr4 stuff while we're here. Note, we defer
296 * enabling CR4_SMAP until startup_end(); however, that's importantly
297 * before we start other CPUs. That ensures that it will be synced out
300 if (is_x86_feature(x86_featureset
, X86FSET_DE
))
301 setcr4(getcr4() | CR4_DE
);
303 if (is_x86_feature(x86_featureset
, X86FSET_SMEP
))
304 setcr4(getcr4() | CR4_SMEP
);
310 t0
.t_stk
= (caddr_t
)rp
- MINFRAME
;
311 t0
.t_stkbase
= t0stack
;
312 t0
.t_pri
= maxclsyspri
- 3;
313 t0
.t_schedflag
= TS_LOAD
| TS_DONT_SWAP
;
315 t0
.t_plockp
= &p0lock
.pl_lock
;
322 t0
.t_disp_queue
= &cpu0_disp
;
323 t0
.t_bind_cpu
= PBIND_NONE
;
324 t0
.t_bind_pset
= PS_NONE
;
325 t0
.t_bindflag
= (uchar_t
)default_binding_mode
;
326 t0
.t_cpupart
= &cp_default
;
327 t0
.t_clfuncs
= &sys_classfuncs
.thread
;
329 THREAD_ONPROC(&t0
, CPU
);
331 lwp0
.lwp_thread
= &t0
;
332 lwp0
.lwp_regs
= (void *)rp
;
333 lwp0
.lwp_procp
= &p0
;
334 t0
.t_tid
= p0
.p_lwpcnt
= p0
.p_lwprcnt
= p0
.p_lwpid
= 1;
340 p0
.p_stksize
= 2*PAGESIZE
;
343 p0
.p_lockp
= &p0lock
;
345 p0
.p_t1_lgrpid
= LGRP_NONE
;
346 p0
.p_tr_lgrpid
= LGRP_NONE
;
347 psecflags_default(&p0
.p_secflags
);
349 sigorset(&p0
.p_ignore
, &ignoredefault
);
351 CPU
->cpu_thread
= &t0
;
352 bzero(&cpu0_disp
, sizeof (disp_t
));
353 CPU
->cpu_disp
= &cpu0_disp
;
354 CPU
->cpu_disp
->disp_cpu
= CPU
;
355 CPU
->cpu_dispthread
= &t0
;
356 CPU
->cpu_idle_thread
= &t0
;
357 CPU
->cpu_flags
= CPU_READY
| CPU_RUNNING
| CPU_EXISTS
| CPU_ENABLE
;
358 CPU
->cpu_dispatch_pri
= t0
.t_pri
;
362 CPU
->cpu_pri
= 12; /* initial PIL for the boot CPU */
365 * Initialize thread/cpu microstate accounting
367 init_mstate(&t0
, LMS_SYSTEM
);
368 init_cpu_mstate(CPU
, CMS_SYSTEM
);
371 * Initialize lists of available and active CPUs.
375 pg_cpu_bootstrap(CPU
);
378 * Now that we have taken over the GDT, IDT and have initialized
379 * active CPU list it's time to inform kmdb if present.
381 if (boothowto
& RB_DEBUG
)
384 if (BOP_GETPROPLEN(bootops
, "efi-systab") < 0) {
386 * In BIOS system, explicitly set console to text mode (0x3)
387 * if this is a boot post Fast Reboot, and the console is set
388 * to CONS_SCREEN_TEXT.
390 if (post_fastreboot
&&
391 boot_console_type(NULL
) == CONS_SCREEN_TEXT
) {
392 set_console_mode(0x3);
397 * If requested (boot -d) drop into kmdb.
399 * This must be done after cpu_list_init() on the 64-bit kernel
400 * since taking a trap requires that we re-compute gsbase based
403 if (boothowto
& RB_DEBUGENTER
)
406 cpu_vm_data_init(CPU
);
408 rp
->r_fp
= 0; /* terminate kernel stack traces! */
410 prom_init("kernel", (void *)NULL
);
412 /* User-set option overrides firmware value. */
413 if (bootprop_getval(PLAT_DR_OPTIONS_NAME
, &prop_value
) == 0) {
414 plat_dr_options
= (uint64_t)prop_value
;
417 /* No support of DR operations on xpv */
420 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
421 plat_dr_options
&= ~PLAT_DR_FEATURE_ENABLED
;
423 /* Only enable CPU/memory DR on 64 bits kernel. */
424 plat_dr_options
&= ~PLAT_DR_FEATURE_MEMORY
;
425 plat_dr_options
&= ~PLAT_DR_FEATURE_CPU
;
430 * Get value of "plat_dr_physmax" boot option.
431 * It overrides values calculated from MSCT or SRAT table.
433 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME
, &prop_value
) == 0) {
434 plat_dr_physmax
= ((uint64_t)prop_value
) >> PAGESHIFT
;
437 /* Get value of boot_ncpus. */
438 if (bootprop_getval(BOOT_NCPUS_NAME
, &prop_value
) != 0) {
441 boot_ncpus
= (int)prop_value
;
442 if (boot_ncpus
<= 0 || boot_ncpus
> NCPU
)
447 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
448 * support CPU DR operations.
450 if (plat_dr_support_cpu() == 0) {
451 max_ncpus
= boot_max_ncpus
= boot_ncpus
;
453 if (bootprop_getval(PLAT_MAX_NCPUS_NAME
, &prop_value
) != 0) {
456 max_ncpus
= (int)prop_value
;
457 if (max_ncpus
<= 0 || max_ncpus
> NCPU
) {
460 if (boot_ncpus
> max_ncpus
) {
461 boot_ncpus
= max_ncpus
;
465 if (bootprop_getval(BOOT_MAX_NCPUS_NAME
, &prop_value
) != 0) {
466 boot_max_ncpus
= boot_ncpus
;
468 boot_max_ncpus
= (int)prop_value
;
469 if (boot_max_ncpus
<= 0 || boot_max_ncpus
> NCPU
) {
470 boot_max_ncpus
= boot_ncpus
;
471 } else if (boot_max_ncpus
> max_ncpus
) {
472 boot_max_ncpus
= max_ncpus
;
478 * Initialize the lgrp framework
480 lgrp_init(LGRP_INIT_STAGE1
);
482 if (boothowto
& RB_HALT
) {
483 prom_printf("unix: kernel halted by -h flag\n");
487 ASSERT_STACK_ALIGNED();
490 * Fill out cpu_ucode_info. Update microcode if necessary.
493 cpuid_pass_ucode(CPU
, x86_featureset
);
495 if (workaround_errata(CPU
) != 0)
496 panic("critical workaround(s) missing for boot cpu");
501 mach_modpath(char *path
, const char *filename
)
504 * Construct the directory path from the filename.
509 const char isastr
[] = "/amd64";
510 size_t isalen
= strlen(isastr
);
512 len
= strlen(SYSTEM_BOOT_PATH
"/kernel");
513 (void) strcpy(path
, SYSTEM_BOOT_PATH
"/kernel ");
516 if ((p
= strrchr(filename
, '/')) == NULL
)
519 while (p
> filename
&& *(p
- 1) == '/')
520 p
--; /* remove trailing '/' characters */
522 p
++; /* so "/" -is- the modpath in this case */
525 * Remove optional isa-dependent directory name - the module
526 * subsystem will put this back again (!)
530 strncmp(&filename
[len
- isalen
], isastr
, isalen
) == 0)
534 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
536 len
+= (p
- filename
) + 1 + strlen(MOD_DEFPATH
) + 1;
537 (void) strncpy(path
, filename
, p
- filename
);