include/sys/nvme.h

   1 /*
   2  * This file and its contents are supplied under the terms of the
   3  * Common Development and Distribution License ("CDDL"), version 1.0.
   4  * You may only use this file in accordance with the terms of version
   5  * 1.0 of the CDDL.
   6  *
   7  * A full copy of the text of the CDDL should have accompanied this
   8  * source.  A copy of the CDDL is also available via the Internet at
   9  * http://www.illumos.org/license/CDDL.
  10  */
  11
  12 /*
  13  * Copyright 2016 Nexenta Systems, Inc.
  14  */
  15
  16 #ifndef _SYS_NVME_H
  17 #define _SYS_NVME_H
  18
  19 #include <sys/types.h>
  20
  21 #ifdef _KERNEL
  22 #include <sys/types32.h>
  23 #else
  24 #include <stdint.h>
  25 #endif
  26
  27 /*
  28  * Declarations used for communication between nvmeadm(8) and nvme(7D)
  29  */
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 /*
  36  * NVMe ioctl definitions
  37  */
  38
  39 #define NVME_IOC                        (('N' << 24) | ('V' << 16) | ('M' << 8))
  40 #define NVME_IOC_IDENTIFY_CTRL          (NVME_IOC | 1)
  41 #define NVME_IOC_IDENTIFY_NSID          (NVME_IOC | 2)
  42 #define NVME_IOC_CAPABILITIES           (NVME_IOC | 3)
  43 #define NVME_IOC_GET_LOGPAGE            (NVME_IOC | 4)
  44 #define NVME_IOC_GET_FEATURES           (NVME_IOC | 5)
  45 #define NVME_IOC_INTR_CNT               (NVME_IOC | 6)
  46 #define NVME_IOC_VERSION                (NVME_IOC | 7)
  47 #define NVME_IOC_FORMAT                 (NVME_IOC | 8)
  48 #define NVME_IOC_DETACH                 (NVME_IOC | 9)
  49 #define NVME_IOC_ATTACH                 (NVME_IOC | 10)
  50 #define NVME_IOC_MAX                    NVME_IOC_ATTACH
  51
  52 #define IS_NVME_IOC(x)                  ((x) > NVME_IOC && (x) <= NVME_IOC_MAX)
  53 #define NVME_IOC_CMD(x)                 ((x) & 0xff)
  54
  55 typedef struct {
  56         size_t          n_len;
  57         uintptr_t       n_buf;
  58         uint64_t        n_arg;
  59 } nvme_ioctl_t;
  60
  61 #ifdef _KERNEL
  62 typedef struct {
  63         size32_t        n_len;
  64         uintptr32_t     n_buf;
  65         uint64_t        n_arg;
  66 } nvme_ioctl32_t;
  67 #endif
  68
  69 /*
  70  * NVMe capabilities
  71  */
  72 typedef struct {
  73         uint32_t mpsmax;                /* Memory Page Size Maximum */
  74         uint32_t mpsmin;                /* Memory Page Size Minimum */
  75 } nvme_capabilities_t;
  76
  77 /*
  78  * NVMe version
  79  */
  80 typedef struct {
  81         uint16_t v_minor;
  82         uint16_t v_major;
  83 } nvme_version_t;
  84
  85 #define NVME_VERSION_ATLEAST(v, maj, min) \
  86         (((v)->v_major) > (maj) || \
  87         ((v)->v_major == (maj) && (v)->v_minor >= (min)))
  88
  89 #define NVME_VERSION_HIGHER(v, maj, min) \
  90         (((v)->v_major) > (maj) || \
  91         ((v)->v_major == (maj) && (v)->v_minor > (min)))
  92
  93
  94 #pragma pack(1)
  95
  96 /*
  97  * NVMe Identify data structures
  98  */
  99
 100 #define NVME_IDENTIFY_BUFSIZE   4096    /* buffer size for Identify */
 101
 102 /* NVMe Queue Entry Size bitfield */
 103 typedef struct {
 104         uint8_t qes_min:4;              /* minimum entry size */
 105         uint8_t qes_max:4;              /* maximum entry size */
 106 } nvme_idctl_qes_t;
 107
 108 /* NVMe Power State Descriptor */
 109 typedef struct {
 110         uint16_t psd_mp;                /* Maximum Power */
 111         uint8_t psd_rsvd1;
 112         uint8_t psd_mps:1;              /* Max Power Scale (1.1) */
 113         uint8_t psd_nops:1;             /* Non-Operational State (1.1) */
 114         uint8_t psd_rsvd2:6;
 115         uint32_t psd_enlat;             /* Entry Latency */
 116         uint32_t psd_exlat;             /* Exit Latency */
 117         uint8_t psd_rrt:5;              /* Relative Read Throughput */
 118         uint8_t psd_rsvd3:3;
 119         uint8_t psd_rrl:5;              /* Relative Read Latency */
 120         uint8_t psd_rsvd4:3;
 121         uint8_t psd_rwt:5;              /* Relative Write Throughput */
 122         uint8_t psd_rsvd5:3;
 123         uint8_t psd_rwl:5;              /* Relative Write Latency */
 124         uint8_t psd_rsvd6:3;
 125         uint8_t psd_rsvd7[16];
 126 } nvme_idctl_psd_t;
 127
 128 /* NVMe Identify Controller Data Structure */
 129 typedef struct {
 130         /* Controller Capabilities & Features */
 131         uint16_t id_vid;                /* PCI vendor ID */
 132         uint16_t id_ssvid;              /* PCI subsystem vendor ID */
 133         char id_serial[20];             /* Serial Number */
 134         char id_model[40];              /* Model Number */
 135         char id_fwrev[8];               /* Firmware Revision */
 136         uint8_t id_rab;                 /* Recommended Arbitration Burst */
 137         uint8_t id_oui[3];              /* vendor IEEE OUI */
 138         struct {                        /* Multi-Interface Capabilities */
 139                 uint8_t m_multi_pci:1;  /* HW has multiple PCIe interfaces */
 140                 uint8_t m_multi_ctrl:1; /* HW has multiple controllers (1.1) */
 141                 uint8_t m_sr_iov:1;     /* controller is SR-IOV virt fn (1.1) */
 142                 uint8_t m_rsvd:5;
 143         } id_mic;
 144         uint8_t id_mdts;                /* Maximum Data Transfer Size */
 145         uint16_t id_cntlid;             /* Unique Controller Identifier (1.1) */
 146         uint8_t id_rsvd_cc[256 - 80];
 147
 148         /* Admin Command Set Attributes */
 149         struct {                        /* Optional Admin Command Support */
 150                 uint16_t oa_security:1; /* Security Send & Receive */
 151                 uint16_t oa_format:1;   /* Format NVM */
 152                 uint16_t oa_firmware:1; /* Firmware Activate & Download */
 153                 uint16_t oa_rsvd:13;
 154         } id_oacs;
 155         uint8_t id_acl;                 /* Abort Command Limit */
 156         uint8_t id_aerl;                /* Asynchronous Event Request Limit */
 157         struct {                        /* Firmware Updates */
 158                 uint8_t fw_readonly:1;  /* Slot 1 is Read-Only */
 159                 uint8_t fw_nslot:3;     /* number of firmware slots */
 160                 uint8_t fw_rsvd:4;
 161         } id_frmw;
 162         struct {                        /* Log Page Attributes */
 163                 uint8_t lp_smart:1;     /* SMART/Health information per NS */
 164                 uint8_t lp_rsvd:7;
 165         } id_lpa;
 166         uint8_t id_elpe;                /* Error Log Page Entries */
 167         uint8_t id_npss;                /* Number of Power States */
 168         struct {                        /* Admin Vendor Specific Command Conf */
 169                 uint8_t av_spec:1;      /* use format from spec */
 170                 uint8_t av_rsvd:7;
 171         } id_avscc;
 172         struct {                        /* Autonomous Power State Trans (1.1) */
 173                 uint8_t ap_sup:1;       /* APST supported (1.1) */
 174                 uint8_t ap_rsvd:7;
 175         } id_apsta;
 176         uint8_t id_rsvd_ac[256 - 10];
 177
 178         /* NVM Command Set Attributes */
 179         nvme_idctl_qes_t id_sqes;       /* Submission Queue Entry Size */
 180         nvme_idctl_qes_t id_cqes;       /* Completion Queue Entry Size */
 181         uint16_t id_rsvd_nc_1;
 182         uint32_t id_nn;                 /* Number of Namespaces */
 183         struct {                        /* Optional NVM Command Support */
 184                 uint16_t on_compare:1;  /* Compare */
 185                 uint16_t on_wr_unc:1;   /* Write Uncorrectable */
 186                 uint16_t on_dset_mgmt:1; /* Dataset Management */
 187                 uint16_t on_wr_zero:1;  /* Write Zeros (1.1) */
 188                 uint16_t on_save:1;     /* Save/Select in Get/Set Feat (1.1) */
 189                 uint16_t on_reserve:1;  /* Reservations (1.1) */
 190                 uint16_t on_rsvd:10;
 191         } id_oncs;
 192         struct {                        /* Fused Operation Support */
 193                 uint16_t f_cmp_wr:1;    /* Compare and Write */
 194                 uint16_t f_rsvd:15;
 195         } id_fuses;
 196         struct {                        /* Format NVM Attributes */
 197                 uint8_t fn_format:1;    /* Format applies to all NS */
 198                 uint8_t fn_sec_erase:1; /* Secure Erase applies to all NS */
 199                 uint8_t fn_crypt_erase:1; /* Cryptographic Erase supported */
 200                 uint8_t fn_rsvd:5;
 201         } id_fna;
 202         struct {                        /* Volatile Write Cache */
 203                 uint8_t vwc_present:1;  /* Volatile Write Cache present */
 204                 uint8_t rsvd:7;
 205         } id_vwc;
 206         uint16_t id_awun;               /* Atomic Write Unit Normal */
 207         uint16_t id_awupf;              /* Atomic Write Unit Power Fail */
 208         struct {                        /* NVM Vendor Specific Command Conf */
 209                 uint8_t nv_spec:1;      /* use format from spec */
 210                 uint8_t nv_rsvd:7;
 211         } id_nvscc;
 212         uint8_t id_rsvd_nc_2;
 213         uint16_t id_acwu;               /* Atomic Compare & Write Unit (1.1) */
 214         uint16_t id_rsvd_nc_3;
 215         struct {                        /* SGL Support (1.1) */
 216                 uint16_t sgl_sup:1;     /* SGL Supported in NVM cmds (1.1) */
 217                 uint16_t sgl_rsvd1:15;
 218                 uint16_t sgl_bucket:1;  /* SGL Bit Bucket supported (1.1) */
 219                 uint16_t sgl_rsvd2:15;
 220         } id_sgls;
 221         uint8_t id_rsvd_nc_4[192 - 28];
 222
 223         /* I/O Command Set Attributes */
 224         uint8_t id_rsvd_ioc[1344];
 225
 226         /* Power State Descriptors */
 227         nvme_idctl_psd_t id_psd[32];
 228
 229         /* Vendor Specific */
 230         uint8_t id_vs[1024];
 231 } nvme_identify_ctrl_t;
 232
 233 /* NVMe Identify Namespace LBA Format */
 234 typedef struct {
 235         uint16_t lbaf_ms;               /* Metadata Size */
 236         uint8_t lbaf_lbads;             /* LBA Data Size */
 237         uint8_t lbaf_rp:2;              /* Relative Performance */
 238         uint8_t lbaf_rsvd1:6;
 239 } nvme_idns_lbaf_t;
 240
 241 /* NVMe Identify Namespace Data Structure */
 242 typedef struct {
 243         uint64_t id_nsize;              /* Namespace Size */
 244         uint64_t id_ncap;               /* Namespace Capacity */
 245         uint64_t id_nuse;               /* Namespace Utilization */
 246         struct {                        /* Namespace Features */
 247                 uint8_t f_thin:1;       /* Thin Provisioning */
 248                 uint8_t f_rsvd:7;
 249         } id_nsfeat;
 250         uint8_t id_nlbaf;               /* Number of LBA formats */
 251         struct {                        /* Formatted LBA size */
 252                 uint8_t lba_format:4;   /* LBA format */
 253                 uint8_t lba_extlba:1;   /* extended LBA (includes metadata) */
 254                 uint8_t lba_rsvd:3;
 255         } id_flbas;
 256         struct {                        /* Metadata Capabilities */
 257                 uint8_t mc_extlba:1;    /* extended LBA transfers */
 258                 uint8_t mc_separate:1;  /* separate metadata transfers */
 259                 uint8_t mc_rsvd:6;
 260         } id_mc;
 261         struct {                        /* Data Protection Capabilities */
 262                 uint8_t dp_type1:1;     /* Protection Information Type 1 */
 263                 uint8_t dp_type2:1;     /* Protection Information Type 2 */
 264                 uint8_t dp_type3:1;     /* Protection Information Type 3 */
 265                 uint8_t dp_first:1;     /* first 8 bytes of metadata */
 266                 uint8_t dp_last:1;      /* last 8 bytes of metadata */
 267                 uint8_t dp_rsvd:3;
 268         } id_dpc;
 269         struct {                        /* Data Protection Settings */
 270                 uint8_t dp_pinfo:3;     /* Protection Information enabled */
 271                 uint8_t dp_first:1;     /* first 8 bytes of metadata */
 272                 uint8_t dp_rsvd:4;
 273         } id_dps;
 274         struct {                        /* NS Multi-Path/Sharing Cap (1.1) */
 275                 uint8_t nm_shared:1;    /* NS is shared (1.1) */
 276                 uint8_t nm_rsvd:7;
 277         } id_nmic;
 278         struct {                        /* Reservation Capabilities (1.1) */
 279                 uint8_t rc_persist:1;   /* Persist Through Power Loss (1.1) */
 280                 uint8_t rc_wr_excl:1;   /* Write Exclusive (1.1) */
 281                 uint8_t rc_excl:1;      /* Exclusive Access (1.1) */
 282                 uint8_t rc_wr_excl_r:1; /* Wr Excl - Registrants Only (1.1) */
 283                 uint8_t rc_excl_r:1;    /* Excl Acc - Registrants Only (1.1) */
 284                 uint8_t rc_wr_excl_a:1; /* Wr Excl - All Registrants (1.1) */
 285                 uint8_t rc_excl_a:1;    /* Excl Acc - All Registrants (1.1) */
 286                 uint8_t rc_rsvd:1;
 287         } id_rescap;
 288         uint8_t id_rsvd1[120 - 32];
 289         uint8_t id_eui64[8];            /* IEEE Extended Unique Id (1.1) */
 290         nvme_idns_lbaf_t id_lbaf[16];   /* LBA Formats */
 291
 292         uint8_t id_rsvd2[192];
 293
 294         uint8_t id_vs[3712];            /* Vendor Specific */
 295 } nvme_identify_nsid_t;
 296
 297
 298 /*
 299  * NVMe completion queue entry status field
 300  */
 301 typedef struct {
 302         uint16_t sf_p:1;                /* Phase Tag */
 303         uint16_t sf_sc:8;               /* Status Code */
 304         uint16_t sf_sct:3;              /* Status Code Type */
 305         uint16_t sf_rsvd2:2;
 306         uint16_t sf_m:1;                /* More */
 307         uint16_t sf_dnr:1;              /* Do Not Retry */
 308 } nvme_cqe_sf_t;
 309
 310
 311 /*
 312  * NVMe Get Log Page
 313  */
 314 #define NVME_LOGPAGE_ERROR      0x1     /* Error Information */
 315 #define NVME_LOGPAGE_HEALTH     0x2     /* SMART/Health Information */
 316 #define NVME_LOGPAGE_FWSLOT     0x3     /* Firmware Slot Information */
 317
 318 typedef struct {
 319         uint64_t el_count;              /* Error Count */
 320         uint16_t el_sqid;               /* Submission Queue ID */
 321         uint16_t el_cid;                /* Command ID */
 322         nvme_cqe_sf_t el_sf;            /* Status Field */
 323         uint8_t el_byte;                /* Parameter Error Location byte */
 324         uint8_t el_bit:3;               /* Parameter Error Location bit */
 325         uint8_t el_rsvd1:5;
 326         uint64_t el_lba;                /* Logical Block Address */
 327         uint32_t el_nsid;               /* Namespace ID */
 328         uint8_t el_vendor;              /* Vendor Specific Information avail */
 329         uint8_t el_rsvd2[64 - 29];
 330 } nvme_error_log_entry_t;
 331
 332 typedef struct {
 333         uint64_t lo;
 334         uint64_t hi;
 335 } nvme_uint128_t;
 336
 337 typedef struct {
 338         struct {                        /* Critical Warning */
 339                 uint8_t cw_avail:1;     /* available space too low */
 340                 uint8_t cw_temp:1;      /* temperature too high */
 341                 uint8_t cw_reliab:1;    /* degraded reliability */
 342                 uint8_t cw_readonly:1;  /* media is read-only */
 343                 uint8_t cw_volatile:1;  /* volatile memory backup failed */
 344                 uint8_t cw_rsvd:3;
 345         } hl_crit_warn;
 346         uint16_t hl_temp;               /* Temperature */
 347         uint8_t hl_avail_spare;         /* Available Spare */
 348         uint8_t hl_avail_spare_thr;     /* Available Spare Threshold */
 349         uint8_t hl_used;                /* Percentage Used */
 350         uint8_t hl_rsvd1[32 - 6];
 351         nvme_uint128_t hl_data_read;    /* Data Units Read */
 352         nvme_uint128_t hl_data_write;   /* Data Units Written */
 353         nvme_uint128_t hl_host_read;    /* Host Read Commands */
 354         nvme_uint128_t hl_host_write;   /* Host Write Commands */
 355         nvme_uint128_t hl_ctrl_busy;    /* Controller Busy Time */
 356         nvme_uint128_t hl_power_cycles; /* Power Cycles */
 357         nvme_uint128_t hl_power_on_hours; /* Power On Hours */
 358         nvme_uint128_t hl_unsafe_shutdn; /* Unsafe Shutdowns */
 359         nvme_uint128_t hl_media_errors; /* Media Errors */
 360         nvme_uint128_t hl_errors_logged; /* Number of errors logged */
 361         uint8_t hl_rsvd2[512 - 192];
 362 } nvme_health_log_t;
 363
 364 typedef struct {
 365         uint8_t fw_afi:3;               /* Active Firmware Slot */
 366         uint8_t fw_rsvd1:5;
 367         uint8_t fw_rsvd2[7];
 368         char fw_frs[7][8];              /* Firmware Revision / Slot */
 369         uint8_t fw_rsvd3[512 - 64];
 370 } nvme_fwslot_log_t;
 371
 372
 373 /*
 374  * NVMe Format NVM
 375  */
 376 #define NVME_FRMT_SES_NONE      0
 377 #define NVME_FRMT_SES_USER      1
 378 #define NVME_FRMT_SES_CRYPTO    2
 379 #define NVME_FRMT_MAX_SES       2
 380
 381 #define NVME_FRMT_MAX_LBAF      15
 382
 383 typedef union {
 384         struct {
 385                 uint32_t fm_lbaf:4;             /* LBA Format */
 386                 uint32_t fm_ms:1;               /* Metadata Settings */
 387                 uint32_t fm_pi:3;               /* Protection Information */
 388                 uint32_t fm_pil:1;              /* Prot. Information Location */
 389                 uint32_t fm_ses:3;              /* Secure Erase Settings */
 390                 uint32_t fm_resvd:20;
 391         } b;
 392         uint32_t r;
 393 } nvme_format_nvm_t;
 394
 395
 396 /*
 397  * NVMe Get / Set Features
 398  */
 399 #define NVME_FEAT_ARBITRATION   0x1     /* Command Arbitration */
 400 #define NVME_FEAT_POWER_MGMT    0x2     /* Power Management */
 401 #define NVME_FEAT_LBA_RANGE     0x3     /* LBA Range Type */
 402 #define NVME_FEAT_TEMPERATURE   0x4     /* Temperature Threshold */
 403 #define NVME_FEAT_ERROR         0x5     /* Error Recovery */
 404 #define NVME_FEAT_WRITE_CACHE   0x6     /* Volatile Write Cache */
 405 #define NVME_FEAT_NQUEUES       0x7     /* Number of Queues */
 406 #define NVME_FEAT_INTR_COAL     0x8     /* Interrupt Coalescing */
 407 #define NVME_FEAT_INTR_VECT     0x9     /* Interrupt Vector Configuration */
 408 #define NVME_FEAT_WRITE_ATOM    0xa     /* Write Atomicity */
 409 #define NVME_FEAT_ASYNC_EVENT   0xb     /* Asynchronous Event Configuration */
 410 #define NVME_FEAT_AUTO_PST      0xc     /* Autonomous Power State Transition */
 411                                         /* (1.1) */
 412
 413 #define NVME_FEAT_PROGRESS      0x80    /* Software Progress Marker */
 414
 415 /* Arbitration Feature */
 416 typedef union {
 417         struct {
 418                 uint8_t arb_ab:3;       /* Arbitration Burst */
 419                 uint8_t arb_rsvd:5;
 420                 uint8_t arb_lpw;        /* Low Priority Weight */
 421                 uint8_t arb_mpw;        /* Medium Priority Weight */
 422                 uint8_t arb_hpw;        /* High Priority Weight */
 423         } b;
 424         uint32_t r;
 425 } nvme_arbitration_t;
 426
 427 /* Power Management Feature */
 428 typedef union {
 429         struct {
 430                 uint32_t pm_ps:5;       /* Power State */
 431                 uint32_t pm_rsvd:27;
 432         } b;
 433         uint32_t r;
 434 } nvme_power_mgmt_t;
 435
 436 /* LBA Range Type Feature */
 437 typedef union {
 438         struct {
 439                 uint32_t lr_num:6;      /* Number of LBA ranges */
 440                 uint32_t lr_rsvd:26;
 441         } b;
 442         uint32_t r;
 443 } nvme_lba_range_type_t;
 444
 445 typedef struct {
 446         uint8_t lr_type;                /* Type */
 447         struct {                        /* Attributes */
 448                 uint8_t lr_write:1;     /* may be overwritten */
 449                 uint8_t lr_hidden:1;    /* hidden from OS/EFI/BIOS */
 450                 uint8_t lr_rsvd1:6;
 451         } lr_attr;
 452         uint8_t lr_rsvd2[14];
 453         uint64_t lr_slba;               /* Starting LBA */
 454         uint64_t lr_nlb;                /* Number of Logical Blocks */
 455         uint8_t lr_guid[16];            /* Unique Identifier */
 456         uint8_t lr_rsvd3[16];
 457 } nvme_lba_range_t;
 458
 459 #define NVME_LBA_RANGE_BUFSIZE  4096
 460
 461 /* Temperature Threshold Feature */
 462 typedef union {
 463         struct {
 464                 uint16_t tt_tmpth;      /* Temperature Threshold */
 465                 uint16_t tt_rsvd;
 466         } b;
 467         uint32_t r;
 468 } nvme_temp_threshold_t;
 469
 470 /* Error Recovery Feature */
 471 typedef union {
 472         struct {
 473                 uint16_t er_tler;       /* Time-Limited Error Recovery */
 474                 uint16_t er_rsvd;
 475         } b;
 476         uint32_t r;
 477 } nvme_error_recovery_t;
 478
 479 /* Volatile Write Cache Feature */
 480 typedef union {
 481         struct {
 482                 uint32_t wc_wce:1;      /* Volatile Write Cache Enable */
 483                 uint32_t wc_rsvd:31;
 484         } b;
 485         uint32_t r;
 486 } nvme_write_cache_t;
 487
 488 /* Number of Queues Feature */
 489 typedef union {
 490         struct {
 491                 uint16_t nq_nsq;        /* Number of Submission Queues */
 492                 uint16_t nq_ncq;        /* Number of Completion Queues */
 493         } b;
 494         uint32_t r;
 495 } nvme_nqueues_t;
 496
 497 /* Interrupt Coalescing Feature */
 498 typedef union {
 499         struct {
 500                 uint8_t ic_thr;         /* Aggregation Threshold */
 501                 uint8_t ic_time;        /* Aggregation Time */
 502                 uint16_t ic_rsvd;
 503         } b;
 504         uint32_t r;
 505 } nvme_intr_coal_t;
 506
 507 /* Interrupt Configuration Features */
 508 typedef union {
 509         struct {
 510                 uint16_t iv_iv;         /* Interrupt Vector */
 511                 uint16_t iv_cd:1;       /* Coalescing Disable */
 512                 uint16_t iv_rsvd:15;
 513         } b;
 514         uint32_t r;
 515 } nvme_intr_vect_t;
 516
 517 /* Write Atomicity Feature */
 518 typedef union {
 519         struct {
 520                 uint32_t wa_dn:1;       /* Disable Normal */
 521                 uint32_t wa_rsvd:31;
 522         } b;
 523         uint32_t r;
 524 } nvme_write_atomicity_t;
 525
 526 /* Asynchronous Event Configuration Feature */
 527 typedef union {
 528         struct {
 529                 uint8_t aec_avail:1;    /* available space too low */
 530                 uint8_t aec_temp:1;     /* temperature too high */
 531                 uint8_t aec_reliab:1;   /* degraded reliability */
 532                 uint8_t aec_readonly:1; /* media is read-only */
 533                 uint8_t aec_volatile:1; /* volatile memory backup failed */
 534                 uint8_t aec_rsvd1:3;
 535                 uint8_t aec_rsvd2[3];
 536         } b;
 537         uint32_t r;
 538 } nvme_async_event_conf_t;
 539
 540 /* Autonomous Power State Transition Feature (1.1) */
 541 typedef union {
 542         struct {
 543                 uint8_t apst_apste:1;   /* APST enabled */
 544                 uint8_t apst_rsvd:7;
 545         } b;
 546         uint8_t r;
 547 } nvme_auto_power_state_trans_t;
 548
 549 typedef struct {
 550         uint32_t apst_rsvd1:3;
 551         uint32_t apst_itps:5;   /* Idle Transition Power State */
 552         uint32_t apst_itpt:24;  /* Idle Time Prior to Transition */
 553         uint32_t apst_rsvd2;
 554 } nvme_auto_power_state_t;
 555
 556 #define NVME_AUTO_PST_BUFSIZE   256
 557
 558 /* Software Progress Marker Feature */
 559 typedef union {
 560         struct {
 561                 uint8_t spm_pbslc;      /* Pre-Boot Software Load Count */
 562                 uint8_t spm_rsvd[3];
 563         } b;
 564         uint32_t r;
 565 } nvme_software_progress_marker_t;
 566
 567 #pragma pack() /* pack(1) */
 568
 569
 570 #ifdef __cplusplus
 571 }
 572 #endif
 573
 574 #endif /* _SYS_NVME_H */