components/openindiana/drm/drm/sys/drm/drm_mode.h

   1 /* BEGIN CSTYLED */
   2
   3 /*
   4  * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
   5  */
   6
   7 /*
   8  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
   9  * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
  10  * Copyright (c) 2008 Red Hat Inc.
  11  * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
  12  * Copyright (c) 2007-2008, 2013, Intel Corporation
  13  *
  14  * Permission is hereby granted, free of charge, to any person obtaining a
  15  * copy of this software and associated documentation files (the "Software"),
  16  * to deal in the Software without restriction, including without limitation
  17  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  18  * and/or sell copies of the Software, and to permit persons to whom the
  19  * Software is furnished to do so, subject to the following conditions:
  20  *
  21  * The above copyright notice and this permission notice shall be included in
  22  * all copies or substantial portions of the Software.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  25  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  26  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  27  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  28  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  29  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  30  * IN THE SOFTWARE.
  31  */
  32
  33 #ifndef _DRM_MODE_H
  34 #define _DRM_MODE_H
  35 #include "drm.h"
  36 #define DRM_DISPLAY_INFO_LEN    32
  37 #define DRM_CONNECTOR_NAME_LEN  32
  38 #define DRM_DISPLAY_MODE_LEN    32
  39 #define DRM_PROP_NAME_LEN       32
  40
  41 #define DRM_MODE_TYPE_BUILTIN   (1<<0)
  42 #define DRM_MODE_TYPE_CLOCK_C   ((1<<1) | DRM_MODE_TYPE_BUILTIN)
  43 #define DRM_MODE_TYPE_CRTC_C    ((1<<2) | DRM_MODE_TYPE_BUILTIN)
  44 #define DRM_MODE_TYPE_PREFERRED (1<<3)
  45 #define DRM_MODE_TYPE_DEFAULT   (1<<4)
  46 #define DRM_MODE_TYPE_USERDEF   (1<<5)
  47 #define DRM_MODE_TYPE_DRIVER    (1<<6)
  48
  49 /* Video mode flags */
  50 /* bit compatible with the xorg definitions. */
  51 #define DRM_MODE_FLAG_PHSYNC    (1<<0)
  52 #define DRM_MODE_FLAG_NHSYNC    (1<<1)
  53 #define DRM_MODE_FLAG_PVSYNC    (1<<2)
  54 #define DRM_MODE_FLAG_NVSYNC    (1<<3)
  55 #define DRM_MODE_FLAG_INTERLACE (1<<4)
  56 #define DRM_MODE_FLAG_DBLSCAN   (1<<5)
  57 #define DRM_MODE_FLAG_CSYNC     (1<<6)
  58 #define DRM_MODE_FLAG_PCSYNC    (1<<7)
  59 #define DRM_MODE_FLAG_NCSYNC    (1<<8)
  60 #define DRM_MODE_FLAG_HSKEW     (1<<9) /* hskew provided */
  61 #define DRM_MODE_FLAG_BCAST     (1<<10)
  62 #define DRM_MODE_FLAG_PIXMUX    (1<<11)
  63 #define DRM_MODE_FLAG_DBLCLK    (1<<12)
  64 #define DRM_MODE_FLAG_CLKDIV2   (1<<13)
  65
  66 /* DPMS flags */
  67 /* bit compatible with the xorg definitions. */
  68 #define DRM_MODE_DPMS_ON        0
  69 #define DRM_MODE_DPMS_STANDBY   1
  70 #define DRM_MODE_DPMS_SUSPEND   2
  71 #define DRM_MODE_DPMS_OFF       3
  72
  73 /* Scaling mode options */
  74 #define DRM_MODE_SCALE_NONE             0 /* Unmodified timing (display or
  75                                              software can still scale) */
  76 #define DRM_MODE_SCALE_FULLSCREEN       1 /* Full screen, ignore aspect */
  77 #define DRM_MODE_SCALE_CENTER           2 /* Centered, no scaling */
  78 #define DRM_MODE_SCALE_ASPECT           3 /* Full screen, preserve aspect */
  79
  80 /* Dithering mode options */
  81 #define DRM_MODE_DITHERING_OFF  0
  82 #define DRM_MODE_DITHERING_ON   1
  83 #define DRM_MODE_DITHERING_AUTO 2
  84
  85 /* Dirty info options */
  86 #define DRM_MODE_DIRTY_OFF      0
  87 #define DRM_MODE_DIRTY_ON       1
  88 #define DRM_MODE_DIRTY_ANNOTATE 2
  89
  90 struct drm_mode_modeinfo {
  91         __u32 clock;
  92         __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
  93         __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
  94
  95         __u32 vrefresh;
  96
  97         __u32 flags;
  98         __u32 type;
  99         char name[DRM_DISPLAY_MODE_LEN];
 100 };
 101
 102 struct drm_mode_card_res {
 103         __u64 fb_id_ptr;
 104         __u64 crtc_id_ptr;
 105         __u64 connector_id_ptr;
 106         __u64 encoder_id_ptr;
 107         __u32 count_fbs;
 108         __u32 count_crtcs;
 109         __u32 count_connectors;
 110         __u32 count_encoders;
 111         __u32 min_width, max_width;
 112         __u32 min_height, max_height;
 113 };
 114
 115 struct drm_mode_crtc {
 116         __u64 set_connectors_ptr;
 117         __u32 count_connectors;
 118
 119         __u32 crtc_id; /**< Id */
 120         __u32 fb_id; /**< Id of framebuffer */
 121
 122         __u32 x, y; /**< Position on the frameuffer */
 123
 124         __u32 gamma_size;
 125         __u32 mode_valid;
 126         struct drm_mode_modeinfo mode;
 127 };
 128
 129 #define DRM_MODE_PRESENT_TOP_FIELD      (1<<0)
 130 #define DRM_MODE_PRESENT_BOTTOM_FIELD   (1<<1)
 131
 132 /* Planes blend with or override other bits on the CRTC */
 133 struct drm_mode_set_plane {
 134         __u32 plane_id;
 135         __u32 crtc_id;
 136         __u32 fb_id; /* fb object contains surface format type */
 137         __u32 flags; /* see above flags */
 138
 139         /* Signed dest location allows it to be partially off screen */
 140         __s32 crtc_x, crtc_y;
 141         __u32 crtc_w, crtc_h;
 142
 143         /* Source values are 16.16 fixed point */
 144         __u32 src_x, src_y;
 145         __u32 src_h, src_w;
 146 };
 147
 148 struct drm_mode_get_plane {
 149         __u32 plane_id;
 150
 151         __u32 crtc_id;
 152         __u32 fb_id;
 153
 154         __u32 possible_crtcs;
 155         __u32 gamma_size;
 156
 157         __u32 count_format_types;
 158         __u64 format_type_ptr;
 159 };
 160
 161 struct drm_mode_get_plane_res {
 162         __u64 plane_id_ptr;
 163         __u32 count_planes;
 164 };
 165
 166 #define DRM_MODE_ENCODER_NONE   0
 167 #define DRM_MODE_ENCODER_DAC    1
 168 #define DRM_MODE_ENCODER_TMDS   2
 169 #define DRM_MODE_ENCODER_LVDS   3
 170 #define DRM_MODE_ENCODER_TVDAC  4
 171 #define DRM_MODE_ENCODER_VIRTUAL 5
 172
 173 struct drm_mode_get_encoder {
 174         __u32 encoder_id;
 175         __u32 encoder_type;
 176
 177         __u32 crtc_id; /**< Id of crtc */
 178
 179         __u32 possible_crtcs;
 180         __u32 possible_clones;
 181 };
 182
 183 /* This is for connectors with multiple signal types. */
 184 /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
 185 #define DRM_MODE_SUBCONNECTOR_Automatic 0
 186 #define DRM_MODE_SUBCONNECTOR_Unknown   0
 187 #define DRM_MODE_SUBCONNECTOR_DVID      3
 188 #define DRM_MODE_SUBCONNECTOR_DVIA      4
 189 #define DRM_MODE_SUBCONNECTOR_Composite 5
 190 #define DRM_MODE_SUBCONNECTOR_SVIDEO    6
 191 #define DRM_MODE_SUBCONNECTOR_Component 8
 192 #define DRM_MODE_SUBCONNECTOR_SCART     9
 193
 194 #define DRM_MODE_CONNECTOR_Unknown      0
 195 #define DRM_MODE_CONNECTOR_VGA          1
 196 #define DRM_MODE_CONNECTOR_DVII         2
 197 #define DRM_MODE_CONNECTOR_DVID         3
 198 #define DRM_MODE_CONNECTOR_DVIA         4
 199 #define DRM_MODE_CONNECTOR_Composite    5
 200 #define DRM_MODE_CONNECTOR_SVIDEO       6
 201 #define DRM_MODE_CONNECTOR_LVDS         7
 202 #define DRM_MODE_CONNECTOR_Component    8
 203 #define DRM_MODE_CONNECTOR_9PinDIN      9
 204 #define DRM_MODE_CONNECTOR_DisplayPort  10
 205 #define DRM_MODE_CONNECTOR_HDMIA        11
 206 #define DRM_MODE_CONNECTOR_HDMIB        12
 207 #define DRM_MODE_CONNECTOR_TV           13
 208 #define DRM_MODE_CONNECTOR_eDP          14
 209 #define DRM_MODE_CONNECTOR_VIRTUAL      15
 210
 211 struct drm_mode_get_connector {
 212
 213         __u64 encoders_ptr;
 214         __u64 modes_ptr;
 215         __u64 props_ptr;
 216         __u64 prop_values_ptr;
 217
 218         __u32 count_modes;
 219         __u32 count_props;
 220         __u32 count_encoders;
 221
 222         __u32 encoder_id; /**< Current Encoder */
 223         __u32 connector_id; /**< Id */
 224         __u32 connector_type;
 225         __u32 connector_type_id;
 226
 227         __u32 connection;
 228         __u32 mm_width, mm_height; /**< HxW in millimeters */
 229         __u32 subpixel;
 230 };
 231
 232 #define DRM_MODE_PROP_PENDING   (1<<0)
 233 #define DRM_MODE_PROP_RANGE     (1<<1)
 234 #define DRM_MODE_PROP_IMMUTABLE (1<<2)
 235 #define DRM_MODE_PROP_ENUM      (1<<3) /* enumerated type with text strings */
 236 #define DRM_MODE_PROP_BLOB      (1<<4)
 237 #define DRM_MODE_PROP_BITMASK   (1<<5) /* bitmask of enumerated types */
 238
 239 struct drm_mode_property_enum {
 240         __u64 value;
 241         char name[DRM_PROP_NAME_LEN];
 242 };
 243
 244 struct drm_mode_get_property {
 245         __u64 values_ptr; /* values and blob lengths */
 246         __u64 enum_blob_ptr; /* enum and blob id ptrs */
 247
 248         __u32 prop_id;
 249         __u32 flags;
 250         char name[DRM_PROP_NAME_LEN];
 251
 252         __u32 count_values;
 253         __u32 count_enum_blobs;
 254 };
 255
 256 struct drm_mode_connector_set_property {
 257         __u64 value;
 258         __u32 prop_id;
 259         __u32 connector_id;
 260 };
 261
 262 struct drm_mode_obj_get_properties {
 263         __u64 props_ptr;
 264         __u64 prop_values_ptr;
 265         __u32 count_props;
 266         __u32 obj_id;
 267         __u32 obj_type;
 268 };
 269
 270 struct drm_mode_obj_set_property {
 271         __u64 value;
 272         __u32 prop_id;
 273         __u32 obj_id;
 274         __u32 obj_type;
 275 };
 276
 277 struct drm_mode_get_blob {
 278         __u32 blob_id;
 279         __u32 length;
 280         __u64 data;
 281 };
 282
 283 struct drm_mode_fb_cmd {
 284         __u32 fb_id;
 285         __u32 width, height;
 286         __u32 pitch;
 287         __u32 bpp;
 288         __u32 depth;
 289         /* driver specific handle */
 290         __u32 handle;
 291 };
 292
 293 #define DRM_MODE_FB_INTERLACED  (1<<0) /* for interlaced framebuffers */
 294
 295 struct drm_mode_fb_cmd2 {
 296         __u32 fb_id;
 297         __u32 width, height;
 298         __u32 pixel_format; /* fourcc code from drm_fourcc.h */
 299         __u32 flags; /* see above flags */
 300
 301         /*
 302          * In case of planar formats, this ioctl allows up to 4
 303          * buffer objects with offets and pitches per plane.
 304          * The pitch and offset order is dictated by the fourcc,
 305          * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
 306          *
 307          *   YUV 4:2:0 image with a plane of 8 bit Y samples
 308          *   followed by an interleaved U/V plane containing
 309          *   8 bit 2x2 subsampled colour difference samples.
 310          *
 311          * So it would consist of Y as offset[0] and UV as
 312          * offeset[1].  Note that offset[0] will generally
 313          * be 0.
 314          */
 315         __u32 handles[4];
 316         __u32 pitches[4]; /* pitch for each plane */
 317         __u32 offsets[4]; /* offset of each plane */
 318 };
 319
 320 #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
 321 #define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
 322 #define DRM_MODE_FB_DIRTY_FLAGS         0x03
 323
 324 #define DRM_MODE_FB_DIRTY_MAX_CLIPS     256
 325
 326 /*
 327  * Mark a region of a framebuffer as dirty.
 328  *
 329  * Some hardware does not automatically update display contents
 330  * as a hardware or software draw to a framebuffer. This ioctl
 331  * allows userspace to tell the kernel and the hardware what
 332  * regions of the framebuffer have changed.
 333  *
 334  * The kernel or hardware is free to update more then just the
 335  * region specified by the clip rects. The kernel or hardware
 336  * may also delay and/or coalesce several calls to dirty into a
 337  * single update.
 338  *
 339  * Userspace may annotate the updates, the annotates are a
 340  * promise made by the caller that the change is either a copy
 341  * of pixels or a fill of a single color in the region specified.
 342  *
 343  * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
 344  * the number of updated regions are half of num_clips given,
 345  * where the clip rects are paired in src and dst. The width and
 346  * height of each one of the pairs must match.
 347  *
 348  * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
 349  * promises that the region specified of the clip rects is filled
 350  * completely with a single color as given in the color argument.
 351  */
 352
 353 struct drm_mode_fb_dirty_cmd {
 354         __u32 fb_id;
 355         __u32 flags;
 356         __u32 color;
 357         __u32 num_clips;
 358         __u64 clips_ptr;
 359 };
 360
 361 struct drm_mode_mode_cmd {
 362         __u32 connector_id;
 363         struct drm_mode_modeinfo mode;
 364 };
 365
 366 #define DRM_MODE_CURSOR_BO      0x01
 367 #define DRM_MODE_CURSOR_MOVE    0x02
 368 #define DRM_MODE_CURSOR_FLAGS   0x03
 369
 370 /*
 371  * depending on the value in flags diffrent members are used.
 372  *
 373  * CURSOR_BO uses
 374  *    crtc
 375  *    width
 376  *    height
 377  *    handle - if 0 turns the cursor of
 378  *
 379  * CURSOR_MOVE uses
 380  *    crtc
 381  *    x
 382  *    y
 383  */
 384 struct drm_mode_cursor {
 385         __u32 flags;
 386         __u32 crtc_id;
 387         __s32 x;
 388         __s32 y;
 389         __u32 width;
 390         __u32 height;
 391         /* driver specific handle */
 392         __u32 handle;
 393 };
 394
 395 struct drm_mode_cursor2 {
 396         __u32 flags;
 397         __u32 crtc_id;
 398         __s32 x;
 399         __s32 y;
 400         __u32 width;
 401         __u32 height;
 402         /* driver specific handle */
 403         __u32 handle;
 404         __s32 hot_x;
 405         __s32 hot_y;
 406 };
 407
 408 struct drm_mode_crtc_lut {
 409         __u32 crtc_id;
 410         __u32 gamma_size;
 411
 412         /* pointers to arrays */
 413         __u64 red;
 414         __u64 green;
 415         __u64 blue;
 416 };
 417
 418 #define DRM_MODE_PAGE_FLIP_EVENT 0x01
 419 #define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
 420
 421 /*
 422  * Request a page flip on the specified crtc.
 423  *
 424  * This ioctl will ask KMS to schedule a page flip for the specified
 425  * crtc.  Once any pending rendering targeting the specified fb (as of
 426  * ioctl time) has completed, the crtc will be reprogrammed to display
 427  * that fb after the next vertical refresh.  The ioctl returns
 428  * immediately, but subsequent rendering to the current fb will block
 429  * in the execbuffer ioctl until the page flip happens.  If a page
 430  * flip is already pending as the ioctl is called, EBUSY will be
 431  * returned.
 432  *
 433  * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
 434  * request that drm sends back a vblank event (see drm.h: struct
 435  * drm_event_vblank) when the page flip is done.  The user_data field
 436  * passed in with this ioctl will be returned as the user_data field
 437  * in the vblank event struct.
 438  *
 439  * The reserved field must be zero until we figure out something
 440  * clever to use it for.
 441  */
 442
 443 struct drm_mode_crtc_page_flip {
 444         __u32 crtc_id;
 445         __u32 fb_id;
 446         __u32 flags;
 447         __u32 reserved;
 448         __u64 user_data;
 449 };
 450
 451 /* create a dumb scanout buffer */
 452 struct drm_mode_create_dumb {
 453         uint32_t height;
 454         uint32_t width;
 455         uint32_t bpp;
 456         uint32_t flags;
 457         /* handle, pitch, size will be returned */
 458         uint32_t handle;
 459         uint32_t pitch;
 460         uint64_t size;
 461 };
 462
 463 /* set up for mmap of a dumb scanout buffer */
 464 struct drm_mode_map_dumb {
 465         /** Handle for the object being mapped. */
 466         __u32 handle;
 467         __u32 pad;
 468         /**
 469          * Fake offset to use for subsequent mmap call
 470          *
 471          * This is a fixed-size type for 32/64 compatibility.
 472          */
 473         __u64 offset;
 474 };
 475
 476 struct drm_mode_destroy_dumb {
 477         uint32_t handle;
 478 };
 479
 480 #endif /* _DRM_MODE_H */