libc/sysdeps/linux/nds32/fpu_control.h

   1 /*
   2  * Copyright (C) 2016-2017 Andes Technology, Inc.
   3  * Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
   4  */
   5
   6 #ifndef _FPU_CONTROL_H
   7
   8 #ifdef  __NDS32_ABI_2FP_PLUS__
   9 /*
  10  * Andes Floating-Point Control Status Register
  11  * 31-20 -> Reserved
  12  * 19    -> RIT (RO)
  13  * 18    -> DNIT(RO)
  14  * 17    -> IEXT(RO)
  15  * 16    -> UDFT(RO)
  16  * 15    -> OVFT(RO)
  17  * 14    -> DBZT(RO)
  18  * 13    -> IVOT(RO)
  19  * 12    -> DNZ(RW),Denormalized flush-to-Zero mode.
  20  * 11    -> IEXE(RW),IEEE Ineaxct (IEX) exception trapping enable.
  21  * 10    -> UDFE(RW),IEEE Underflow (UDF) exception trapping enable.
  22  * 9     -> OVFE(RW),IEEE Overflow (OVF) exception trapping enable.
  23  * 8     -> DBZE(RW),IEEE Divide by Zero (DBZ) exception trapping enable.
  24  * 7     -> IVOE(RW),IEEE Invalid Operation (IVO) exception trapping enable.
  25  * 6     -> IEX(RW),IEEE Inexact (IEX) cumulative exception flag.
  26  * 5     -> UDF(RW),IEEE Underflow (UDF) cumulative exception flag.
  27  * 4     -> OVF(RW),IEEE Overflow (OVF) cumulative exception flag.
  28  * 3     -> DBZ(RW),IEEE Divide by Zero (DBZ) cumulative exception flag.
  29  * 2     -> IVO(RW),IEEE Invalid Operation (IVO) cumulative exception flag.
  30  * 1-0   -> Rounding modes.
  31  *
  32  * Rounding modes.
  33  * 00 - rounding to nearest (RN)
  34  * 01 - rounding (up) toward plus infinity (RP)
  35  * 10 - rounding (down)toward minus infinity (RM)
  36  * 11 - rounding toward zero (RZ)
  37  *
  38  */
  39
  40
  41 /* masking of interrupts */
  42 #define _FPU_MASK_IEX   0x0800  /* Invalid operation */
  43 #define _FPU_MASK_UDF   0x0400  /* Underflow         */
  44 #define _FPU_MASK_OVF   0x0200  /* Overflow          */
  45 #define _FPU_MASK_DBZ   0x0100  /* Division by zero  */
  46 #define _FPU_MASK_IVO   0x0080  /* Invalid operation */
  47
  48 /*Reserved and read-only bits*/
  49 #define _FPU_RESERVED   0xffffe000
  50 #define _FPU_DEFAULT    0x00000000
  51
  52 /* Default + exceptions enabled. */
  53 #define _FPU_IEEE       (_FPU_DEFAULT | 0x00000f80)
  54
  55 /* Type of the control word.  */
  56 typedef unsigned int fpu_control_t;
  57
  58 /* Macros for accessing the hardware control word.  */
  59 /* This is fmrx %0, fpscr.  */
  60 #define _FPU_GETCW(cw) \
  61   __asm__ __volatile__ ("fmfcsr\t %0\n\t" : "=r" (cw))
  62 /* This is fmxr fpscr, %0.  */
  63 #define _FPU_SETCW(cw) \
  64   __asm__ __volatile__ ("fmtcsr\t %0\n\t": : "r" (cw))
  65
  66 /* Default control word set at startup.  */
  67 extern fpu_control_t __fpu_control;
  68 #else
  69 #define _FPU_GETCW(cw) (cw) = 0
  70 #define _FPU_SETCW(cw) (void) (cw)
  71 #define _FPU_RESERVED 0xffffffff
  72 #define _FPU_DEFAULT  0x00000000
  73 typedef unsigned int fpu_control_t;
  74 extern fpu_control_t __fpu_control;
  75
  76 #endif //__NDS32_ABI_2FP_PLUS__
  77 #endif //_FPU_CONTROL_H