2 * Copyright (C) 2016-2017 Andes Technology, Inc.
3 * Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
7 setjmp/longjmp for nds32.
8 r0 - r5 are for paramter passing - no need to save
9 r6 - r14 are callee saved - needs to save
10 r15 is temp register for assembler - no need to save
11 r16 - r25 are caller saved - no need to save
12 r26 - r27 are temp registers for OS - no need to save
13 r28 is fp - need to save
14 r29 is gp - need to save
15 r30 is ra - need to save
16 r31 is sp - need to save
17 so we need to save r6 - r14 and r28 - r31
18 The jmpbuf looks like this:
32 #ifdef NDS32_ABI_2FP_PLUS
34 (callee-saved FPU regs)
36 reserved(for 8-byte align if needed)
42 #include <bits/setjmp.h>
45 /* __longjmp (env[0].__jmpbuf, val ?: 1); */
48 lmw.bim $r6, [$r0], $r14, #0xf
50 #ifdef NDS32_ABI_2FP_PLUS
51 lwi.bi $r20, [$r0], #4 /* Load $fpcfg.freg to $r20. */
53 /* Case switch for $r20 as $fpcfg.freg. */
54 beqz $r20, .LCFG0 /* Branch if $fpcfg.freg = 0b00. */
55 xori $r15, $r20, #0b10
56 beqz $r15, .LCFG2 /* Branch if $fpcfg.freg = 0b10. */
57 srli $r20, $r20, #0b01
58 beqz $r20, .LCFG1 /* Branch if $fpcfg.freg = 0b01. */
59 /* Fall-through if $fpcfg.freg = 0b11. */
61 fldi.bi $fd31, [$r0], #8
62 fldi.bi $fd30, [$r0], #8
63 fldi.bi $fd29, [$r0], #8
64 fldi.bi $fd28, [$r0], #8
65 fldi.bi $fd27, [$r0], #8
66 fldi.bi $fd26, [$r0], #8
67 fldi.bi $fd25, [$r0], #8
68 fldi.bi $fd24, [$r0], #8
70 fldi.bi $fd10, [$r0], #8
71 fldi.bi $fd9, [$r0], #8
72 fldi.bi $fd8, [$r0], #8
74 fldi.bi $fd7, [$r0], #8
75 fldi.bi $fd6, [$r0], #8
76 fldi.bi $fd5, [$r0], #8
77 fldi.bi $fd4, [$r0], #8
79 fldi.bi $fd3, [$r0], #8
80 #endif /* NDS32_ABI_2FP_PLUS */
83 ! return error code; make sure error code is not 0
90 libc_hidden_def(__longjmp)