include/configs/quantum.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  * changes for 16M board
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #undef CONFIG_MPC860
  38 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  39 #define CONFIG_RPXLITE          1       /* QUANTUM is the RPXlite clone */
  40 #define CONFIG_RMU              1   /* The QUNATUM is based on our RMU */
  41
  42 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  43 #undef  CONFIG_8xx_CONS_SMC2
  44 #undef  CONFIG_8xx_CONS_NONE
  45 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  46 #if 0
  47 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  48 #else
  49 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  50 #endif
  51
  52 /* default developmenmt environment */
  53
  54 #define CONFIG_ETHADDR 00:0B:17:00:00:00
  55
  56 #define CONFIG_IPADDR  10.10.69.10
  57 #define CONFIG_SERVERIP 10.10.69.49
  58 #define CONFIG_NETMASK  255.255.255.0
  59 #define CONFIG_HOSTNAME QUANTUM
  60 #define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
  61
  62 #define CONFIG_BOOTARGS  "root=/dev/ram rw"
  63
  64 #define CONFIG_BOOTCOMMAND "bootm ff000000"
  65
  66 #define CONFIG_EXTRA_ENV_SETTINGS \
  67     "serial#=12345\0"           \
  68         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"    \
  69         "ramargs=setenv bootargs root=/dev/ram rw\0" \
  70     "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
  71
  72 /*
  73  * Select the more full-featured memory test (Barr embedded systems)
  74  */
  75 #define CFG_ALT_MEMTEST
  76
  77 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  78 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  79
  80
  81 /* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
  82 #define CONFIG_RTC_M48T35A 1
  83
  84 #if 0
  85 #define CONFIG_WATCHDOG 1               /* watchdog enabled             */
  86 #else
  87 #undef CONFIG_WATCHDOG
  88 #endif
  89
  90 /*  NVRAM and RTC */
  91 #define CFG_NVRAM_BASE_ADDR 0xFA000000
  92 #define CFG_NVRAM_SIZE 2048
  93
  94
  95 /*
  96  * Command line configuration.
  97  */
  98 #include <config_cmd_default.h>
  99
 100 #define CONFIG_CMD_DATE
 101 #define CONFIG_CMD_DHCP
 102 #define CONFIG_CMD_NFS
 103 #define CONFIG_CMD_PING
 104 #define CONFIG_CMD_REGINFO
 105 #define CONFIG_CMD_SNTP
 106
 107
 108 /*
 109  * BOOTP options
 110  */
 111 #define CONFIG_BOOTP_SUBNETMASK
 112 #define CONFIG_BOOTP_GATEWAY
 113 #define CONFIG_BOOTP_HOSTNAME
 114 #define CONFIG_BOOTP_BOOTPATH
 115 #define CONFIG_BOOTP_BOOTFILESIZE
 116
 117
 118 #define CONFIG_AUTOBOOT_KEYED   /* Enable password protection */
 119 #define CONFIG_AUTOBOOT_PROMPT          "\nEnter password - autoboot in %d sec...\n"
 120 #define CONFIG_AUTOBOOT_DELAY_STR       "system"
 121 /*
 122  * Miscellaneous configurable options
 123  */
 124 #define CFG_LONGHELP                    /* undef to save memory         */
 125 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 126 #if defined(CONFIG_CMD_KGDB)
 127 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 128 #else
 129 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 130 #endif
 131 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 132 #define CFG_MAXARGS     16              /* max number of command args   */
 133 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 134
 135 #define CFG_MEMTEST_START       0x00040000      /* memtest works on     */
 136 #define CFG_MEMTEST_END         0x01f00000      /* 256K ... 15 MB in DRAM       */
 137
 138 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 139
 140 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 141
 142 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 143
 144 /*
 145  * Low Level Configuration Settings
 146  * (address mappings, register initial values, etc.)
 147  * You should know what you are doing if you make changes here.
 148  */
 149 /*-----------------------------------------------------------------------
 150  * Internal Memory Mapped Register
 151  */
 152 #define CFG_IMMR                0xFA200000
 153
 154 /*-----------------------------------------------------------------------
 155  * Definitions for initial stack pointer and data area (in DPRAM)
 156  */
 157 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 158 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 159 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 160 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 161 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 162
 163 /*-----------------------------------------------------------------------
 164  * Start addresses for the final memory configuration
 165  * (Set up by the startup code)
 166  * Please note that CFG_SDRAM_BASE _must_ start at 0
 167  */
 168 #define CFG_SDRAM_BASE          0x00000000
 169 #define CFG_FLASH_BASE  0xFF000000
 170
 171 #if 1
 172     #define CFG_FLASH_CFI_DRIVER
 173 #else
 174     #undef CFG_FLASH_CFI_DRIVER
 175 #endif
 176
 177
 178 #ifdef CFG_FLASH_CFI_DRIVER
 179     #define CFG_FLASH_CFI 1
 180     #undef CFG_FLASH_USE_BUFFER_WRITE
 181     #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
 182 #endif
 183
 184 /*%%% #define CFG_FLASH_BASE            0xFFF00000 */
 185 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
 186 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 187 #else
 188 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
 189 #endif
 190 #define CFG_MONITOR_BASE        0xFFF00000
 191 /*%%% #define CFG_MONITOR_BASE  CFG_FLASH_BASE */
 192 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 193
 194 /*
 195  * For booting Linux, the board info and command line data
 196  * have to be in the first 8 MB of memory, since this is
 197  * the maximum mapped by the Linux kernel during initialization.
 198  */
 199 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 200
 201 /*-----------------------------------------------------------------------
 202  * FLASH organization
 203  */
 204 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 205 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip */
 206
 207 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 208 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 209
 210 #define CFG_ENV_IS_IN_FLASH     1
 211 #define CFG_ENV_OFFSET      0x00F40000  /*   Offset   of Environment Sector     absolute address 0xfff40000*/
 212 #define CFG_ENV_SECT_SIZE       0x40000 /* Total Size of Environment Sector     */
 213 #define CFG_ENV_SIZE            CFG_ENV_SECT_SIZE
 214 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + CFG_ENV_OFFSET)
 215
 216 /* Address and size of Redundant Environment Sector     */
 217 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 218 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 219
 220 /* FPGA */
 221 #define CONFIG_MISC_INIT_R
 222 #define CFG_FPGA_SPARTAN2
 223 #define CFG_FPGA_PROG_FEEDBACK
 224
 225
 226 /*-----------------------------------------------------------------------
 227  * Reset address
 228  */
 229 #define CFG_RESET_ADDRESS       ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
 230
 231 /*-----------------------------------------------------------------------
 232  * Cache Configuration
 233  */
 234 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 235 #if defined(CONFIG_CMD_KGDB)
 236 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 237 #endif
 238
 239 /*-----------------------------------------------------------------------
 240  * SYPCR - System Protection Control                            11-9
 241  * SYPCR can only be written once after reset!
 242  *-----------------------------------------------------------------------
 243  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 244  */
 245 #if defined(CONFIG_WATCHDOG)
 246 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 247                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 248 #else
 249 #define CFG_SYPCR       (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 250 #endif
 251
 252 /*-----------------------------------------------------------------------
 253  * SIUMCR - SIU Module Configuration                            11-6
 254  *-----------------------------------------------------------------------
 255  * PCMCIA config., multi-function pin tri-state
 256  */
 257 #define CFG_SIUMCR      (SIUMCR_MLRC10)
 258
 259 /*-----------------------------------------------------------------------
 260  * TBSCR - Time Base Status and Control                         11-26
 261  *-----------------------------------------------------------------------
 262  * Clear Reference Interrupt Status, Timebase freezing enabled
 263  */
 264 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 265
 266 /*-----------------------------------------------------------------------
 267  * RTCSC - Real-Time Clock Status and Control Register          11-27
 268  *-----------------------------------------------------------------------
 269  */
 270 /*%%%#define CFG_RTCSC  (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 271 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_RTE)
 272
 273 /*-----------------------------------------------------------------------
 274  * PISCR - Periodic Interrupt Status and Control                11-31
 275  *-----------------------------------------------------------------------
 276  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 277  */
 278 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
 279
 280 /*-----------------------------------------------------------------------
 281  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 282  *-----------------------------------------------------------------------
 283  * Reset PLL lock status sticky bit, timer expired status bit and timer
 284  * interrupt status bit
 285  *
 286  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 287  */
 288 /* up to 50 MHz we use a 1:1 clock */
 289 #define CFG_PLPRCR      ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 290
 291 /*-----------------------------------------------------------------------
 292  * SCCR - System Clock and reset Control Register               15-27
 293  *-----------------------------------------------------------------------
 294  * Set clock output, timebase and RTC source and divider,
 295  * power management and some other internal clocks
 296  */
 297 #define SCCR_MASK       SCCR_EBDF00
 298 /* up to 50 MHz we use a 1:1 clock */
 299 #define CFG_SCCR        (SCCR_COM00 | SCCR_TBS)
 300
 301 /*-----------------------------------------------------------------------
 302  * PCMCIA stuff
 303  *-----------------------------------------------------------------------
 304  *
 305  */
 306 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 307 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 308 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 309 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 310 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 311 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 312 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 313 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 314
 315 /*-----------------------------------------------------------------------
 316  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 317  *-----------------------------------------------------------------------
 318  */
 319
 320 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 321
 322 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 323 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 324 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 325
 326 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 327 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 328
 329 #define CFG_ATA_IDE0_OFFSET     0x0000
 330
 331 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 332
 333 /* Offset for data I/O                  */
 334 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 335
 336 /* Offset for normal register accesses  */
 337 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 338
 339 /* Offset for alternate registers       */
 340 #define CFG_ATA_ALT_OFFSET      0x0100
 341
 342 /*-----------------------------------------------------------------------
 343  *
 344  *-----------------------------------------------------------------------
 345  *
 346  */
 347 /*#define       CFG_DER 0x2002000F*/
 348 #define CFG_DER 0
 349
 350 /*
 351  * Init Memory Controller:
 352  *
 353  * BR0 and OR0 (FLASH)
 354  */
 355
 356 #define FLASH_BASE_PRELIM       0xFE000000      /* FLASH base */
 357 #define CFG_PRELIM_OR_AM        0xFE000000      /* OR addr mask */
 358
 359 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 360 #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 361
 362 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 363 #define CFG_BR0_PRELIM  ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 364
 365 /*
 366  * BR1 and OR1 (SDRAM)
 367  *
 368  */
 369 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 370 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB */
 371
 372 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 373 #define CFG_OR_TIMING_SDRAM     0x00000E00
 374
 375 #define CFG_OR1_PRELIM  (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
 376 #define CFG_BR1_PRELIM  ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 377
 378 /* RPXLITE mem setting */
 379 #define CFG_BR3_PRELIM  0xFA400001              /* FPGA */
 380 #define CFG_OR3_PRELIM  0xFFFF8910
 381
 382 #define CFG_BR4_PRELIM  0xFA000401              /* NVRAM&SRAM */
 383 #define CFG_OR4_PRELIM  0xFFFE0970
 384
 385 /*
 386  * Memory Periodic Timer Prescaler
 387  */
 388
 389 /* periodic timer for refresh */
 390 #define CFG_MAMR_PTA    20
 391
 392 /*
 393  * Refresh clock Prescalar
 394  */
 395 #define CFG_MPTPR       MPTPR_PTP_DIV2
 396
 397 /*
 398  * MAMR settings for SDRAM
 399  */
 400
 401 /* 9 column SDRAM */
 402 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 403                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 404                          MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
 405
 406 /*
 407  * Internal Definitions
 408  *
 409  * Boot Flags
 410  */
 411 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 412 #define BOOTFLAG_WARM   0x02    /* Software reboot                      */
 413
 414 /*
 415  * BCSRx
 416  *
 417  * Board Status and Control Registers
 418  *
 419  */
 420
 421 #define BCSR0 0xFA400000
 422 #define BCSR1 0xFA400001
 423 #define BCSR2 0xFA400002
 424 #define BCSR3 0xFA400003
 425
 426 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 427 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 428 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 429 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 430 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 431 #define BCSR0_COLTEST   0x20
 432 #define BCSR0_ETHLPBK   0x40
 433 #define BCSR0_ETHEN     0x80
 434
 435 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 436 #define BCSR1_PCVCTL6   0x02
 437 #define BCSR1_PCVCTL5   0x04
 438 #define BCSR1_PCVCTL4   0x08
 439 #define BCSR1_IPB5SEL   0x10
 440
 441 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 442 #define BCSR2_ENUSBCLK  0x10
 443 #define BCSR2_USBPWREN  0x20
 444 #define BCSR2_USBSPD    0x40
 445 #define BCSR2_USBSUSP   0x80
 446
 447 #define BCSR3_BWRTC     0x01    /* Real Time Clock Battery */
 448 #define BCSR3_BWNVR     0x02    /* NVRAM Battery */
 449 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 450 #define BCSR3_RPXL      0x08    /* Reserved (reads back '1') */
 451 #define BCSR3_D27       0x10    /* Dip Switch settings */
 452 #define BCSR3_D26       0x20
 453 #define BCSR3_D25       0x40
 454 #define BCSR3_D24       0x80
 455
 456 #endif  /* __CONFIG_H */