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Merge branch 'master' of git://www.denx.de/git/u-boot-fdt
[u-boot-openmoko/qq2440-openmoko-u-boot.git] / include / configs / canyonlands.h
bloba1c6674b1ad5860939df7bdd0a3b6128c6db3cab
1 /*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 /************************************************************************
22 * canyonlands.h - configuration for Canyonlands (460EX)
23 ***********************************************************************/
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30 /* This config file is used for Canyonlands (460EX) and Glacier (460GT) */
31 #ifndef CONFIG_CANYONLANDS
32 #define CONFIG_460GT 1 /* Specific PPC460GT */
33 #else
34 #define CONFIG_460EX 1 /* Specific PPC460EX */
35 #endif
36 #define CONFIG_440 1
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38
39 #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
40
41 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
43 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
44 #define CONFIG_BOARD_TYPES 1 /* support board types */
45
46 /*-----------------------------------------------------------------------
47 * Base addresses -- Note these are effective addresses where the
48 * actual resources get mapped (not physical addresses)
49 *----------------------------------------------------------------------*/
50 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
51
52 #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
53 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
54 #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
55
56 #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
57 #define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
58 #define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
59
60 #define CFG_PCIE0_CFGBASE 0xc0000000
61 #define CFG_PCIE1_CFGBASE 0xc1000000
62 #define CFG_PCIE0_XCFGBASE 0xc3000000
63 #define CFG_PCIE1_XCFGBASE 0xc3001000
64
65 #define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
66
67 /* base address of inbound PCIe window */
68 #define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
69
70 /* EBC stuff */
71 #define CFG_NAND_ADDR 0xE0000000
72 #define CFG_BCSR_BASE 0xE1000000
73 #define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
74 #define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */
75 #define CFG_FLASH_BASE_PHYS_H 0x4
76 #define CFG_FLASH_BASE_PHYS_L 0xCC000000
77 #define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
78 (u64)CFG_FLASH_BASE_PHYS_L)
79 #define CFG_FLASH_SIZE (64 << 20)
80
81 #define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */
82 #define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
83 #define CFG_LOCAL_CONF_REGS 0xEF000000
84
85 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
86
87 #define CFG_AHB_BASE 0xE2000000 /* internal AHB peripherals */
88
89 #define CFG_MONITOR_BASE TEXT_BASE
90 #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
91 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/
92
93 /*-----------------------------------------------------------------------
94 * Initial RAM & stack pointer (placed in OCM)
95 *----------------------------------------------------------------------*/
96 #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
97 #define CFG_INIT_RAM_END (4 << 10)
98 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
99 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
100 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
101
102 /*-----------------------------------------------------------------------
103 * Serial Port
104 *----------------------------------------------------------------------*/
105 #define CONFIG_BAUDRATE 115200
106 #define CONFIG_SERIAL_MULTI 1
107 #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
108
109 #define CFG_BAUDRATE_TABLE \
110 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
111
112 /*-----------------------------------------------------------------------
113 * Environment
114 *----------------------------------------------------------------------*/
115 /*
116 * Define here the location of the environment variables (FLASH).
117 */
118 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
119 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
120 #define CFG_NAND_CS 3 /* NAND chip connected to CSx */
121 #else
122 #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
123 #define CFG_NAND_CS 0 /* NAND chip connected to CSx */
124 #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
125 #endif
126
127 /*
128 * IPL (Initial Program Loader, integrated inside CPU)
129 * Will load first 4k from NAND (SPL) into cache and execute it from there.
130 *
131 * SPL (Secondary Program Loader)
132 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
133 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
134 * controller and the NAND controller so that the special U-Boot image can be
135 * loaded from NAND to SDRAM.
136 *
137 * NUB (NAND U-Boot)
138 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
139 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
140 *
141 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
142 * set up. While still running from cache, I experienced problems accessing
143 * the NAND controller. sr - 2006-08-25
144 */
145 #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
146 #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
147 #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
148 #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
149 #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */
150 /* this addr */
151 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
152
153 /*
154 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
155 */
156 #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
157 #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
158
159 /*
160 * Now the NAND chip has to be defined (no autodetection used!)
161 */
162 #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
163 #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
164 #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
165 #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
166 #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
167
168 #define CFG_NAND_ECCSIZE 256
169 #define CFG_NAND_ECCBYTES 3
170 #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
171 #define CFG_NAND_OOBSIZE 16
172 #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
173 #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
174
175 #ifdef CFG_ENV_IS_IN_NAND
176 /*
177 * For NAND booting the environment is embedded in the U-Boot image. Please take
178 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
179 */
180 #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
181 #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
182 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
183 #endif
184
185 /*-----------------------------------------------------------------------
186 * FLASH related
187 *----------------------------------------------------------------------*/
188 #define CFG_FLASH_CFI /* The flash is CFI compatible */
189 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
190 #define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
191
192 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
193 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
194 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
195
196 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
197 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
198
199 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
200 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
201
202 #ifdef CFG_ENV_IS_IN_FLASH
203 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
204 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
205 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
206
207 /* Address and size of Redundant Environment Sector */
208 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
209 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
210 #endif /* CFG_ENV_IS_IN_FLASH */
211
212 /*-----------------------------------------------------------------------
213 * NAND-FLASH related
214 *----------------------------------------------------------------------*/
215 #define CFG_MAX_NAND_DEVICE 1
216 #define NAND_MAX_CHIPS 1
217 #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
218 #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
219
220 /*------------------------------------------------------------------------------
221 * DDR SDRAM
222 *----------------------------------------------------------------------------*/
223 #if !defined(CONFIG_NAND_U_BOOT)
224 /*
225 * NAND booting U-Boot version uses a fixed initialization, since the whole
226 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
227 * code.
228 */
229 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
230 #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
231 #define CONFIG_DDR_ECC 1 /* with ECC support */
232 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
233 #endif
234 #define CFG_MBYTES_SDRAM 256 /* 256MB */
235
236 /*-----------------------------------------------------------------------
237 * I2C
238 *----------------------------------------------------------------------*/
239 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
240 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
241 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
242 #define CFG_I2C_SLAVE 0x7F
243
244 #define CFG_I2C_MULTI_EEPROMS
245 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
246 #define CFG_I2C_EEPROM_ADDR_LEN 1
247 #define CFG_EEPROM_PAGE_WRITE_ENABLE
248 #define CFG_EEPROM_PAGE_WRITE_BITS 3
249 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
250
251 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
252 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
253 #define CONFIG_DTT_AD7414 1 /* use AD7414 */
254 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
255 #define CFG_DTT_MAX_TEMP 70
256 #define CFG_DTT_LOW_TEMP -30
257 #define CFG_DTT_HYSTERESIS 3
258
259 /* RTC configuration */
260 #define CONFIG_RTC_M41T62 1
261 #define CFG_I2C_RTC_ADDR 0x68
262
263 /*-----------------------------------------------------------------------
264 * Ethernet
265 *----------------------------------------------------------------------*/
266 #define CONFIG_IBM_EMAC4_V4 1
267 #define CONFIG_MII 1 /* MII PHY management */
268 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
269 #define CONFIG_PHY1_ADDR 1
270 #define CONFIG_HAS_ETH0
271 #define CONFIG_HAS_ETH1
272 /* Only Glacier (460GT) has 4 EMAC interfaces */
273 #ifdef CONFIG_460GT
274 #define CONFIG_PHY2_ADDR 2
275 #define CONFIG_PHY3_ADDR 3
276 #define CONFIG_HAS_ETH2
277 #define CONFIG_HAS_ETH3
278 #endif
279 #define CONFIG_NET_MULTI 1
280
281 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
282 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
283 #define CONFIG_PHY_DYNAMIC_ANEG 1
284
285 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
286
287 /*-----------------------------------------------------------------------
288 * USB-OHCI
289 *----------------------------------------------------------------------*/
290 /* Only Canyonlands (460EX) has USB */
291 #ifdef CONFIG_460EX
292 #define CONFIG_USB_OHCI_NEW
293 #define CONFIG_USB_STORAGE
294 #undef CFG_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
295 #define CFG_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
296 #define CFG_OHCI_USE_NPS /* force NoPowerSwitching mode */
297 #define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000)
298 #define CFG_USB_OHCI_SLOT_NAME "ppc440"
299 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
300 #endif
301
302 /*-----------------------------------------------------------------------
303 * Default environment
304 *----------------------------------------------------------------------*/
305 #define CONFIG_PREBOOT "echo;" \
306 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
307 "echo"
308
309 #undef CONFIG_BOOTARGS
310
311 /* Setup some board specific values for the default environment variables */
312 #ifdef CONFIG_CANYONLANDS
313 #define CONFIG_HOSTNAME canyonlands
314 #define CFG_BOOTFILE "bootfile=canyonlands/uImage\0"
315 #define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0"
316 #else
317 #define CONFIG_HOSTNAME glacier
318 #define CFG_BOOTFILE "bootfile=glacier/uImage\0"
319 #define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0"
320 #endif
321
322 #define CONFIG_EXTRA_ENV_SETTINGS \
323 CFG_BOOTFILE \
324 CFG_DTBFILE \
325 "netdev=eth0\0" \
326 "nfsargs=setenv bootargs root=/dev/nfs rw " \
327 "nfsroot=${serverip}:${rootpath}\0" \
328 "ramargs=setenv bootargs root=/dev/ram rw\0" \
329 "addip=setenv bootargs ${bootargs} " \
330 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
331 ":${hostname}:${netdev}:off panic=1\0" \
332 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
333 "net_nfs=tftp 200000 ${bootfile};" \
334 "run nfsargs addip addtty;" \
335 "bootm 200000\0" \
336 "net_nfs_fdt=tftp 200000 ${bootfile};" \
337 "tftp ${fdt_addr} ${fdt_file};" \
338 "run nfsargs addip addtty;" \
339 "bootm 200000 - ${fdt_addr}\0" \
340 "flash_nfs=run nfsargs addip addtty;" \
341 "bootm ${kernel_addr}\0" \
342 "flash_self=run ramargs addip addtty;" \
343 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
344 "rootpath=/opt/eldk/ppc_4xxFP\0" \
345 "fdt_addr=400000\0" \
346 "kernel_addr=fc000000\0" \
347 "ramdisk_addr=fc200000\0" \
348 "initrd_high=30000000\0" \
349 "load=tftp 200000 ${hostname}/u-boot.bin\0" \
350 "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
351 "cp.b ${fileaddr} fffa0000 ${filesize};" \
352 "setenv filesize;saveenv\0" \
353 "upd=run load update\0" \
354 "nload=tftp 200000 ${hostname}/u-boot-nand.bin\0" \
355 "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
356 "setenv filesize;saveenv\0" \
357 "nupd=run nload nupdate\0" \
358 "pciconfighost=1\0" \
359 "pcie_mode=RP:RP\0" \
360 ""
361 #define CONFIG_BOOTCOMMAND "run flash_self"
362
363 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
364
365 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
366 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
367
368 /*
369 * BOOTP options
370 */
371 #define CONFIG_BOOTP_BOOTFILESIZE
372 #define CONFIG_BOOTP_BOOTPATH
373 #define CONFIG_BOOTP_GATEWAY
374 #define CONFIG_BOOTP_HOSTNAME
375 #define CONFIG_BOOTP_SUBNETMASK
376
377 /*
378 * Command line configuration.
379 */
380 #include <config_cmd_default.h>
381
382 #define CONFIG_CMD_ASKENV
383 #define CONFIG_CMD_DATE
384 #define CONFIG_CMD_DHCP
385 #define CONFIG_CMD_DTT
386 #define CONFIG_CMD_DIAG
387 #define CONFIG_CMD_EEPROM
388 #define CONFIG_CMD_ELF
389 #define CONFIG_CMD_I2C
390 #define CONFIG_CMD_IRQ
391 #define CONFIG_CMD_MII
392 #define CONFIG_CMD_NAND
393 #define CONFIG_CMD_NET
394 #define CONFIG_CMD_NFS
395 #define CONFIG_CMD_PCI
396 #define CONFIG_CMD_PING
397 #define CONFIG_CMD_REGINFO
398 #define CONFIG_CMD_SDRAM
399 #ifdef CONFIG_460EX
400 #define CONFIG_CMD_EXT2
401 #define CONFIG_CMD_FAT
402 #define CONFIG_CMD_USB
403 #endif
404
405 /* Partitions */
406 #define CONFIG_MAC_PARTITION
407 #define CONFIG_DOS_PARTITION
408 #define CONFIG_ISO_PARTITION
409
410 /*-----------------------------------------------------------------------
411 * Miscellaneous configurable options
412 *----------------------------------------------------------------------*/
413 #define CFG_LONGHELP /* undef to save memory */
414 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
415 #if defined(CONFIG_CMD_KGDB)
416 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
417 #else
418 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
419 #endif
420 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
421 #define CFG_MAXARGS 16 /* max number of command args */
422 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
423
424 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
425 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
426
427 #define CFG_LOAD_ADDR 0x100000 /* default load address */
428 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
429
430 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
431
432 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
433 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
434 #define CONFIG_LOOPW 1 /* enable loopw command */
435 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
436 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
437 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
438 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
439
440 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
441 #ifdef CFG_HUSH_PARSER
442 #define CFG_PROMPT_HUSH_PS2 "> "
443 #endif
444
445 /*-----------------------------------------------------------------------
446 * PCI stuff
447 *----------------------------------------------------------------------*/
448 /* General PCI */
449 #define CONFIG_PCI /* include pci support */
450 #define CONFIG_PCI_PNP /* do pci plug-and-play */
451 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
452 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
453
454 /* Board-specific PCI */
455 #define CFG_PCI_TARGET_INIT /* let board init pci target */
456 #undef CFG_PCI_MASTER_INIT
457
458 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
459 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
460
461 /*
462 * For booting Linux, the board info and command line data
463 * have to be in the first 8 MB of memory, since this is
464 * the maximum mapped by the Linux kernel during initialization.
465 */
466 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
467
468 /*
469 * Internal Definitions
470 */
471 #if defined(CONFIG_CMD_KGDB)
472 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
473 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
474 #endif
475
476 /*-----------------------------------------------------------------------
477 * External Bus Controller (EBC) Setup
478 *----------------------------------------------------------------------*/
479
480 /*
481 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
482 * boot EBC mapping only supports a maximum of 16MBytes
483 * (4.ff00.0000 - 4.ffff.ffff).
484 * To solve this problem, the FLASH has to get remapped to another
485 * EBC address which accepts bigger regions:
486 *
487 * 0xfc00.0000 -> 4.cc00.0000
488 */
489
490 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
491 /* Memory Bank 3 (NOR-FLASH) initialization */
492 #define CFG_EBC_PB3AP 0x10055e00
493 #define CFG_EBC_PB3CR (CFG_BOOT_BASE_ADDR | 0x9a000)
494
495 /* Memory Bank 0 (NAND-FLASH) initialization */
496 #define CFG_EBC_PB0AP 0x018003c0
497 #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
498 #else
499 /* Memory Bank 0 (NOR-FLASH) initialization */
500 #define CFG_EBC_PB0AP 0x10055e00
501 #define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
502
503 /* Memory Bank 3 (NAND-FLASH) initialization */
504 #define CFG_EBC_PB3AP 0x018003c0
505 #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
506 #endif
507
508 /* Memory Bank 2 (CPLD) initialization */
509 #define CFG_EBC_PB2AP 0x00804240
510 #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
511
512 #define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
513
514 /*
515 * PPC4xx GPIO Configuration
516 */
517 #ifdef CONFIG_460EX
518 /* 460EX: Use USB configuration */
519 #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
520 { \
521 /* GPIO Core 0 */ \
522 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
523 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
524 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
525 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
526 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
527 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
528 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
529 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
530 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
531 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
532 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
533 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
534 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
535 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
536 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
537 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
538 {GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
539 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
540 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
541 {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
542 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
543 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
544 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
545 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
546 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
547 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
548 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
549 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
550 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
551 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
552 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
553 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
554 }, \
555 { \
556 /* GPIO Core 1 */ \
557 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
558 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
559 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
560 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
561 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
562 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
563 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
564 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
565 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
566 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
567 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
568 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
569 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
570 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
571 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
572 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
573 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
574 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
575 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
576 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
577 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
578 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
579 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
580 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
581 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
582 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
583 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
584 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
585 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
586 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
587 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
588 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
589 } \
590 }
591 #else
592 /* 460GT: Use EMAC2+3 configuration */
593 #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
594 { \
595 /* GPIO Core 0 */ \
596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
597 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
598 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
599 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
600 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
601 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
602 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
603 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
604 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
605 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
606 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
607 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
608 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
609 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
610 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
611 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
612 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
613 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
614 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
615 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
616 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
617 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
618 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
619 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
620 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
621 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
622 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
623 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
624 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
625 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
626 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
627 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
628 }, \
629 { \
630 /* GPIO Core 1 */ \
631 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
632 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
633 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
634 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
635 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
636 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
637 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
638 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
639 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
640 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
641 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
642 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
643 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
644 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
645 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
646 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
647 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
648 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
649 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
650 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
651 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
652 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
653 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
654 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
655 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
656 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
657 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
658 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
659 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
660 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
661 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
662 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
663 } \
664 }
665 #endif
666
667 /* pass open firmware flat tree */
668 #define CONFIG_OF_LIBFDT 1
669 #define CONFIG_OF_BOARD_SETUP 1
670
671 #endif /* __CONFIG_H */
qq2440-openmoko-u-boot