include/configs/Total5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * Check valid setting of revision define.
  32  * Total5100 and Total5200 Rev.1 are identical except for the processor.
  33  */
  34 #if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
  35 #error CONFIG_TOTAL5200_REV must be 1 or 2
  36 #endif
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42
  43 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  44 #define CONFIG_TOTAL5200        1       /* ... on Total5200 board */
  45
  46 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  47
  48 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  49 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  50
  51 /*
  52  * Serial console configuration
  53  */
  54 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
  55 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  56 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  57
  58 /*
  59  * Video console
  60  */
  61 #define CONFIG_VIDEO
  62 #define CONFIG_VIDEO_SED13806
  63 #define CONFIG_VIDEO_SED13806_16BPP
  64
  65 #define CONFIG_CFB_CONSOLE
  66 #define CONFIG_VIDEO_LOGO
  67 /* #define CONFIG_VIDEO_BMP_LOGO */
  68 #define CONFIG_CONSOLE_EXTRA_INFO
  69 #define CONFIG_VGA_AS_SINGLE_DEVICE
  70 #define CONFIG_VIDEO_SW_CURSOR
  71 #define CONFIG_SPLASH_SCREEN
  72
  73
  74 #ifdef CONFIG_MPC5200   /* MGT5100 PCI is not supported yet. */
  75 /*
  76  * PCI Mapping:
  77  * 0x40000000 - 0x4fffffff - PCI Memory
  78  * 0x50000000 - 0x50ffffff - PCI IO Space
  79  */
  80 #define CONFIG_PCI              1
  81 #define CONFIG_PCI_PNP          1
  82 #define CONFIG_PCI_SCAN_SHOW    1
  83
  84 #define CONFIG_PCI_MEM_BUS      0x40000000
  85 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  86 #define CONFIG_PCI_MEM_SIZE     0x10000000
  87
  88 #define CONFIG_PCI_IO_BUS       0x50000000
  89 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  90 #define CONFIG_PCI_IO_SIZE      0x01000000
  91
  92 #define CONFIG_NET_MULTI        1
  93 #define CONFIG_MII              1
  94 #define CONFIG_EEPRO100         1
  95 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  96 #define CONFIG_NS8382X          1
  97
  98 #else   /* MGT5100 */
  99
 100 #define CONFIG_MII              1
 101
 102 #endif
 103
 104 /* Partitions */
 105 #define CONFIG_MAC_PARTITION
 106 #define CONFIG_DOS_PARTITION
 107
 108 /* USB */
 109 #define CONFIG_USB_OHCI
 110 #define CONFIG_USB_STORAGE
 111
 112
 113 /*
 114  * BOOTP options
 115  */
 116 #define CONFIG_BOOTP_BOOTFILESIZE
 117 #define CONFIG_BOOTP_BOOTPATH
 118 #define CONFIG_BOOTP_GATEWAY
 119 #define CONFIG_BOOTP_HOSTNAME
 120
 121
 122 /*
 123  * Command line configuration.
 124  */
 125 #include <config_cmd_default.h>
 126
 127 #if defined(CONFIG_MPC5200)
 128     #define CONFIG_CMD_PCI
 129 #endif
 130
 131 #define CONFIG_CMD_BMP
 132 #define CONFIG_CMD_EEPROM
 133 #define CONFIG_CMD_FAT
 134 #define CONFIG_CMD_I2C
 135 #define CONFIG_CMD_IDE
 136 #define CONFIG_CMD_PING
 137 #define CONFIG_CMD_USB
 138
 139
 140 #if (TEXT_BASE == 0xFE000000)           /* Boot low */
 141 #   define CFG_LOWBOOT          1
 142 #endif
 143
 144 /*
 145  * Autobooting
 146  */
 147 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 148
 149 #define CONFIG_PREBOOT  \
 150         "setenv stdout serial;setenv stderr serial;" \
 151         "echo;" \
 152         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 153         "echo"
 154
 155 #undef  CONFIG_BOOTARGS
 156
 157 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 158         "netdev=eth0\0"                                                 \
 159         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 160                 "nfsroot=${serverip}:${rootpath}\0"                     \
 161         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 162         "addip=setenv bootargs ${bootargs} "                            \
 163                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 164                 ":${hostname}:${netdev}:off panic=1\0"                  \
 165         "flash_nfs=run nfsargs addip;"                                  \
 166                 "bootm ${kernel_addr}\0"                                \
 167         "flash_self=run ramargs addip;"                                 \
 168                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 169         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 170         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 171         "bootfile=/tftpboot/MPC5200/uImage\0"                           \
 172         ""
 173
 174 #define CONFIG_BOOTCOMMAND      "run flash_self"
 175
 176 #if defined(CONFIG_MPC5200)
 177 /*
 178  * IPB Bus clocking configuration.
 179  */
 180 #undef CFG_IPBCLK_EQUALS_XLBCLK                 /* define for 133MHz speed */
 181 #endif
 182
 183 /*
 184  * I2C configuration
 185  */
 186 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 187 #define CFG_I2C_MODULE          1       /* Select I2C module #1 or #2 */
 188
 189 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 190 #define CFG_I2C_SLAVE           0x7F
 191
 192 /*
 193  * EEPROM configuration
 194  */
 195 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 196 #define CFG_I2C_EEPROM_ADDR_LEN         1
 197 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 198 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  70
 199
 200 /*
 201  * Flash configuration
 202  */
 203 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 204 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 205 #if CONFIG_TOTAL5200_REV==2
 206 #   define CFG_MAX_FLASH_BANKS  3       /* max num of flash banks */
 207 #   define CFG_FLASH_BANKS_LIST { CFG_CS5_START, CFG_CS4_START, CFG_BOOTCS_START }
 208 #else
 209 #   define CFG_MAX_FLASH_BANKS  1       /* max num of flash banks  */
 210 #   define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
 211 #endif
 212 #define CFG_FLASH_EMPTY_INFO
 213 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 214
 215 #if CONFIG_TOTAL5200_REV==1
 216 #   define CFG_FLASH_BASE       0xFE000000
 217 #   define CFG_FLASH_SIZE       0x02000000
 218 #elif CONFIG_TOTAL5200_REV==2
 219 #   define CFG_FLASH_BASE       0xFA000000
 220 #   define CFG_FLASH_SIZE       0x06000000
 221 #endif /* CONFIG_TOTAL5200_REV */
 222
 223 #if defined(CFG_LOWBOOT)
 224 #   define CFG_ENV_ADDR         0xFE040000
 225 #else   /* CFG_LOWBOOT */
 226 #   define CFG_ENV_ADDR         0xFFF40000
 227 #endif  /* CFG_LOWBOOT */
 228
 229 /*
 230  * Environment settings
 231  */
 232 #define CFG_ENV_IS_IN_FLASH     1
 233 #define CFG_ENV_SIZE            0x40000
 234 #define CFG_ENV_SECT_SIZE       0x40000
 235 #define CONFIG_ENV_OVERWRITE    1
 236
 237 /*
 238  * Memory map
 239  */
 240 #define CFG_SDRAM_BASE          0x00000000
 241 #define CFG_DEFAULT_MBAR        0x80000000
 242 #define CFG_MBAR                0xF0000000      /*   64 kB */
 243 #define CFG_FPGA_BASE           0xF0010000      /*   64 kB */
 244 #define CFG_CPLD_BASE           0xF0020000      /*   64 kB */
 245 #define CFG_LCD_BASE            0xF1000000      /* 4096 kB */
 246
 247 /* Use SRAM until RAM will be available */
 248 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 249 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 250
 251 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 252 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 253 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 254
 255 #define CFG_MONITOR_BASE    TEXT_BASE
 256 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 257 #   define CFG_RAMBOOT          1
 258 #endif
 259
 260 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 261 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 262 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 263
 264 /*
 265  * Ethernet configuration
 266  */
 267 #define CONFIG_MPC5xxx_FEC      1
 268 /* dummy, 7-wire FEC does not have phy address */
 269 #define CONFIG_PHY_ADDR         0x00
 270
 271 /*
 272  * GPIO configuration
 273  *
 274  * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
 275  * Reserved                                                      0
 276  * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
 277  * CS7:   Interrupt GPIO on PSC3_5                               0
 278  * CS8:   Interrupt GPIO on PSC3_4                               0
 279  * ATA:   reset default, changed in ATA driver                   00
 280  * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
 281  * IRDA:  reset default, changed in IrDA driver                  000
 282  * ETHER: reset default, changed in Ethernet driver              0000
 283  * PCI_DIS: reset default, changed in PCI driver                 0
 284  * USB_SE: reset default, changed in USB driver                  0
 285  * USB:   reset default, changed in USB driver                   00
 286  * PSC3:  SPI and UART functionality without CD                  1100
 287  * Reserved                                                      0
 288  * PSC2:  CAN1/2                                                 001
 289  * Reserved                                                      0
 290  * PSC1:  reset default, changed in AC'97 driver                 000
 291  *
 292  */
 293 #define CFG_GPS_PORT_CONFIG     0x00000C10
 294
 295 /*
 296  * Miscellaneous configurable options
 297  */
 298 #define CFG_LONGHELP                    /* undef to save memory     */
 299 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 300 #if defined(CONFIG_CMD_KGDB)
 301 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 302 #else
 303 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 304 #endif
 305 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 306 #define CFG_MAXARGS             16              /* max number of command args   */
 307 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 308
 309 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 310 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 311
 312 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 313
 314 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 315
 316 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 317 #if defined(CONFIG_CMD_KGDB)
 318 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 319 #endif
 320
 321
 322 /*
 323  * Various low-level settings
 324  */
 325 #if defined(CONFIG_MPC5200)
 326 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 327 #define CFG_HID0_FINAL          HID0_ICE
 328 #else
 329 #define CFG_HID0_INIT           0
 330 #define CFG_HID0_FINAL          0
 331 #endif
 332
 333 #if defined (CONFIG_MGT5100)
 334 #   define CONFIG_BOARD_EARLY_INIT_R    /* switch from CS_BOOT to CS0 */
 335 #endif
 336
 337 #if CONFIG_TOTAL5200_REV==1
 338 #   define CFG_BOOTCS_START     CFG_FLASH_BASE
 339 #   define CFG_BOOTCS_SIZE      0x02000000      /* 32 MB */
 340 #   define CFG_BOOTCS_CFG       0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 341 #   define CFG_CS0_START        CFG_FLASH_BASE
 342 #   define CFG_CS0_SIZE         0x02000000      /* 32 MB */
 343 #else
 344 #   define CFG_BOOTCS_START     (CFG_CS4_START + CFG_CS4_SIZE)
 345 #   define CFG_BOOTCS_SIZE      0x02000000      /* 32 MB */
 346 #   define CFG_BOOTCS_CFG       0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 347 #   define CFG_CS4_START        (CFG_CS5_START + CFG_CS5_SIZE)
 348 #   define CFG_CS4_SIZE         0x02000000      /* 32 MB */
 349 #   define CFG_CS4_CFG          0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 350 #   define CFG_CS5_START        CFG_FLASH_BASE
 351 #   define CFG_CS5_SIZE         0x02000000      /* 32 MB */
 352 #   define CFG_CS5_CFG          0x0004DF00      /* 4WS, MX, AL, CE, AS_25, DS_32 */
 353 #endif
 354
 355 #define CFG_CS1_START           CFG_FPGA_BASE
 356 #define CFG_CS1_SIZE            0x00010000      /* 64 kB */
 357 #define CFG_CS1_CFG             0x0019FF00      /* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
 358
 359 #define CFG_CS2_START           CFG_LCD_BASE
 360 #define CFG_CS2_SIZE            0x00400000      /* 4096 kB */
 361 #define CFG_CS2_CFG             0x0032FD0C      /* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
 362
 363 #if CONFIG_TOTAL5200_REV==1
 364 #   define CFG_CS3_START        CFG_CPLD_BASE
 365 #   define CFG_CS3_SIZE         0x00010000      /* 64 kB */
 366 #   define CFG_CS3_CFG          0x000ADF00      /* 10WS, MX, AL, CE, AS_25, DS_32 */
 367 #else
 368 #   define CFG_CS3_START        CFG_CPLD_BASE
 369 #   define CFG_CS3_SIZE         0x00010000      /* 64 kB */
 370 #   define CFG_CS3_CFG          0x000AD800      /* 10WS, MX, AL, CE, AS_24, DS_8 */
 371 #endif
 372
 373 #define CFG_CS_BURST            0x00000000
 374 #define CFG_CS_DEADCYCLE        0x33333333
 375
 376 /*-----------------------------------------------------------------------
 377  * USB stuff
 378  *-----------------------------------------------------------------------
 379  */
 380 #define CONFIG_USB_CLOCK        0x0001BBBB
 381 #define CONFIG_USB_CONFIG       0x00001000
 382
 383 /*-----------------------------------------------------------------------
 384  * IDE/ATA stuff Supports IDE harddisk
 385  *-----------------------------------------------------------------------
 386  */
 387
 388 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 389
 390 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 391 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 392
 393 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 394 #define CONFIG_IDE_PREINIT
 395
 396 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 397 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 398
 399 #define CFG_ATA_IDE0_OFFSET     0x0000
 400
 401 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 402
 403 /* Offset for data I/O                  */
 404 #define CFG_ATA_DATA_OFFSET     (0x0060)
 405
 406 /* Offset for normal register accesses  */
 407 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 408
 409 /* Offset for alternate registers       */
 410 #define CFG_ATA_ALT_OFFSET      (0x005C)
 411
 412 /* Interval between registers                                                */
 413 #define CFG_ATA_STRIDE          4
 414
 415 #endif /* __CONFIG_H */