include/configs/NETTA.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  26  * U-Boot port on NetTA4 board
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #define CONFIG_MPC885           1       /* This is a MPC885 CPU         */
  38 #define CONFIG_NETTA            1       /* ...on a NetTA board          */
  39
  40 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  41 #undef  CONFIG_8xx_CONS_SMC2
  42 #undef  CONFIG_8xx_CONS_NONE
  43
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  45
  46 /* #define CONFIG_XIN            10000000 */
  47 #define CONFIG_XIN               50000000
  48 #define MPC8XX_HZ               120000000
  49 /* #define MPC8XX_HZ            100000000 */
  50 /* #define MPC8XX_HZ             50000000 */
  51 /* #define MPC8XX_HZ             80000000 */
  52
  53 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_HZ
  54
  55 #if 0
  56 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  57 #else
  58 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  59 #endif
  60
  61 #undef  CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
  62
  63 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  64
  65 #undef  CONFIG_BOOTARGS
  66 #define CONFIG_BOOTCOMMAND                                                      \
  67         "tftpboot; "                                                            \
  68         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  69         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  70         "bootm"
  71
  72 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  73 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76 #define CONFIG_HW_WATCHDOG
  77
  78 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_SUBNETMASK
  84 #define CONFIG_BOOTP_GATEWAY
  85 #define CONFIG_BOOTP_HOSTNAME
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88 #define CONFIG_BOOTP_NISDOMAIN
  89
  90
  91 #undef CONFIG_MAC_PARTITION
  92 #undef CONFIG_DOS_PARTITION
  93
  94 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  95
  96 #define CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
  97 #define FEC_ENET                1       /* eth.c needs it that way... */
  98 #undef  CFG_DISCOVER_PHY                /* do not discover phys */
  99 #define CONFIG_MII              1
 100 #define CONFIG_RMII             1       /* use RMII interface */
 101
 102 #if defined(CONFIG_NETTA_ISDN)
 103 #define CONFIG_ETHER_ON_FEC1    1
 104 #define CONFIG_FEC1_PHY         1       /* phy address of FEC1 */
 105 #define CONFIG_FEC1_PHY_NORXERR 1
 106 #undef  CONFIG_ETHER_ON_FEC2
 107 #else
 108 #define CONFIG_ETHER_ON_FEC1    1
 109 #define CONFIG_FEC1_PHY         8       /* phy address of FEC1 */
 110 #define CONFIG_FEC1_PHY_NORXERR 1
 111 #define CONFIG_ETHER_ON_FEC2    1
 112 #define CONFIG_FEC2_PHY         1       /* phy address of FEC2 */
 113 #define CONFIG_FEC2_PHY_NORXERR 1
 114 #endif
 115
 116 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 117
 118 /* POST support */
 119 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 120                                  CFG_POST_CODEC    | \
 121                                  CFG_POST_DSP      )
 122
 123
 124 /*
 125  * Command line configuration.
 126  */
 127 #include <config_cmd_default.h>
 128
 129 #define CONFIG_CMD_CDP
 130 #define CONFIG_CMD_DHCP
 131 #define CONFIG_CMD_DIAG
 132 #define CONFIG_CMD_FAT
 133 #define CONFIG_CMD_IDE
 134 #define CONFIG_CMD_JFFS2
 135 #define CONFIG_CMD_MII
 136 #define CONFIG_CMD_NAND
 137 #define CONFIG_CMD_NFS
 138 #define CONFIG_CMD_PCMCIA
 139 #define CONFIG_CMD_PING
 140
 141
 142 #define CONFIG_BOARD_EARLY_INIT_F       1
 143 #define CONFIG_MISC_INIT_R
 144
 145 /*
 146  * Miscellaneous configurable options
 147  */
 148 #define CFG_LONGHELP                    /* undef to save memory         */
 149 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 150
 151 #define CFG_HUSH_PARSER 1
 152 #define CFG_PROMPT_HUSH_PS2     "> "
 153
 154 #if defined(CONFIG_CMD_KGDB)
 155 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 156 #else
 157 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 158 #endif
 159 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 160 #define CFG_MAXARGS     16              /* max number of command args   */
 161 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 162
 163 #define CFG_MEMTEST_START       0x0300000       /* memtest works on     */
 164 #define CFG_MEMTEST_END         0x0700000       /* 3 ... 7 MB in DRAM   */
 165
 166 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 167
 168 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 169
 170 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 171
 172 /*
 173  * Low Level Configuration Settings
 174  * (address mappings, register initial values, etc.)
 175  * You should know what you are doing if you make changes here.
 176  */
 177 /*-----------------------------------------------------------------------
 178  * Internal Memory Mapped Register
 179  */
 180 #define CFG_IMMR                0xFF000000
 181
 182 /*-----------------------------------------------------------------------
 183  * Definitions for initial stack pointer and data area (in DPRAM)
 184  */
 185 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 186 #define CFG_INIT_RAM_END        0x3000  /* End of used area in DPRAM    */
 187 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 188 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 189 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 190
 191 /*-----------------------------------------------------------------------
 192  * Start addresses for the final memory configuration
 193  * (Set up by the startup code)
 194  * Please note that CFG_SDRAM_BASE _must_ start at 0
 195  */
 196 #define CFG_SDRAM_BASE          0x00000000
 197 #define CFG_FLASH_BASE          0x40000000
 198 #if defined(DEBUG)
 199 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 200 #else
 201 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 202 #endif
 203 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 204 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 205
 206 /*
 207  * For booting Linux, the board info and command line data
 208  * have to be in the first 8 MB of memory, since this is
 209  * the maximum mapped by the Linux kernel during initialization.
 210  */
 211 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 212
 213 /*-----------------------------------------------------------------------
 214  * FLASH organization
 215  */
 216 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 217 #define CFG_MAX_FLASH_SECT      8       /* max number of sectors on one chip    */
 218
 219 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 220 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 221
 222 #define CFG_ENV_IS_IN_FLASH     1
 223 #define CFG_ENV_SECT_SIZE       0x10000
 224
 225 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x60000)
 226 #define CFG_ENV_OFFSET          0
 227 #define CFG_ENV_SIZE            0x4000
 228
 229 #define CFG_ENV_ADDR_REDUND     (CFG_FLASH_BASE + 0x70000)
 230 #define CFG_ENV_OFFSET_REDUND   0
 231 #define CFG_ENV_SIZE_REDUND     CFG_ENV_SIZE
 232
 233 /*-----------------------------------------------------------------------
 234  * Cache Configuration
 235  */
 236 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 237 #if defined(CONFIG_CMD_KGDB)
 238 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 239 #endif
 240
 241 /*-----------------------------------------------------------------------
 242  * SYPCR - System Protection Control                            11-9
 243  * SYPCR can only be written once after reset!
 244  *-----------------------------------------------------------------------
 245  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 246  */
 247 #if defined(CONFIG_WATCHDOG)
 248 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 249                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 250 #else
 251 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 252 #endif
 253
 254 /*-----------------------------------------------------------------------
 255  * SIUMCR - SIU Module Configuration                            11-6
 256  *-----------------------------------------------------------------------
 257  * PCMCIA config., multi-function pin tri-state
 258  */
 259 #ifndef CONFIG_CAN_DRIVER
 260 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 261 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 262 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
 263 #endif  /* CONFIG_CAN_DRIVER */
 264
 265 /*-----------------------------------------------------------------------
 266  * TBSCR - Time Base Status and Control                         11-26
 267  *-----------------------------------------------------------------------
 268  * Clear Reference Interrupt Status, Timebase freezing enabled
 269  */
 270 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 271
 272 /*-----------------------------------------------------------------------
 273  * RTCSC - Real-Time Clock Status and Control Register          11-27
 274  *-----------------------------------------------------------------------
 275  */
 276 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 277
 278 /*-----------------------------------------------------------------------
 279  * PISCR - Periodic Interrupt Status and Control                11-31
 280  *-----------------------------------------------------------------------
 281  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 282  */
 283 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 284
 285 /*-----------------------------------------------------------------------
 286  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 287  *-----------------------------------------------------------------------
 288  * Reset PLL lock status sticky bit, timer expired status bit and timer
 289  * interrupt status bit
 290  *
 291  */
 292
 293 #if CONFIG_XIN == 10000000
 294
 295 #if MPC8XX_HZ == 120000000
 296 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 297                          (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 298                          PLPRCR_TEXPS)
 299 #elif MPC8XX_HZ == 100000000
 300 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 301                          (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 302                          PLPRCR_TEXPS)
 303 #elif MPC8XX_HZ == 50000000
 304 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 305                          (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 306                          PLPRCR_TEXPS)
 307 #elif MPC8XX_HZ == 25000000
 308 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 309                          (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
 310                          PLPRCR_TEXPS)
 311 #elif MPC8XX_HZ == 40000000
 312 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 313                          (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 314                          PLPRCR_TEXPS)
 315 #elif MPC8XX_HZ == 75000000
 316 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 317                          (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 318                          PLPRCR_TEXPS)
 319 #else
 320 #error unsupported CPU freq for XIN = 10MHz
 321 #endif
 322
 323 #elif CONFIG_XIN == 50000000
 324
 325 #if MPC8XX_HZ == 120000000
 326 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 327                          (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 328                          PLPRCR_TEXPS)
 329 #elif MPC8XX_HZ == 100000000
 330 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 331                          (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 332                          PLPRCR_TEXPS)
 333 #elif MPC8XX_HZ ==  80000000
 334 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 335                          (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
 336                          PLPRCR_TEXPS)
 337 #elif MPC8XX_HZ ==  50000000
 338 #define CFG_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 339                          (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
 340                          PLPRCR_TEXPS)
 341 #else
 342 #error unsupported CPU freq for XIN = 50MHz
 343 #endif
 344
 345 #else
 346
 347 #error unsupported XIN freq
 348 #endif
 349
 350
 351 /*
 352  *-----------------------------------------------------------------------
 353  * SCCR - System Clock and reset Control Register               15-27
 354  *-----------------------------------------------------------------------
 355  * Set clock output, timebase and RTC source and divider,
 356  * power management and some other internal clocks
 357  *
 358  * Note: When TBS == 0 the timebase is independent of current cpu clock.
 359  */
 360
 361 #define SCCR_MASK       SCCR_EBDF11
 362 #if MPC8XX_HZ > 66666666
 363 #define CFG_SCCR        (/* SCCR_TBS    | */ SCCR_CRQEN | \
 364                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 365                          SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 366                          SCCR_DFALCD00 | SCCR_EBDF01)
 367 #else
 368 #define CFG_SCCR        (/* SCCR_TBS    | */ SCCR_CRQEN | \
 369                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 370                          SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 371                          SCCR_DFALCD00)
 372 #endif
 373
 374 /*-----------------------------------------------------------------------
 375  *
 376  *-----------------------------------------------------------------------
 377  *
 378  */
 379 /*#define       CFG_DER 0x2002000F*/
 380 #define CFG_DER 0
 381
 382 /*
 383  * Init Memory Controller:
 384  *
 385  * BR0/1 and OR0/1 (FLASH)
 386  */
 387
 388 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 389
 390 /* used to re-map FLASH both when starting from SRAM or FLASH:
 391  * restrict access enough to keep SRAM working (if any)
 392  * but not too much to meddle with FLASH accesses
 393  */
 394 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 395 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 396
 397 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 398 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 399
 400 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 401 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 402 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 403
 404 /*
 405  * BR3 and OR3 (SDRAM)
 406  *
 407  */
 408 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
 409 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
 410
 411 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 412 #define CFG_OR_TIMING_SDRAM     (OR_CSNT_SAM | OR_G5LS)
 413
 414 #define CFG_OR3_PRELIM  ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
 415 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
 416
 417 /*
 418  * Memory Periodic Timer Prescaler
 419  */
 420
 421 /*
 422  * Memory Periodic Timer Prescaler
 423  *
 424  * The Divider for PTA (refresh timer) configuration is based on an
 425  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 426  * the number of chip selects (NCS) and the actually needed refresh
 427  * rate is done by setting MPTPR.
 428  *
 429  * PTA is calculated from
 430  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 431  *
 432  *      gclk      CPU clock (not bus clock!)
 433  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 434  *
 435  * 4096  Rows from SDRAM example configuration
 436  * 1000  factor s -> ms
 437  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 438  *    4  Number of refresh cycles per period
 439  *   64  Refresh cycle in ms per number of rows
 440  * --------------------------------------------
 441  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 442  *
 443  * 50 MHz => 50.000.000 / Divider =  98
 444  * 66 Mhz => 66.000.000 / Divider = 129
 445  * 80 Mhz => 80.000.000 / Divider = 156
 446  */
 447
 448 #if   MPC8XX_HZ == 120000000
 449 #define CFG_MAMR_PTA             234
 450 #elif MPC8XX_HZ == 100000000
 451 #define CFG_MAMR_PTA             195
 452 #elif MPC8XX_HZ ==  80000000
 453 #define CFG_MAMR_PTA             156
 454 #elif MPC8XX_HZ ==  50000000
 455 #define CFG_MAMR_PTA              98
 456 #else
 457 #error Unknown frequency
 458 #endif
 459
 460
 461 /*
 462  * For 16 MBit, refresh rates could be 31.3 us
 463  * (= 64 ms / 2K = 125 / quad bursts).
 464  * For a simpler initialization, 15.6 us is used instead.
 465  *
 466  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 467  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 468  */
 469 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 470 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 471
 472 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 473 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 474 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 475
 476 /*
 477  * MAMR settings for SDRAM
 478  */
 479
 480 /* 8 column SDRAM */
 481 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 482                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 483                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 484
 485 /* 9 column SDRAM */
 486 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 487                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 488                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 489
 490 /*
 491  * Internal Definitions
 492  *
 493  * Boot Flags
 494  */
 495 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 496 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 497
 498 #define CONFIG_ARTOS                    /* include ARTOS support */
 499
 500 #define CONFIG_LAST_STAGE_INIT          /* needed to reset the damn phys */
 501
 502 /***********************************************************************************************************
 503
 504    Pin definitions:
 505
 506  +------+----------------+--------+------------------------------------------------------------
 507  |  #   | Name           | Type   | Comment
 508  +------+----------------+--------+------------------------------------------------------------
 509  | PA3  | OK_ETH_3V      | Input  | CISCO Ethernet power OK
 510  |      |                |        | (NetRoute: FEC1, TA: FEC2) (0=power OK)
 511  | PA6  | P_VCCD1        | Output | TPS2211A PCMCIA
 512  | PA7  | DCL1_3V        | Periph | IDL1 PCM clock
 513  | PA8  | DSP_DR1        | Periph | IDL1 PCM Data Rx
 514  | PA9  | L1TXDA         | Periph | IDL1 PCM Data Tx
 515  | PA10 | P_VCCD0        | Output | TPS2211A PCMCIA
 516  | PA12 | P_SHDN         | Output | TPS2211A PCMCIA
 517  | PA13 | ETH_LOOP       | Output | CISCO Loopback remote power
 518  |      |                |        | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
 519  | PA14 | P_VPPD0        | Output | TPS2211A PCMCIA
 520  | PA15 | P_VPPD1        | Output | TPS2211A PCMCIA
 521  | PB14 | SPIEN_FXO      | Output | SPI CS for FXO daughter-board
 522  | PB15 | SPIEN_S1       | Output | SPI CS for S-interface 1 (NetRoute only)
 523  | PB16 | DREQ1          | Output | D channel request for S-interface chip 1.
 524  | PB17 | L1ST3          | Periph | IDL1 timeslot enable signal for PPC
 525  | PB18 | L1ST2          | Periph | IDL1 timeslot enable signal for PPC
 526  | PB19 | SPIEN_S2       | Output | SPI CS for S-interface 2 (NetRoute only)
 527  | PB20 | SPIEN_SEEPROM  | Output | SPI CS for serial eeprom
 528  | PB21 | LEDIO          | Output | Led mode indication for PHY
 529  | PB22 | UART_CTS       | Input  | UART CTS
 530  | PB23 | UART_RTS       | Output | UART RTS
 531  | PB24 | UART_RX        | Periph | UART Data Rx
 532  | PB25 | UART_TX        | Periph | UART Data Tx
 533  | PB26 | RMII-MDC       | Periph | Free for future use (MII mgt clock)
 534  | PB27 | RMII-MDIO      | Periph | Free for future use (MII mgt data)
 535  | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
 536  | PB29 | SPI_TXD        | Output | SPI Data Tx
 537  | PB30 | SPI_CLK        | Output | SPI Clock
 538  | PB31 | RMII1-REFCLK   | Periph | RMII reference clock for FEC1
 539  | PC4  | PHY1_LINK      | Input  | PHY link state FEC1 (interrupt)
 540  | PC5  | PHY2_LINK      | Input  | PHY link state FEC2 (interrupt)
 541  | PC6  | RMII1-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
 542  | PC7  | RMII2-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
 543  | PC8  | P_OC           | Input  | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
 544  | PC9  | COM_HOOK1      | Input  | Codec interrupt chip #1 (interrupt)
 545  | PC10 | COM_HOOK2      | Input  | Codec interrupt chip #2 (interrupt)
 546  | PC11 | COM_HOOK4      | Input  | Codec interrupt chip #4 (interrupt)
 547  | PC12 | COM_HOOK3      | Input  | Codec interrupt chip #3 (interrupt)
 548  | PC13 | F_RY_BY        | Input  | NAND ready signal (interrupt)
 549  | PC14 | FAN_OK         | Input  | Fan status signal (interrupt) (1=OK)
 550  | PC15 | PC15_DIRECT0   | Periph | PCMCIA DMA request.
 551  | PD3  | F_ALE          | Output | NAND
 552  | PD4  | F_CLE          | Output | NAND
 553  | PD5  | F_CE           | Output | NAND
 554  | PD6  | DSP_INT        | Output | DSP debug interrupt
 555  | PD7  | DSP_RESET      | Output | DSP reset
 556  | PD8  | RMII_MDC       | Periph | MII mgt clock
 557  | PD9  | SPIEN_C1       | Output | SPI CS for codec #1
 558  | PD10 | SPIEN_C2       | Output | SPI CS for codec #2
 559  | PD11 | SPIEN_C3       | Output | SPI CS for codec #3
 560  | PD12 | FSC2           | Periph | IDL2 frame sync
 561  | PD13 | DGRANT2        | Input  | D channel grant from S #2
 562  | PD14 | SPIEN_C4       | Output | SPI CS for codec #4
 563  | PD15 | TP700          | Output | Testpoint for software debugging
 564  | PE14 | RMII2-TXD0     | Periph | FEC2 transmit data
 565  | PE15 | RMII2-TXD1     | Periph | FEC2 transmit data
 566  | PE16 | RMII2-REFCLK   | Periph | TA: RMII ref clock for
 567  |      | DCL2           | Periph | NetRoute: PCM clock #2
 568  | PE17 | TP703          | Output | Testpoint for software debugging
 569  | PE18 | DGRANT1        | Input  |  D channel grant from S #1
 570  | PE19 | RMII2-TXEN     | Periph | TA: FEC2 tx enable
 571  |      | PCM2OUT        | Periph | NetRoute: Tx data for IDL2
 572  | PE20 | FSC1           | Periph | IDL1 frame sync
 573  | PE21 | RMII2-RXD0     | Periph | FEC2 receive data
 574  | PE22 | RMII2-RXD1     | Periph | FEC2 receive data
 575  | PE23 | L1ST1          | Periph | IDL1 timeslot enable signal for PPC
 576  | PE24 | U-N1           | Output | Select user/network for S #1 (0=user)
 577  | PE25 | U-N2           | Output | Select user/network for S #2 (0=user)
 578  | PE26 | RMII2-RXDV     | Periph | FEC2 valid
 579  | PE27 | DREQ2          | Output | D channel request for S #2.
 580  | PE28 | FPGA_DONE      | Input  | FPGA done signal
 581  | PE29 | FPGA_INIT      | Output | FPGA init signal
 582  | PE30 | UDOUT2_3V      | Input  | IDL2 PCM input
 583  | PE31 |                |        | Free
 584  +------+----------------+--------+---------------------------------------------------
 585
 586  Chip selects:
 587
 588  +------+----------------+------------------------------------------------------------
 589  |  #   | Name           | Comment
 590  +------+----------------+------------------------------------------------------------
 591  | CS0  | CS0            | Boot flash
 592  | CS1  | CS_FLASH       | NAND flash
 593  | CS2  | CS_DSP         | DSP
 594  | CS3  | DCS_DRAM       | DRAM
 595  | CS4  | CS_ER1         | External output register
 596  +------+----------------+------------------------------------------------------------
 597
 598  Interrupts:
 599
 600  +------+----------------+------------------------------------------------------------
 601  |  #   | Name           | Comment
 602  +------+----------------+------------------------------------------------------------
 603  | IRQ1 | UINTER_3V      | S interupt chips interrupt (common)
 604  | IRQ3 | IRQ_DSP        | DSP interrupt
 605  | IRQ4 | IRQ_DSP1       | Extra DSP interrupt
 606  +------+----------------+------------------------------------------------------------
 607
 608 *************************************************************************************************/
 609
 610 #define DSP_SIZE        0x00010000      /* 64K */
 611 #define NAND_SIZE       0x00010000      /* 64K */
 612 #define ER_SIZE         0x00010000      /* 64K */
 613 #define DUMMY_SIZE      0x00010000      /* 64K */
 614
 615 #define DSP_BASE        0xF1000000
 616 #define NAND_BASE       0xF1010000
 617 #define ER_BASE         0xF1020000
 618 #define DUMMY_BASE      0xF1FF0000
 619
 620 /****************************************************************/
 621
 622 /* NAND */
 623 #define CFG_NAND_LEGACY
 624 #define CFG_NAND_BASE                   NAND_BASE
 625 #define CONFIG_MTD_NAND_VERIFY_WRITE
 626 #define CONFIG_MTD_NAND_UNSAFE
 627
 628 #define CFG_MAX_NAND_DEVICE             1
 629 /* #define NAND_NO_RB */
 630
 631 #define SECTORSIZE              512
 632 #define ADDR_COLUMN             1
 633 #define ADDR_PAGE               2
 634 #define ADDR_COLUMN_PAGE        3
 635 #define NAND_ChipID_UNKNOWN     0x00
 636 #define NAND_MAX_FLOORS         1
 637 #define NAND_MAX_CHIPS          1
 638
 639 /* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
 640 #define NAND_DISABLE_CE(nand) \
 641         do { \
 642                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 5)); \
 643         } while(0)
 644
 645 #define NAND_ENABLE_CE(nand) \
 646         do { \
 647                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
 648         } while(0)
 649
 650 #define NAND_CTL_CLRALE(nandptr) \
 651         do { \
 652                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
 653         } while(0)
 654
 655 #define NAND_CTL_SETALE(nandptr) \
 656         do { \
 657                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 3)); \
 658         } while(0)
 659
 660 #define NAND_CTL_CLRCLE(nandptr) \
 661         do { \
 662                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
 663         } while(0)
 664
 665 #define NAND_CTL_SETCLE(nandptr) \
 666         do { \
 667                 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  (1 << (15 - 4)); \
 668         } while(0)
 669
 670 #ifndef NAND_NO_RB
 671 #define NAND_WAIT_READY(nand) \
 672         do { \
 673                 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
 674                         WATCHDOG_RESET(); \
 675                 } \
 676         } while (0)
 677 #else
 678 #define NAND_WAIT_READY(nand) udelay(12)
 679 #endif
 680
 681 #define WRITE_NAND_COMMAND(d, adr) \
 682         do { \
 683                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 684         } while(0)
 685
 686 #define WRITE_NAND_ADDRESS(d, adr) \
 687         do { \
 688                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 689         } while(0)
 690
 691 #define WRITE_NAND(d, adr) \
 692         do { \
 693                 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
 694         } while(0)
 695
 696 #define READ_NAND(adr) \
 697         ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
 698
 699 #define CONFIG_JFFS2_NAND       1                       /* jffs2 on nand support */
 700 #define NAND_CACHE_PAGES        16                      /* size of nand cache in 512 bytes pages */
 701
 702 /*
 703  * JFFS2 partitions
 704  *
 705  */
 706 /* No command line, one static partition, whole device */
 707 #undef CONFIG_JFFS2_CMDLINE
 708 #define CONFIG_JFFS2_DEV                "nand0"
 709 #define CONFIG_JFFS2_PART_SIZE          0x00100000
 710 #define CONFIG_JFFS2_PART_OFFSET        0x00200000
 711
 712 /* mtdparts command line support */
 713 /* Note: fake mtd_id used, no linux mtd map file */
 714 /*
 715 #define CONFIG_JFFS2_CMDLINE
 716 #define MTDIDS_DEFAULT          "nand0=netta-nand"
 717 #define MTDPARTS_DEFAULT        "mtdparts=netta-nand:1m@2m(jffs2)"
 718 */
 719
 720 /*****************************************************************************/
 721
 722 #define CFG_DIRECT_FLASH_TFTP
 723 #define CFG_DIRECT_NAND_TFTP
 724
 725 /*****************************************************************************/
 726
 727 #if 1
 728 /*-----------------------------------------------------------------------
 729  * PCMCIA stuff
 730  *-----------------------------------------------------------------------
 731  */
 732
 733 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 734 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 735 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 736 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 737 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 738 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 739 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 740 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 741
 742 /*-----------------------------------------------------------------------
 743  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 744  *-----------------------------------------------------------------------
 745  */
 746
 747 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 748
 749 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 750 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 751 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 752
 753 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 754 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 755
 756 #define CFG_ATA_IDE0_OFFSET     0x0000
 757
 758 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 759
 760 /* Offset for data I/O                  */
 761 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 762
 763 /* Offset for normal register accesses  */
 764 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 765
 766 /* Offset for alternate registers       */
 767 #define CFG_ATA_ALT_OFFSET      0x0100
 768
 769 #define CONFIG_MAC_PARTITION
 770 #define CONFIG_DOS_PARTITION
 771 #endif
 772
 773 /*************************************************************************************************/
 774
 775 #define CONFIG_CDP_DEVICE_ID            20
 776 #define CONFIG_CDP_DEVICE_ID_PREFIX     "NT"    /* netta */
 777 #define CONFIG_CDP_PORT_ID              "eth%d"
 778 #define CONFIG_CDP_CAPABILITIES         0x00000010
 779 #define CONFIG_CDP_VERSION              "u-boot 1.0" " " __DATE__ " " __TIME__
 780 #define CONFIG_CDP_PLATFORM             "Intracom NetTA"
 781 #define CONFIG_CDP_TRIGGER              0x20020001
 782 #define CONFIG_CDP_POWER_CONSUMPTION    4300    /* 90 mA @ 48V */
 783 #define CONFIG_CDP_APPLIANCE_VLAN_TYPE  0x01    /* ipphone? */
 784
 785 /*************************************************************************************************/
 786
 787 #define CONFIG_AUTO_COMPLETE    1
 788
 789 /*************************************************************************************************/
 790
 791 #define CONFIG_CRC32_VERIFY     1
 792
 793 /*************************************************************************************************/
 794
 795 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE       1
 796
 797 /*************************************************************************************************/
 798
 799 #endif  /* __CONFIG_H */