include/configs/DB64460.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /* This define must be before the core.h include */
  32 #define CONFIG_DB64460          1       /* this is an DB64460 board     */
  33
  34 #ifndef __ASSEMBLY__
  35 #include "../board/Marvell/include/core.h"
  36 #endif
  37
  38 /*-----------------------------------------------------*/
  39 /*    #include "../board/db64460/local.h"             */
  40 #ifndef __LOCAL_H
  41 #define __LOCAL_H
  42
  43 #define CONFIG_ETHADDR          64:46:00:00:00:01
  44 #define CONFIG_HAS_ETH1
  45 #define CONFIG_ETH1ADDR         64:46:00:00:00:02
  46 #define CONFIG_HAS_ETH2
  47 #define CONFIG_ETH2ADDR         64:46:00:00:00:03
  48
  49 #define CONFIG_ENV_OVERWRITE
  50 #endif  /* __CONFIG_H */
  51
  52 /*
  53  * High Level Configuration Options
  54  * (easy to change)
  55  */
  56
  57 #define CONFIG_74xx                     /* we have a 750FX (override local.h) */
  58
  59 #define CONFIG_DB64460          1       /* this is an DB64460 board     */
  60
  61 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115000    */
  62 /*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
  63         DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
  64         so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
  65         see sdram_init.c   */
  66 #undef CONFIG_ECC        /* enable ECC support */
  67 #define CONFIG_MV64460_ECC
  68
  69 /* which initialization functions to call for this board */
  70 #define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
  71 #define CONFIG_BOARD_EARLY_INIT_F
  72
  73 #define CFG_BOARD_NAME          "DB64460"
  74 #define CONFIG_IDENT_STRING     "Marvell DB64460 (1.0)"
  75
  76 /*#define CFG_HUSH_PARSER */
  77 #undef CFG_HUSH_PARSER
  78
  79 #define CFG_PROMPT_HUSH_PS2     "> "
  80
  81 /*
  82  * The following defines let you select what serial you want to use
  83  * for your console driver.
  84  *
  85  * what to do:
  86  * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
  87  * cable onto the second DUART channel, change the CFG_DUART port from 1
  88  * to 0 below.
  89  *
  90  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  91  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  92  */
  93
  94 #define CONFIG_MPSC_PORT        0
  95
  96 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
  97 #define CONFIG_NET_MULTI
  98 #define MV_ETH_DEVS 3
  99
 100 /* #undef CONFIG_ETHER_PORT_MII  */
 101 #if 0
 102 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 103 #else
 104 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds     */
 105 #endif
 106 #define CONFIG_ZERO_BOOTDELAY_CHECK
 107
 108
 109 #undef  CONFIG_BOOTARGS
 110 /*#define CONFIG_PREBOOT        "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
 111
 112 /* ronen - autoboot using tftp */
 113 #if (CONFIG_BOOTDELAY >= 0)
 114 #define CONFIG_BOOTCOMMAND      "tftpboot 0x400000 uImage;\
 115  setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
 116  ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
 117
 118 #define CONFIG_BOOTARGS "console=ttyS0,115200"
 119
 120 #endif
 121
 122 /* ronen - the u-boot.bin should be ~0x30000 bytes */
 123 #define CONFIG_EXTRA_ENV_SETTINGS \
 124      "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
 125 cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
 126       "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
 127 cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
 128       "bootargs_root=root=/dev/nfs rw\0" \
 129       "bootargs_end=:::DB64460:eth0:none \0"\
 130       "ethprime=mv_enet0\0"\
 131       "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
 132 ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 133
 134 /* --------------------------------------------------------------------------------------------------------------- */
 135 /* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
 136
 137 #define CONFIG_IPADDR           10.2.40.90
 138
 139 #define CONFIG_SERIAL           "No. 1"
 140 #define CONFIG_SERVERIP         10.2.1.126
 141 #define CONFIG_ROOTPATH /mnt/yellow_dog_mini
 142
 143
 144 #define CONFIG_TESTDRAMDATA     y
 145 #define CONFIG_TESTDRAMADDRESS  n
 146 #define CONFIG_TESETDRAMWALK    n
 147
 148 /* --------------------------------------------------------------------------------------------------------------- */
 149
 150 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 151 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes       */
 152
 153 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 154 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
 155
 156 /*
 157  * BOOTP options
 158  */
 159 #define CONFIG_BOOTP_SUBNETMASK
 160 #define CONFIG_BOOTP_GATEWAY
 161 #define CONFIG_BOOTP_HOSTNAME
 162 #define CONFIG_BOOTP_BOOTPATH
 163 #define CONFIG_BOOTP_BOOTFILESIZE
 164
 165
 166 /*
 167  * JFFS2 partitions
 168  *
 169  */
 170 /* No command line, one static partition, whole device */
 171 #undef CONFIG_JFFS2_CMDLINE
 172 #define CONFIG_JFFS2_DEV                "nor1"
 173 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 174 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 175
 176 /* mtdparts command line support */
 177
 178 /* Use first bank for JFFS2, second bank contains U-Boot.
 179  *
 180  * Note: fake mtd_id's used, no linux mtd map file.
 181  */
 182 /*
 183 #define CONFIG_JFFS2_CMDLINE
 184 #define MTDIDS_DEFAULT          "nor1=db64460-1"
 185 #define MTDPARTS_DEFAULT        "mtdparts=db64460-1:-(jffs2)"
 186 */
 187
 188
 189 /*
 190  * Command line configuration.
 191  */
 192 #include <config_cmd_default.h>
 193
 194 #define CONFIG_CMD_ASKENV
 195 #define CONFIG_CMD_I2C
 196 #define CONFIG_CMD_EEPROM
 197 #define CONFIG_CMD_CACHE
 198 #define CONFIG_CMD_JFFS2
 199 #define CONFIG_CMD_PCI
 200 #define CONFIG_CMD_NET
 201
 202
 203 /*
 204  * Miscellaneous configurable options
 205  */
 206 #define CFG_I2C_EEPROM_ADDR_LEN 1
 207 #define CFG_I2C_MULTI_EEPROMS
 208 #define CFG_I2C_SPEED   40000           /* I2C speed default */
 209
 210 /* #define CFG_GT_DUAL_CPU       also for JTAG even with one cpu */
 211 #define CFG_LONGHELP                    /* undef to save memory         */
 212 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 213 #if defined(CONFIG_CMD_KGDB)
 214 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 215 #else
 216 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 217 #endif
 218 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 219 #define CFG_MAXARGS     16              /* max number of command args   */
 220 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 221
 222 /*#define CFG_MEMTEST_START     0x00400000       memtest works on       */
 223 /*#define CFG_MEMTEST_END               0x00C00000       4 ... 12 MB in DRAM    */
 224 /*#define CFG_MEMTEST_END               0x07c00000       4 ... 124 MB in DRAM   */
 225
 226 /*
 227 #define CFG_DRAM_TEST
 228  * DRAM tests
 229  *   CFG_DRAM_TEST - enables the following tests.
 230  *
 231  *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
 232  *                        Environment variable 'test_dram_data' must be
 233  *                        set to 'y'.
 234  *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
 235  *                        addressable. Environment variable
 236  *                        'test_dram_address' must be set to 'y'.
 237  *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 238  *                        This test takes about 6 minutes to test 64 MB.
 239  *                        Environment variable 'test_dram_walk' must be
 240  *                        set to 'y'.
 241  */
 242 #define CFG_DRAM_TEST
 243 #if defined(CFG_DRAM_TEST)
 244 #define CFG_MEMTEST_START               0x00400000      /* memtest works on     */
 245 /* #define CFG_MEMTEST_END              0x00C00000       4 ... 12 MB in DRAM    */
 246 #define CFG_MEMTEST_END         0x07c00000      /* 4 ... 124 MB in DRAM */
 247 #define CFG_DRAM_TEST_DATA
 248 #define CFG_DRAM_TEST_ADDRESS
 249 #define CFG_DRAM_TEST_WALK
 250 #endif /* CFG_DRAM_TEST */
 251
 252 #undef CONFIG_DISPLAY_MEMMAP            /* at the end of the bootprocess show the memory map */
 253 #undef CFG_DISPLAY_DIMM_SPD_CONTENT     /* show SPD content during boot */
 254
 255 #define CFG_LOAD_ADDR           0x00400000      /* default load address */
 256
 257 #define CFG_HZ                  1000            /* decr freq: 1ms ticks */
 258 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
 259 #define CFG_BUS_HZ              133000000       /* 133 MHz (CPU = 5*Bus = 666MHz)               */
 260 #define CFG_BUS_CLK             CFG_BUS_HZ
 261
 262 #define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
 263 #define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
 264
 265 /*ronen - this is the Tclk (MV64460 core) */
 266 #define CFG_TCLK                133000000
 267
 268
 269 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 270
 271 #define CFG_750FX_HID0          0x8000c084
 272 #define CFG_750FX_HID1          0x54800000
 273 #define CFG_750FX_HID2          0x00000000
 274
 275 /*
 276  * Low Level Configuration Settings
 277  * (address mappings, register initial values, etc.)
 278  * You should know what you are doing if you make changes here.
 279  */
 280
 281 /*-----------------------------------------------------------------------
 282  * Definitions for initial stack pointer and data area
 283  */
 284
 285 /*
 286  * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
 287  * To an unused memory region. The stack will remain in cache until RAM
 288  * is initialized
 289 */
 290 #define CFG_INIT_RAM_LOCK
 291 #define CFG_INIT_RAM_ADDR       0x40000000 /* unused memory region */
 292 #define CFG_INIT_RAM_END        0x1000
 293 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for init data */
 294 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 295
 296 #define RELOCATE_INTERNAL_RAM_ADDR
 297 #ifdef RELOCATE_INTERNAL_RAM_ADDR
 298         #define CFG_INTERNAL_RAM_ADDR   0xf8000000
 299 #endif
 300
 301 /*-----------------------------------------------------------------------
 302  * Start addresses for the final memory configuration
 303  * (Set up by the startup code)
 304  * Please note that CFG_SDRAM_BASE _must_ start at 0
 305  */
 306 #define CFG_SDRAM_BASE          0x00000000
 307 /* Dummies for BAT 4-7 */
 308 #define CFG_SDRAM1_BASE         0x10000000      /* each 256 MByte */
 309 #define CFG_SDRAM2_BASE         0x20000000
 310 #define CFG_SDRAM3_BASE         0x30000000
 311 #define CFG_SDRAM4_BASE         0x40000000
 312 #define CFG_FLASH_BASE                  0xfff00000
 313
 314 #define CFG_DFL_BOOTCS_BASE     0xff800000
 315 #define CONFIG_VERY_BIG_RAM             /* we will use up to 256M memory for cause we are short of BATS*/
 316
 317 #define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
 318 #define UART_BASE_BOOTM       0xfbb00000 /* in order to be sync with the kernel parameters. */
 319 #define PCI0_IO_BASE_BOOTM    0xfd000000
 320
 321 #define CFG_RESET_ADDRESS               0xfff00100
 322 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 323 #define CFG_MONITOR_BASE                CFG_FLASH_BASE
 324 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc */
 325
 326 /* areas to map different things with the GT in physical space */
 327 #define CFG_DRAM_BANKS          4
 328
 329 /* What to put in the bats. */
 330 #define CFG_MISC_REGION_BASE    0xf0000000
 331
 332 /* Peripheral Device section */
 333
 334 /*******************************************************/
 335 /* We have on the db64460 Board :                  */
 336 /* GT-Chipset Register Area                             */
 337 /* GT-Chipset internal SRAM 256k                    */
 338 /* SRAM on external device module                  */
 339 /* Real time clock on external device module      */
 340 /* dobble UART on external device module         */
 341 /* Data flash on external device module             */
 342 /* Boot flash on external device module             */
 343 /*******************************************************/
 344 #define CFG_DFL_GT_REGS         0x14000000                              /* boot time GT_REGS */
 345 #define  CFG_DB64460_RESET_ADDR 0x14000000                              /* After power on Reset the DB64460 is here */
 346
 347 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 348 #define CFG_GT_REGS             0xf1000000                              /* GT Registers will be mapped here */
 349 #define CFG_DEV_BASE            0xfc000000                              /* GT Devices CS start here */
 350
 351 #define CFG_DEV0_SPACE          CFG_DEV_BASE                            /* DEV_CS0 device modul sram */
 352 #define CFG_DEV1_SPACE          (CFG_DEV0_SPACE + CFG_DEV0_SIZE)        /* DEV_CS1 device modul real time clock (rtc) */
 353 #define CFG_DEV2_SPACE          (CFG_DEV1_SPACE + CFG_DEV1_SIZE)        /* DEV_CS2 device modul doubel uart (duart) */
 354 #define CFG_DEV3_SPACE          (CFG_DEV2_SPACE + CFG_DEV2_SIZE)        /* DEV_CS3 device modul large flash */
 355
 356 #define CFG_DEV0_SIZE            _8M                                    /* db64460 sram  @ 0xfc00.0000 */
 357 #define CFG_DEV1_SIZE            _8M                                    /* db64460 rtc   @ 0xfc80.0000 */
 358 #define CFG_DEV2_SIZE           _16M                                    /* db64460 duart @ 0xfd00.0000 */
 359 #define CFG_DEV3_SIZE           _16M                                    /* db64460 flash @ 0xfe00.0000 */
 360 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 361
 362 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
 363 #define CFG_DEV0_PAR            0x8FEFFFFF                              /* 32Bit  sram */
 364 #define CFG_DEV1_PAR            0x8FCFFFFF                              /* 8Bit  rtc */
 365 #define CFG_DEV2_PAR            0x8FCFFFFF                              /* 8Bit duart */
 366 #define CFG_8BIT_BOOT_PAR       0x8FCFFFFF                              /* 8Bit flash */
 367 #define CFG_32BIT_BOOT_PAR      0x8FEFFFFF                              /* 32Bit flash */
 368
 369         /*   c    4    a      8     2     4    1      c         */
 370         /* 33 22|2222|22 22|111 1|11 11|1 1  |    |             */
 371         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210       */
 372         /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100       */
 373         /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4        */
 374
 375
 376 /* ronen - update MPP Control MV64460*/
 377 #define CFG_MPP_CONTROL_0       0x02222222
 378 #define CFG_MPP_CONTROL_1       0x11333011
 379 #define CFG_MPP_CONTROL_2       0x40431111
 380 #define CFG_MPP_CONTROL_3       0x00000044
 381
 382 /*# define CFG_SERIAL_PORT_MUX  0x00000102       0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
 383
 384
 385 # define CFG_GPP_LEVEL_CONTROL  0x2c600000      /* 1111 1001 0000 1111 1100 0000 0000 0000*/
 386                                                         /* gpp[31]              gpp[30]         gpp[29]         gpp[28] */
 387                                 /* gpp[27]                      gpp[24]*/
 388                                                         /* gpp[19:14] */
 389
 390 /* setup new config_value for MV64460 DDR-RAM !! */
 391 # define CFG_SDRAM_CONFIG       0x58200400      /* 0x1400  copied from Dink32 bzw. VxWorks*/
 392
 393 #define CFG_DUART_IO            CFG_DEV2_SPACE
 394 #define CFG_DUART_CHAN          1               /* channel to use for console */
 395 #define CFG_INIT_CHAN1
 396 #define CFG_INIT_CHAN2
 397
 398 #define SRAM_BASE               CFG_DEV0_SPACE
 399 #define SRAM_SIZE               0x00100000              /* 1 MB of sram */
 400
 401
 402 /*-----------------------------------------------------------------------
 403  * PCI stuff
 404  *-----------------------------------------------------------------------
 405  */
 406
 407 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 408 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 409 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 410
 411 #define CONFIG_PCI                      /* include pci support          */
 412 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 413 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 414 #define CONFIG_EEPRO100                 /* ronen - Support for Intel 82557/82559/82559ER chips */
 415
 416 /* PCI MEMORY MAP section */
 417 #define CFG_PCI0_MEM_BASE       0x80000000
 418 #define CFG_PCI0_MEM_SIZE       _128M
 419 #define CFG_PCI1_MEM_BASE       0x88000000
 420 #define CFG_PCI1_MEM_SIZE       _128M
 421
 422 #define CFG_PCI0_0_MEM_SPACE    (CFG_PCI0_MEM_BASE)
 423 #define CFG_PCI1_0_MEM_SPACE    (CFG_PCI1_MEM_BASE)
 424
 425 /* PCI I/O MAP section */
 426 #define CFG_PCI0_IO_BASE        0xfa000000
 427 #define CFG_PCI0_IO_SIZE        _16M
 428 #define CFG_PCI1_IO_BASE        0xfb000000
 429 #define CFG_PCI1_IO_SIZE        _16M
 430
 431 #define CFG_PCI0_IO_SPACE       (CFG_PCI0_IO_BASE)
 432 #define CFG_PCI0_IO_SPACE_PCI   (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
 433 #define CFG_PCI1_IO_SPACE       (CFG_PCI1_IO_BASE)
 434 #define CFG_PCI1_IO_SPACE_PCI   (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
 435
 436 #if defined (CONFIG_750CX)
 437 #define CFG_PCI_IDSEL 0x0
 438 #else
 439 #define CFG_PCI_IDSEL 0x30
 440 #endif
 441 /*----------------------------------------------------------------------
 442  * Initial BAT mappings
 443  */
 444
 445 /* NOTES:
 446  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 447  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 448  */
 449
 450 /* SDRAM */
 451 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 452 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 453 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 454 #define CFG_DBAT0U CFG_IBAT0U
 455
 456 /* init ram */
 457 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 458 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
 459 #define CFG_DBAT1L  CFG_IBAT1L
 460 #define CFG_DBAT1U  CFG_IBAT1U
 461
 462 /* PCI0, PCI1 in one BAT */
 463 #define CFG_IBAT2L BATL_NO_ACCESS
 464 #define CFG_IBAT2U CFG_DBAT2U
 465 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 466 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 467
 468 /* GT regs, bootrom, all the devices, PCI I/O */
 469 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 470 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 471 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 472 #define CFG_DBAT3U CFG_IBAT3U
 473
 474 /* I2C addresses for the two DIMM SPD chips */
 475 #define DIMM0_I2C_ADDR  0x56
 476 #define DIMM1_I2C_ADDR  0x54
 477
 478 /*
 479  * For booting Linux, the board info and command line data
 480  * have to be in the first 8 MB of memory, since this is
 481  * the maximum mapped by the Linux kernel during initialization.
 482  */
 483 #define CFG_BOOTMAPSZ           (8<<20) /* Initial Memory map for Linux */
 484
 485 /*-----------------------------------------------------------------------
 486  * FLASH organization
 487  */
 488 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks   */
 489 #define CFG_MAX_FLASH_SECT      67      /* max number of sectors on one chip */
 490
 491 #define CFG_EXTRA_FLASH_DEVICE  DEVICE3 /* extra flash at device 3 */
 492 #define CFG_EXTRA_FLASH_WIDTH   4       /* 32 bit */
 493 #define CFG_BOOT_FLASH_WIDTH    1       /* 8 bit */
 494
 495 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 496 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 497 #define CFG_FLASH_LOCK_TOUT     500     /* Timeout for Flash Lock (in ms) */
 498 #define CFG_FLASH_CFI           1
 499
 500 #define CFG_ENV_IS_IN_FLASH     1
 501 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector */
 502 #define CFG_ENV_SECT_SIZE       0x10000
 503 #define CFG_ENV_ADDR          0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
 504 /* #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
 505
 506 /*-----------------------------------------------------------------------
 507  * Cache Configuration
 508  */
 509 #define CFG_CACHELINE_SIZE      32      /* For all MPC74xx CPUs          */
 510 #if defined(CONFIG_CMD_KGDB)
 511 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 512 #endif
 513
 514 /*-----------------------------------------------------------------------
 515  * L2CR setup -- make sure this is right for your board!
 516  * look in include/mpc74xx.h for the defines used here
 517  */
 518
 519 #define CFG_L2
 520
 521
 522 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 523 #define L2_INIT 0
 524 #else
 525
 526 #define L2_INIT         0
 527 /*
 528 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 529                         L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 530 */
 531 #endif
 532
 533 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 534
 535 /*
 536  * Internal Definitions
 537  *
 538  * Boot Flags
 539  */
 540 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 541 #define BOOTFLAG_WARM   0x02            /* Software reboot                  */
 542
 543 #define CFG_BOARD_ASM_INIT      1
 544
 545 #endif  /* __CONFIG_H */