include/asm-ppc/mmu.h

   1 /*
   2  * PowerPC memory management structures
   3  */
   4
   5 #ifndef _PPC_MMU_H_
   6 #define _PPC_MMU_H_
   7
   8 #include <linux/config.h>
   9
  10 #ifndef __ASSEMBLY__
  11 /* Hardware Page Table Entry */
  12 typedef struct _PTE {
  13 #ifdef CONFIG_PPC64BRIDGE
  14         unsigned long long vsid:52;
  15         unsigned long api:5;
  16         unsigned long :5;
  17         unsigned long h:1;
  18         unsigned long v:1;
  19         unsigned long long rpn:52;
  20 #else /* CONFIG_PPC64BRIDGE */
  21         unsigned long v:1;      /* Entry is valid */
  22         unsigned long vsid:24;  /* Virtual segment identifier */
  23         unsigned long h:1;      /* Hash algorithm indicator */
  24         unsigned long api:6;    /* Abbreviated page index */
  25         unsigned long rpn:20;   /* Real (physical) page number */
  26 #endif /* CONFIG_PPC64BRIDGE */
  27         unsigned long    :3;    /* Unused */
  28         unsigned long r:1;      /* Referenced */
  29         unsigned long c:1;      /* Changed */
  30         unsigned long w:1;      /* Write-thru cache mode */
  31         unsigned long i:1;      /* Cache inhibited */
  32         unsigned long m:1;      /* Memory coherence */
  33         unsigned long g:1;      /* Guarded */
  34         unsigned long  :1;      /* Unused */
  35         unsigned long pp:2;     /* Page protection */
  36 } PTE;
  37
  38 /* Values for PP (assumes Ks=0, Kp=1) */
  39 #define PP_RWXX 0       /* Supervisor read/write, User none */
  40 #define PP_RWRX 1       /* Supervisor read/write, User read */
  41 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
  42 #define PP_RXRX 3       /* Supervisor read,       User read */
  43
  44 /* Segment Register */
  45 typedef struct _SEGREG {
  46         unsigned long t:1;      /* Normal or I/O  type */
  47         unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
  48         unsigned long kp:1;     /* User 'key' (normally 1) */
  49         unsigned long n:1;      /* No-execute */
  50         unsigned long :4;       /* Unused */
  51         unsigned long vsid:24;  /* Virtual Segment Identifier */
  52 } SEGREG;
  53
  54 /* Block Address Translation (BAT) Registers */
  55 typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
  56         unsigned long bepi:15;  /* Effective page index (virtual address) */
  57         unsigned long :8;       /* unused */
  58         unsigned long w:1;
  59         unsigned long i:1;      /* Cache inhibit */
  60         unsigned long m:1;      /* Memory coherence */
  61         unsigned long ks:1;     /* Supervisor key (normally 0) */
  62         unsigned long kp:1;     /* User key (normally 1) */
  63         unsigned long pp:2;     /* Page access protections */
  64 } P601_BATU;
  65
  66 typedef struct _BATU {          /* Upper part of BAT (all except 601) */
  67 #ifdef CONFIG_PPC64BRIDGE
  68         unsigned long long bepi:47;
  69 #else /* CONFIG_PPC64BRIDGE */
  70         unsigned long bepi:15;  /* Effective page index (virtual address) */
  71 #endif /* CONFIG_PPC64BRIDGE */
  72         unsigned long :4;       /* Unused */
  73         unsigned long bl:11;    /* Block size mask */
  74         unsigned long vs:1;     /* Supervisor valid */
  75         unsigned long vp:1;     /* User valid */
  76 } BATU;
  77
  78 typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
  79         unsigned long brpn:15;  /* Real page index (physical address) */
  80         unsigned long :10;      /* Unused */
  81         unsigned long v:1;      /* Valid bit */
  82         unsigned long bl:6;     /* Block size mask */
  83 } P601_BATL;
  84
  85 typedef struct _BATL {          /* Lower part of BAT (all except 601) */
  86 #ifdef CONFIG_PPC64BRIDGE
  87         unsigned long long brpn:47;
  88 #else /* CONFIG_PPC64BRIDGE */
  89         unsigned long brpn:15;  /* Real page index (physical address) */
  90 #endif /* CONFIG_PPC64BRIDGE */
  91         unsigned long :10;      /* Unused */
  92         unsigned long w:1;      /* Write-thru cache */
  93         unsigned long i:1;      /* Cache inhibit */
  94         unsigned long m:1;      /* Memory coherence */
  95         unsigned long g:1;      /* Guarded (MBZ in IBAT) */
  96         unsigned long :1;       /* Unused */
  97         unsigned long pp:2;     /* Page access protections */
  98 } BATL;
  99
 100 typedef struct _BAT {
 101         BATU batu;              /* Upper register */
 102         BATL batl;              /* Lower register */
 103 } BAT;
 104
 105 typedef struct _P601_BAT {
 106         P601_BATU batu;         /* Upper register */
 107         P601_BATL batl;         /* Lower register */
 108 } P601_BAT;
 109
 110 /*
 111  * Simulated two-level MMU.  This structure is used by the kernel
 112  * to keep track of MMU mappings and is used to update/maintain
 113  * the hardware HASH table which is really a cache of mappings.
 114  *
 115  * The simulated structures mimic the hardware available on other
 116  * platforms, notably the 80x86 and 680x0.
 117  */
 118
 119 typedef struct _pte {
 120         unsigned long page_num:20;
 121         unsigned long flags:12;         /* Page flags (some unused bits) */
 122 } pte;
 123
 124 #define PD_SHIFT (10+12)                /* Page directory */
 125 #define PD_MASK  0x02FF
 126 #define PT_SHIFT (12)                   /* Page Table */
 127 #define PT_MASK  0x02FF
 128 #define PG_SHIFT (12)                   /* Page Entry */
 129
 130
 131 /* MMU context */
 132
 133 typedef struct _MMU_context {
 134         SEGREG  segs[16];       /* Segment registers */
 135         pte     **pmap;         /* Two-level page-map structure */
 136 } MMU_context;
 137
 138 extern void _tlbie(unsigned long va);   /* invalidate a TLB entry */
 139 extern void _tlbia(void);               /* invalidate all TLB entries */
 140
 141 typedef enum {
 142         IBAT0 = 0, IBAT1, IBAT2, IBAT3,
 143         DBAT0, DBAT1, DBAT2, DBAT3
 144 } ppc_bat_t;
 145
 146 extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
 147 extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 148
 149 #endif /* __ASSEMBLY__ */
 150
 151 /* Block size masks */
 152 #define BL_128K 0x000
 153 #define BL_256K 0x001
 154 #define BL_512K 0x003
 155 #define BL_1M   0x007
 156 #define BL_2M   0x00F
 157 #define BL_4M   0x01F
 158 #define BL_8M   0x03F
 159 #define BL_16M  0x07F
 160 #define BL_32M  0x0FF
 161 #define BL_64M  0x1FF
 162 #define BL_128M 0x3FF
 163 #define BL_256M 0x7FF
 164
 165 /* BAT Access Protection */
 166 #define BPP_XX  0x00            /* No access */
 167 #define BPP_RX  0x01            /* Read only */
 168 #define BPP_RW  0x02            /* Read/write */
 169
 170 /* Used to set up SDR1 register */
 171 #define HASH_TABLE_SIZE_64K     0x00010000
 172 #define HASH_TABLE_SIZE_128K    0x00020000
 173 #define HASH_TABLE_SIZE_256K    0x00040000
 174 #define HASH_TABLE_SIZE_512K    0x00080000
 175 #define HASH_TABLE_SIZE_1M      0x00100000
 176 #define HASH_TABLE_SIZE_2M      0x00200000
 177 #define HASH_TABLE_SIZE_4M      0x00400000
 178 #define HASH_TABLE_MASK_64K     0x000
 179 #define HASH_TABLE_MASK_128K    0x001
 180 #define HASH_TABLE_MASK_256K    0x003
 181 #define HASH_TABLE_MASK_512K    0x007
 182 #define HASH_TABLE_MASK_1M      0x00F
 183 #define HASH_TABLE_MASK_2M      0x01F
 184 #define HASH_TABLE_MASK_4M      0x03F
 185
 186 /* Control/status registers for the MPC8xx.
 187  * A write operation to these registers causes serialized access.
 188  * During software tablewalk, the registers used perform mask/shift-add
 189  * operations when written/read.  A TLB entry is created when the Mx_RPN
 190  * is written, and the contents of several registers are used to
 191  * create the entry.
 192  */
 193 #define MI_CTR          784     /* Instruction TLB control register */
 194 #define MI_GPM          0x80000000      /* Set domain manager mode */
 195 #define MI_PPM          0x40000000      /* Set subpage protection */
 196 #define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 197 #define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 198 #define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 199 #define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
 200 #define MI_RESETVAL     0x00000000      /* Value of register at reset */
 201
 202 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 203  * Ks = 0, Kp = 1.
 204  */
 205 #define MI_AP           786
 206 #define MI_Ks           0x80000000      /* Should not be set */
 207 #define MI_Kp           0x40000000      /* Should always be set */
 208
 209 /* The effective page number register.  When read, contains the information
 210  * about the last instruction TLB miss.  When MI_RPN is written, bits in
 211  * this register are used to create the TLB entry.
 212  */
 213 #define MI_EPN          787
 214 #define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
 215 #define MI_EVALID       0x00000200      /* Entry is valid */
 216 #define MI_ASIDMASK     0x0000000f      /* ASID match value */
 217                                         /* Reset value is undefined */
 218
 219 /* A "level 1" or "segment" or whatever you want to call it register.
 220  * For the instruction TLB, it contains bits that get loaded into the
 221  * TLB entry when the MI_RPN is written.
 222  */
 223 #define MI_TWC          789
 224 #define MI_APG          0x000001e0      /* Access protection group (0) */
 225 #define MI_GUARDED      0x00000010      /* Guarded storage */
 226 #define MI_PSMASK       0x0000000c      /* Mask of page size bits */
 227 #define MI_PS8MEG       0x0000000c      /* 8M page size */
 228 #define MI_PS512K       0x00000004      /* 512K page size */
 229 #define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
 230 #define MI_SVALID       0x00000001      /* Segment entry is valid */
 231                                         /* Reset value is undefined */
 232
 233 /* Real page number.  Defined by the pte.  Writing this register
 234  * causes a TLB entry to be created for the instruction TLB, using
 235  * additional information from the MI_EPN, and MI_TWC registers.
 236  */
 237 #define MI_RPN          790
 238
 239 /* Define an RPN value for mapping kernel memory to large virtual
 240  * pages for boot initialization.  This has real page number of 0,
 241  * large page size, shared page, cache enabled, and valid.
 242  * Also mark all subpages valid and write access.
 243  */
 244 #define MI_BOOTINIT     0x000001fd
 245
 246 #define MD_CTR          792     /* Data TLB control register */
 247 #define MD_GPM          0x80000000      /* Set domain manager mode */
 248 #define MD_PPM          0x40000000      /* Set subpage protection */
 249 #define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
 250 #define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
 251 #define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
 252 #define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
 253 #define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
 254 #define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
 255 #define MD_RESETVAL     0x04000000      /* Value of register at reset */
 256
 257 #define M_CASID         793     /* Address space ID (context) to match */
 258 #define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
 259
 260
 261 /* These are the Ks and Kp from the PowerPC books.  For proper operation,
 262  * Ks = 0, Kp = 1.
 263  */
 264 #define MD_AP           794
 265 #define MD_Ks           0x80000000      /* Should not be set */
 266 #define MD_Kp           0x40000000      /* Should always be set */
 267
 268 /* The effective page number register.  When read, contains the information
 269  * about the last instruction TLB miss.  When MD_RPN is written, bits in
 270  * this register are used to create the TLB entry.
 271  */
 272 #define MD_EPN          795
 273 #define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
 274 #define MD_EVALID       0x00000200      /* Entry is valid */
 275 #define MD_ASIDMASK     0x0000000f      /* ASID match value */
 276                                         /* Reset value is undefined */
 277
 278 /* The pointer to the base address of the first level page table.
 279  * During a software tablewalk, reading this register provides the address
 280  * of the entry associated with MD_EPN.
 281  */
 282 #define M_TWB           796
 283 #define M_L1TB          0xfffff000      /* Level 1 table base address */
 284 #define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
 285                                         /* Reset value is undefined */
 286
 287 /* A "level 1" or "segment" or whatever you want to call it register.
 288  * For the data TLB, it contains bits that get loaded into the TLB entry
 289  * when the MD_RPN is written.  It is also provides the hardware assist
 290  * for finding the PTE address during software tablewalk.
 291  */
 292 #define MD_TWC          797
 293 #define MD_L2TB         0xfffff000      /* Level 2 table base address */
 294 #define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
 295 #define MD_APG          0x000001e0      /* Access protection group (0) */
 296 #define MD_GUARDED      0x00000010      /* Guarded storage */
 297 #define MD_PSMASK       0x0000000c      /* Mask of page size bits */
 298 #define MD_PS8MEG       0x0000000c      /* 8M page size */
 299 #define MD_PS512K       0x00000004      /* 512K page size */
 300 #define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
 301 #define MD_WT           0x00000002      /* Use writethrough page attribute */
 302 #define MD_SVALID       0x00000001      /* Segment entry is valid */
 303                                         /* Reset value is undefined */
 304
 305
 306 /* Real page number.  Defined by the pte.  Writing this register
 307  * causes a TLB entry to be created for the data TLB, using
 308  * additional information from the MD_EPN, and MD_TWC registers.
 309  */
 310 #define MD_RPN          798
 311
 312 /* This is a temporary storage register that could be used to save
 313  * a processor working register during a tablewalk.
 314  */
 315 #define M_TW            799
 316
 317 /*
 318  * At present, all PowerPC 400-class processors share a similar TLB
 319  * architecture. The instruction and data sides share a unified,
 320  * 64-entry, fully-associative TLB which is maintained totally under
 321  * software control. In addition, the instruction side has a
 322  * hardware-managed, 4-entry, fully- associative TLB which serves as a
 323  * first level to the shared TLB. These two TLBs are known as the UTLB
 324  * and ITLB, respectively.
 325  */
 326
 327 #define        PPC4XX_TLB_SIZE 64
 328
 329 /*
 330  * TLB entries are defined by a "high" tag portion and a "low" data
 331  * portion.  On all architectures, the data portion is 32-bits.
 332  *
 333  * TLB entries are managed entirely under software control by reading,
 334  * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
 335  * instructions.
 336  */
 337
 338 /*
 339  * FSL Book-E support
 340  */
 341
 342 #define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
 343 #define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
 344 #define MAS0_NV(x)      ((x) & 0x00000FFF)
 345
 346 #define MAS1_VALID      0x80000000
 347 #define MAS1_IPROT      0x40000000
 348 #define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
 349 #define MAS1_TS         0x00001000
 350 #define MAS1_TSIZE(x)   ((x << 8) & 0x00000F00)
 351
 352 #define MAS2_EPN        0xFFFFF000
 353 #define MAS2_X0         0x00000040
 354 #define MAS2_X1         0x00000020
 355 #define MAS2_W          0x00000010
 356 #define MAS2_I          0x00000008
 357 #define MAS2_M          0x00000004
 358 #define MAS2_G          0x00000002
 359 #define MAS2_E          0x00000001
 360
 361 #define MAS3_RPN        0xFFFFF000
 362 #define MAS3_U0         0x00000200
 363 #define MAS3_U1         0x00000100
 364 #define MAS3_U2         0x00000080
 365 #define MAS3_U3         0x00000040
 366 #define MAS3_UX         0x00000020
 367 #define MAS3_SX         0x00000010
 368 #define MAS3_UW         0x00000008
 369 #define MAS3_SW         0x00000004
 370 #define MAS3_UR         0x00000002
 371 #define MAS3_SR         0x00000001
 372
 373 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
 374 #define MAS4_TIDDSEL    0x000F0000
 375 #define MAS4_TSIZED(x)  MAS1_TSIZE(x)
 376 #define MAS4_X0D        0x00000040
 377 #define MAS4_X1D        0x00000020
 378 #define MAS4_WD         0x00000010
 379 #define MAS4_ID         0x00000008
 380 #define MAS4_MD         0x00000004
 381 #define MAS4_GD         0x00000002
 382 #define MAS4_ED         0x00000001
 383
 384 #define MAS6_SPID0      0x3FFF0000
 385 #define MAS6_SPID1      0x00007FFE
 386 #define MAS6_SAS        0x00000001
 387 #define MAS6_SPID       MAS6_SPID0
 388
 389 #define MAS7_RPN        0xFFFFFFFF
 390
 391 #define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
 392                 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
 393 #define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
 394                 ((((v) << 31) & MAS1_VALID)             |\
 395                 (((iprot) << 30) & MAS1_IPROT)          |\
 396                 (MAS1_TID(tid))                         |\
 397                 (((ts) << 12) & MAS1_TS)                |\
 398                 (MAS1_TSIZE(tsize)))
 399 #define FSL_BOOKE_MAS2(epn, wimge) \
 400                 (((epn) & MAS3_RPN) | (wimge))
 401 #define FSL_BOOKE_MAS3(rpn, user, perms) \
 402                 (((rpn) & MAS3_RPN) | (user) | (perms))
 403
 404 #define BOOKE_PAGESZ_1K         0
 405 #define BOOKE_PAGESZ_4K         1
 406 #define BOOKE_PAGESZ_16K        2
 407 #define BOOKE_PAGESZ_64K        3
 408 #define BOOKE_PAGESZ_256K       4
 409 #define BOOKE_PAGESZ_1M         5
 410 #define BOOKE_PAGESZ_4M         6
 411 #define BOOKE_PAGESZ_16M        7
 412 #define BOOKE_PAGESZ_64M        8
 413 #define BOOKE_PAGESZ_256M       9
 414 #define BOOKE_PAGESZ_1G         10
 415 #define BOOKE_PAGESZ_4G         11
 416 #define BOOKE_PAGESZ_16GB       12
 417 #define BOOKE_PAGESZ_64GB       13
 418 #define BOOKE_PAGESZ_256GB      14
 419 #define BOOKE_PAGESZ_1TB        15
 420
 421 #ifdef CONFIG_E500
 422 #ifndef __ASSEMBLY__
 423 extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
 424                     u8 perms, u8 wimge,
 425                     u8 ts, u8 esel, u8 tsize, u8 iprot);
 426 extern void disable_tlb(u8 esel);
 427 extern void invalidate_tlb(u8 tlb);
 428 extern void init_tlbs(void);
 429
 430 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
 431         { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
 432           .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
 433
 434 struct fsl_e_tlb_entry {
 435         u8      tlb;
 436         u32     epn;
 437         u64     rpn;
 438         u8      perms;
 439         u8      wimge;
 440         u8      ts;
 441         u8      esel;
 442         u8      tsize;
 443         u8      iprot;
 444 };
 445
 446 extern struct fsl_e_tlb_entry tlb_table[];
 447 extern int num_tlb_entries;
 448 #endif
 449 #endif
 450
 451 #if defined(CONFIG_MPC86xx)
 452 #define LAWBAR_BASE_ADDR        0x00FFFFFF
 453 #define LAWAR_TRGT_IF           0x01F00000
 454 #else
 455 #define LAWBAR_BASE_ADDR        0x000FFFFF
 456 #define LAWAR_TRGT_IF           0x00F00000
 457 #endif
 458 #define LAWAR_EN                0x80000000
 459 #define LAWAR_SIZE              0x0000003F
 460
 461 #define LAWAR_TRGT_IF_PCI       0x00000000
 462 #define LAWAR_TRGT_IF_PCI1      0x00000000
 463 #define LAWAR_TRGT_IF_PCIX      0x00000000
 464 #define LAWAR_TRGT_IF_PCI2      0x00100000
 465 #define LAWAR_TRGT_IF_PCIE1     0x00200000
 466 #define LAWAR_TRGT_IF_PCIE2     0x00100000
 467 #define LAWAR_TRGT_IF_PCIE3     0x00300000
 468 #define LAWAR_TRGT_IF_LBC       0x00400000
 469 #define LAWAR_TRGT_IF_CCSR      0x00800000
 470 #define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
 471 #define LAWAR_TRGT_IF_RIO       0x00c00000
 472 #define LAWAR_TRGT_IF_DDR       0x00f00000
 473 #define LAWAR_TRGT_IF_DDR1      0x00f00000
 474 #define LAWAR_TRGT_IF_DDR2      0x01600000
 475
 476 #define LAWAR_SIZE_BASE         0xa
 477 #define LAWAR_SIZE_4K           (LAWAR_SIZE_BASE+1)
 478 #define LAWAR_SIZE_8K           (LAWAR_SIZE_BASE+2)
 479 #define LAWAR_SIZE_16K          (LAWAR_SIZE_BASE+3)
 480 #define LAWAR_SIZE_32K          (LAWAR_SIZE_BASE+4)
 481 #define LAWAR_SIZE_64K          (LAWAR_SIZE_BASE+5)
 482 #define LAWAR_SIZE_128K         (LAWAR_SIZE_BASE+6)
 483 #define LAWAR_SIZE_256K         (LAWAR_SIZE_BASE+7)
 484 #define LAWAR_SIZE_512K         (LAWAR_SIZE_BASE+8)
 485 #define LAWAR_SIZE_1M           (LAWAR_SIZE_BASE+9)
 486 #define LAWAR_SIZE_2M           (LAWAR_SIZE_BASE+10)
 487 #define LAWAR_SIZE_4M           (LAWAR_SIZE_BASE+11)
 488 #define LAWAR_SIZE_8M           (LAWAR_SIZE_BASE+12)
 489 #define LAWAR_SIZE_16M          (LAWAR_SIZE_BASE+13)
 490 #define LAWAR_SIZE_32M          (LAWAR_SIZE_BASE+14)
 491 #define LAWAR_SIZE_64M          (LAWAR_SIZE_BASE+15)
 492 #define LAWAR_SIZE_128M         (LAWAR_SIZE_BASE+16)
 493 #define LAWAR_SIZE_256M         (LAWAR_SIZE_BASE+17)
 494 #define LAWAR_SIZE_512M         (LAWAR_SIZE_BASE+18)
 495 #define LAWAR_SIZE_1G           (LAWAR_SIZE_BASE+19)
 496 #define LAWAR_SIZE_2G           (LAWAR_SIZE_BASE+20)
 497 #define LAWAR_SIZE_4G           (LAWAR_SIZE_BASE+21)
 498 #define LAWAR_SIZE_8G           (LAWAR_SIZE_BASE+22)
 499 #define LAWAR_SIZE_16G          (LAWAR_SIZE_BASE+23)
 500 #define LAWAR_SIZE_32G          (LAWAR_SIZE_BASE+24)
 501
 502 #ifdef CONFIG_440
 503 /* General */
 504 #define TLB_VALID   0x00000200
 505
 506 /* Supported page sizes */
 507
 508 #define SZ_1K   0x00000000
 509 #define SZ_4K   0x00000010
 510 #define SZ_16K  0x00000020
 511 #define SZ_64K  0x00000030
 512 #define SZ_256K 0x00000040
 513 #define SZ_1M   0x00000050
 514 #define SZ_16M  0x00000070
 515 #define SZ_256M 0x00000090
 516
 517 /* Storage attributes */
 518 #define SA_W    0x00000800      /* Write-through */
 519 #define SA_I    0x00000400      /* Caching inhibited */
 520 #define SA_M    0x00000200      /* Memory coherence */
 521 #define SA_G    0x00000100      /* Guarded */
 522 #define SA_E    0x00000080      /* Endian */
 523
 524 /* Access control */
 525 #define AC_X    0x00000024      /* Execute */
 526 #define AC_W    0x00000012      /* Write */
 527 #define AC_R    0x00000009      /* Read */
 528
 529 /* Some handy macros */
 530
 531 #define EPN(e)          ((e) & 0xfffffc00)
 532 #define TLB0(epn,sz)    ((EPN((epn)) | (sz) | TLB_VALID ))
 533 #define TLB1(rpn,erpn)  (((rpn) & 0xfffffc00) | (erpn))
 534 #define TLB2(a)         ((a) & 0x00000fbf)
 535
 536 #define tlbtab_start\
 537         mflr    r1      ;\
 538         bl      0f      ;
 539
 540 #define tlbtab_end\
 541         .long 0, 0, 0   ;\
 542 0:      mflr    r0      ;\
 543         mtlr    r1      ;\
 544         blr             ;
 545
 546 #define tlbentry(epn,sz,rpn,erpn,attr)\
 547         .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
 548
 549 /*----------------------------------------------------------------------------+
 550 | TLB specific defines.
 551 +----------------------------------------------------------------------------*/
 552 #define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
 553 #define TLB_16MB_ALIGN_MASK  0xFFF000000ULL
 554 #define TLB_1MB_ALIGN_MASK   0xFFFF00000ULL
 555 #define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
 556 #define TLB_64KB_ALIGN_MASK  0xFFFFF0000ULL
 557 #define TLB_16KB_ALIGN_MASK  0xFFFFFC000ULL
 558 #define TLB_4KB_ALIGN_MASK   0xFFFFFF000ULL
 559 #define TLB_1KB_ALIGN_MASK   0xFFFFFFC00ULL
 560 #define TLB_256MB_SIZE       0x10000000
 561 #define TLB_16MB_SIZE        0x01000000
 562 #define TLB_1MB_SIZE         0x00100000
 563 #define TLB_256KB_SIZE       0x00040000
 564 #define TLB_64KB_SIZE        0x00010000
 565 #define TLB_16KB_SIZE        0x00004000
 566 #define TLB_4KB_SIZE         0x00001000
 567 #define TLB_1KB_SIZE         0x00000400
 568
 569 #define TLB_WORD0_EPN_MASK   0xFFFFFC00
 570 #define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
 571 #define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
 572 #define TLB_WORD0_V_MASK     0x00000200
 573 #define TLB_WORD0_V_ENABLE   0x00000200
 574 #define TLB_WORD0_V_DISABLE  0x00000000
 575 #define TLB_WORD0_TS_MASK    0x00000100
 576 #define TLB_WORD0_TS_1       0x00000100
 577 #define TLB_WORD0_TS_0       0x00000000
 578 #define TLB_WORD0_SIZE_MASK  0x000000F0
 579 #define TLB_WORD0_SIZE_1KB   0x00000000
 580 #define TLB_WORD0_SIZE_4KB   0x00000010
 581 #define TLB_WORD0_SIZE_16KB  0x00000020
 582 #define TLB_WORD0_SIZE_64KB  0x00000030
 583 #define TLB_WORD0_SIZE_256KB 0x00000040
 584 #define TLB_WORD0_SIZE_1MB   0x00000050
 585 #define TLB_WORD0_SIZE_16MB  0x00000070
 586 #define TLB_WORD0_SIZE_256MB 0x00000090
 587 #define TLB_WORD0_TPAR_MASK  0x0000000F
 588 #define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
 589 #define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
 590
 591 #define TLB_WORD1_RPN_MASK   0xFFFFFC00
 592 #define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
 593 #define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
 594 #define TLB_WORD1_PAR1_MASK  0x00000300
 595 #define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
 596 #define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
 597 #define TLB_WORD1_PAR1_0     0x00000000
 598 #define TLB_WORD1_PAR1_1     0x00000100
 599 #define TLB_WORD1_PAR1_2     0x00000200
 600 #define TLB_WORD1_PAR1_3     0x00000300
 601 #define TLB_WORD1_ERPN_MASK  0x0000000F
 602 #define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
 603 #define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
 604
 605 #define TLB_WORD2_PAR2_MASK  0xC0000000
 606 #define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
 607 #define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
 608 #define TLB_WORD2_PAR2_0     0x00000000
 609 #define TLB_WORD2_PAR2_1     0x40000000
 610 #define TLB_WORD2_PAR2_2     0x80000000
 611 #define TLB_WORD2_PAR2_3     0xC0000000
 612 #define TLB_WORD2_U0_MASK    0x00008000
 613 #define TLB_WORD2_U0_ENABLE  0x00008000
 614 #define TLB_WORD2_U0_DISABLE 0x00000000
 615 #define TLB_WORD2_U1_MASK    0x00004000
 616 #define TLB_WORD2_U1_ENABLE  0x00004000
 617 #define TLB_WORD2_U1_DISABLE 0x00000000
 618 #define TLB_WORD2_U2_MASK    0x00002000
 619 #define TLB_WORD2_U2_ENABLE  0x00002000
 620 #define TLB_WORD2_U2_DISABLE 0x00000000
 621 #define TLB_WORD2_U3_MASK    0x00001000
 622 #define TLB_WORD2_U3_ENABLE  0x00001000
 623 #define TLB_WORD2_U3_DISABLE 0x00000000
 624 #define TLB_WORD2_W_MASK     0x00000800
 625 #define TLB_WORD2_W_ENABLE   0x00000800
 626 #define TLB_WORD2_W_DISABLE  0x00000000
 627 #define TLB_WORD2_I_MASK     0x00000400
 628 #define TLB_WORD2_I_ENABLE   0x00000400
 629 #define TLB_WORD2_I_DISABLE  0x00000000
 630 #define TLB_WORD2_M_MASK     0x00000200
 631 #define TLB_WORD2_M_ENABLE   0x00000200
 632 #define TLB_WORD2_M_DISABLE  0x00000000
 633 #define TLB_WORD2_G_MASK     0x00000100
 634 #define TLB_WORD2_G_ENABLE   0x00000100
 635 #define TLB_WORD2_G_DISABLE  0x00000000
 636 #define TLB_WORD2_E_MASK     0x00000080
 637 #define TLB_WORD2_E_ENABLE   0x00000080
 638 #define TLB_WORD2_E_DISABLE  0x00000000
 639 #define TLB_WORD2_UX_MASK    0x00000020
 640 #define TLB_WORD2_UX_ENABLE  0x00000020
 641 #define TLB_WORD2_UX_DISABLE 0x00000000
 642 #define TLB_WORD2_UW_MASK    0x00000010
 643 #define TLB_WORD2_UW_ENABLE  0x00000010
 644 #define TLB_WORD2_UW_DISABLE 0x00000000
 645 #define TLB_WORD2_UR_MASK    0x00000008
 646 #define TLB_WORD2_UR_ENABLE  0x00000008
 647 #define TLB_WORD2_UR_DISABLE 0x00000000
 648 #define TLB_WORD2_SX_MASK    0x00000004
 649 #define TLB_WORD2_SX_ENABLE  0x00000004
 650 #define TLB_WORD2_SX_DISABLE 0x00000000
 651 #define TLB_WORD2_SW_MASK    0x00000002
 652 #define TLB_WORD2_SW_ENABLE  0x00000002
 653 #define TLB_WORD2_SW_DISABLE 0x00000000
 654 #define TLB_WORD2_SR_MASK    0x00000001
 655 #define TLB_WORD2_SR_ENABLE  0x00000001
 656 #define TLB_WORD2_SR_DISABLE 0x00000000
 657
 658 /*----------------------------------------------------------------------------+
 659 | Following instructions are not available in Book E mode of the GNU assembler.
 660 +----------------------------------------------------------------------------*/
 661 #define DCCCI(ra,rb)                    .long 0x7c000000|\
 662                                         (ra<<16)|(rb<<11)|(454<<1)
 663
 664 #define ICCCI(ra,rb)                    .long 0x7c000000|\
 665                                         (ra<<16)|(rb<<11)|(966<<1)
 666
 667 #define DCREAD(rt,ra,rb)                .long 0x7c000000|\
 668                                         (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
 669
 670 #define ICREAD(ra,rb)                   .long 0x7c000000|\
 671                                         (ra<<16)|(rb<<11)|(998<<1)
 672
 673 #define TLBSX(rt,ra,rb)                 .long 0x7c000000|\
 674                                         (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
 675
 676 #define TLBWE(rs,ra,ws)                 .long 0x7c000000|\
 677                                         (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
 678
 679 #define TLBRE(rt,ra,ws)                 .long 0x7c000000|\
 680                                         (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
 681
 682 #define TLBSXDOT(rt,ra,rb)              .long 0x7c000001|\
 683                                         (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
 684
 685 #define MSYNC                           .long 0x7c000000|\
 686                                         (598<<1)
 687
 688 #define MBAR_INST                               .long 0x7c000000|\
 689                                         (854<<1)
 690
 691 #ifndef __ASSEMBLY__
 692 /* Prototypes */
 693 void mttlb1(unsigned long index, unsigned long value);
 694 void mttlb2(unsigned long index, unsigned long value);
 695 void mttlb3(unsigned long index, unsigned long value);
 696 unsigned long mftlb1(unsigned long index);
 697 unsigned long mftlb2(unsigned long index);
 698 unsigned long mftlb3(unsigned long index);
 699
 700 void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 701 void remove_tlb(u32 vaddr, u32 size);
 702 void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
 703 #endif /* __ASSEMBLY__ */
 704
 705 #endif /* CONFIG_440 */
 706 #endif /* _PPC_MMU_H_ */