include/asm-ppc/io.h

   1 /* originally from linux source.
   2  * removed the dependencies on CONFIG_ values
   3  * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
   4  * Modified By Rob Taylor, Flying Pig Systems, 2000
   5  */
   6
   7 #ifndef _PPC_IO_H
   8 #define _PPC_IO_H
   9
  10 #include <linux/config.h>
  11 #include <asm/byteorder.h>
  12
  13 #define SIO_CONFIG_RA   0x398
  14 #define SIO_CONFIG_RD   0x399
  15
  16 #ifndef _IO_BASE
  17 #define _IO_BASE 0
  18 #endif
  19
  20 #define readb(addr) in_8((volatile u8 *)(addr))
  21 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
  22 #if !defined(__BIG_ENDIAN)
  23 #define readw(addr) (*(volatile u16 *) (addr))
  24 #define readl(addr) (*(volatile u32 *) (addr))
  25 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
  26 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
  27 #else
  28 #define readw(addr) in_le16((volatile u16 *)(addr))
  29 #define readl(addr) in_le32((volatile u32 *)(addr))
  30 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
  31 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
  32 #endif
  33
  34 /*
  35  * The insw/outsw/insl/outsl macros don't do byte-swapping.
  36  * They are only used in practice for transferring buffers which
  37  * are arrays of bytes, and byte-swapping is not appropriate in
  38  * that case.  - paulus
  39  */
  40 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
  41 #define outsb(port, buf, ns)    _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
  42 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
  43 #define outsw(port, buf, ns)    _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
  44 #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
  45 #define outsl(port, buf, nl)    _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
  46
  47 #define inb(port)       in_8((u8 *)((port)+_IO_BASE))
  48 #define outb(val, port)     out_8((u8 *)((port)+_IO_BASE), (val))
  49 #if !defined(__BIG_ENDIAN)
  50 #define inw(port)       in_be16((u16 *)((port)+_IO_BASE))
  51 #define outw(val, port)     out_be16((u16 *)((port)+_IO_BASE), (val))
  52 #define inl(port)       in_be32((u32 *)((port)+_IO_BASE))
  53 #define outl(val, port)     out_be32((u32 *)((port)+_IO_BASE), (val))
  54 #else
  55 #define inw(port)       in_le16((u16 *)((port)+_IO_BASE))
  56 #define outw(val, port)     out_le16((u16 *)((port)+_IO_BASE), (val))
  57 #define inl(port)       in_le32((u32 *)((port)+_IO_BASE))
  58 #define outl(val, port)     out_le32((u32 *)((port)+_IO_BASE), (val))
  59 #endif
  60
  61 #define inb_p(port)     in_8((u8 *)((port)+_IO_BASE))
  62 #define outb_p(val, port)   out_8((u8 *)((port)+_IO_BASE), (val))
  63 #define inw_p(port)     in_le16((u16 *)((port)+_IO_BASE))
  64 #define outw_p(val, port)   out_le16((u16 *)((port)+_IO_BASE), (val))
  65 #define inl_p(port)     in_le32((u32 *)((port)+_IO_BASE))
  66 #define outl_p(val, port)   out_le32((u32 *)((port)+_IO_BASE), (val))
  67
  68 extern void _insb(volatile u8 *port, void *buf, int ns);
  69 extern void _outsb(volatile u8 *port, const void *buf, int ns);
  70 extern void _insw(volatile u16 *port, void *buf, int ns);
  71 extern void _outsw(volatile u16 *port, const void *buf, int ns);
  72 extern void _insl(volatile u32 *port, void *buf, int nl);
  73 extern void _outsl(volatile u32 *port, const void *buf, int nl);
  74 extern void _insw_ns(volatile u16 *port, void *buf, int ns);
  75 extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
  76 extern void _insl_ns(volatile u32 *port, void *buf, int nl);
  77 extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
  78
  79 /*
  80  * The *_ns versions below don't do byte-swapping.
  81  * Neither do the standard versions now, these are just here
  82  * for older code.
  83  */
  84 #define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
  85 #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
  86 #define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
  87 #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
  88
  89
  90 #define IO_SPACE_LIMIT ~0
  91
  92 #define memset_io(a,b,c)       memset((void *)(a),(b),(c))
  93 #define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
  94 #define memcpy_toio(a,b,c)  memcpy((void *)(a),(b),(c))
  95
  96 /*
  97  * Enforce In-order Execution of I/O:
  98  * Acts as a barrier to ensure all previous I/O accesses have
  99  * completed before any further ones are issued.
 100  */
 101 static inline void eieio(void)
 102 {
 103         __asm__ __volatile__ ("eieio" : : : "memory");
 104 }
 105
 106 static inline void sync(void)
 107 {
 108         __asm__ __volatile__ ("sync" : : : "memory");
 109 }
 110
 111 static inline void isync(void)
 112 {
 113         __asm__ __volatile__ ("isync" : : : "memory");
 114 }
 115
 116 /* Enforce in-order execution of data I/O.
 117  * No distinction between read/write on PPC; use eieio for all three.
 118  */
 119 #define iobarrier_rw() eieio()
 120 #define iobarrier_r()  eieio()
 121 #define iobarrier_w()  eieio()
 122
 123 /*
 124  * Non ordered and non-swapping "raw" accessors
 125  */
 126 #define __iomem
 127 #define PCI_FIX_ADDR(addr)      (addr)
 128
 129 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 130 {
 131         return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
 132 }
 133 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 134 {
 135         return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
 136 }
 137 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 138 {
 139         return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
 140 }
 141 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 142 {
 143         *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
 144 }
 145 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 146 {
 147         *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
 148 }
 149 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 150 {
 151         *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
 152 }
 153
 154 /*
 155  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
 156  *
 157  * Read operations have additional twi & isync to make sure the read
 158  * is actually performed (i.e. the data has come back) before we start
 159  * executing any following instructions.
 160  */
 161 extern inline int in_8(const volatile unsigned char __iomem *addr)
 162 {
 163         int ret;
 164
 165         __asm__ __volatile__(
 166                 "sync; lbz%U1%X1 %0,%1;\n"
 167                 "twi 0,%0,0;\n"
 168                 "isync" : "=r" (ret) : "m" (*addr));
 169         return ret;
 170 }
 171
 172 extern inline void out_8(volatile unsigned char __iomem *addr, int val)
 173 {
 174         __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 175 }
 176
 177 extern inline int in_le16(const volatile unsigned short __iomem *addr)
 178 {
 179         int ret;
 180
 181         __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
 182                              "twi 0,%0,0;\n"
 183                              "isync" : "=r" (ret) :
 184                               "r" (addr), "m" (*addr));
 185         return ret;
 186 }
 187
 188 extern inline int in_be16(const volatile unsigned short __iomem *addr)
 189 {
 190         int ret;
 191
 192         __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
 193                              "twi 0,%0,0;\n"
 194                              "isync" : "=r" (ret) : "m" (*addr));
 195         return ret;
 196 }
 197
 198 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
 199 {
 200         __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
 201                               "r" (val), "r" (addr));
 202 }
 203
 204 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
 205 {
 206         __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 207 }
 208
 209 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
 210 {
 211         unsigned ret;
 212
 213         __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
 214                              "twi 0,%0,0;\n"
 215                              "isync" : "=r" (ret) :
 216                              "r" (addr), "m" (*addr));
 217         return ret;
 218 }
 219
 220 extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
 221 {
 222         unsigned ret;
 223
 224         __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
 225                              "twi 0,%0,0;\n"
 226                              "isync" : "=r" (ret) : "m" (*addr));
 227         return ret;
 228 }
 229
 230 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
 231 {
 232         __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
 233                              "r" (val), "r" (addr));
 234 }
 235
 236 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 237 {
 238         __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 239 }
 240
 241 /*
 242  * Given a physical address and a length, return a virtual address
 243  * that can be used to access the memory range with the caching
 244  * properties specified by "flags".
 245  */
 246 typedef unsigned long phys_addr_t;
 247
 248 #define MAP_NOCACHE     (0)
 249 #define MAP_WRCOMBINE   (0)
 250 #define MAP_WRBACK      (0)
 251 #define MAP_WRTHROUGH   (0)
 252
 253 static inline void *
 254 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
 255 {
 256         return (void *)paddr;
 257 }
 258
 259 /*
 260  * Take down a mapping set up by map_physmem().
 261  */
 262 static inline void unmap_physmem(void *vaddr, unsigned long flags)
 263 {
 264
 265 }
 266
 267 #endif