board/spc1920/spc1920.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <config.h>
  27 #include <common.h>
  28 #include <mpc8xx.h>
  29 #include "pld.h"
  30 #include "hpi.h"
  31
  32 #define _NOT_USED_      0xFFFFFFFF
  33
  34 static long int dram_size (long int, long int *, long int);
  35
  36 const uint sdram_table[] = {
  37         /*
  38          * Single Read. (Offset 0 in UPMB RAM)
  39          */
  40         0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  41         0x1FF77C47, /* last */
  42         /*
  43          * SDRAM Initialization (offset 5 in UPMB RAM)
  44          *
  45          * This is no UPM entry point. The following definition uses
  46          * the remaining space to establish an initialization
  47          * sequence, which is executed by a RUN command.
  48          *
  49          */
  50         0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
  51         /*
  52          * Burst Read. (Offset 8 in UPMB RAM)
  53          */
  54         0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  55         0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
  56         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  58         /*
  59          * Single Write. (Offset 18 in UPMB RAM)
  60          */
  61         0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
  62         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  63         /*
  64          * Burst Write. (Offset 20 in UPMB RAM)
  65          */
  66         0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  67         0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
  68         _NOT_USED_,
  69         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  70         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  71         /*
  72          * Refresh  (Offset 30 in UPMB RAM)
  73          */
  74         0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  75         0xFFFFFC84, 0xFFFFFC07, /* last */
  76         _NOT_USED_, _NOT_USED_,
  77         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  78         /*
  79          * Exception. (Offset 3c in UPMB RAM)
  80          */
  81         0x7FFFFC07, /* last */
  82         _NOT_USED_, _NOT_USED_, _NOT_USED_,
  83 };
  84
  85 long int initdram (int board_type)
  86 {
  87         volatile immap_t *immr = (immap_t *) CFG_IMMR;
  88         volatile memctl8xx_t *memctl = &immr->im_memctl;
  89         /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */
  90
  91         long int size_b0;
  92         long int size8, size9;
  93         int i;
  94
  95         /*
  96          * Configure UPMB for SDRAM
  97          */
  98         upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
  99
 100         udelay(100);
 101
 102         memctl->memc_mptpr = CFG_MPTPR;
 103
 104         /* burst length=4, burst type=sequential, CAS latency=2 */
 105         memctl->memc_mar = CFG_MAR;
 106
 107         /*
 108          * Map controller bank 1 to the SDRAM bank at preliminary address.
 109          */
 110         memctl->memc_or1 = CFG_OR1_PRELIM;
 111         memctl->memc_br1 = CFG_BR1_PRELIM;
 112
 113         /* initialize memory address register */
 114         memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
 115
 116         /* mode initialization (offset 5) */
 117         udelay (200);                           /* 0x80006105 */
 118         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);
 119
 120         /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
 121         udelay (1);                             /* 0x80006130 */
 122         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
 123         udelay (1);                             /* 0x80006130 */
 124         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
 125         udelay (1);                             /* 0x80006106 */
 126         memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);
 127
 128         memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
 129
 130         udelay (200);
 131
 132         /* Need at least 10 DRAM accesses to stabilize */
 133         for (i = 0; i < 10; ++i) {
 134                 volatile unsigned long *addr =
 135                         (volatile unsigned long *) CFG_SDRAM_BASE;
 136                 unsigned long val;
 137
 138                 val = *(addr + i);
 139                 *(addr + i) = val;
 140         }
 141
 142         /*
 143          * Check Bank 0 Memory Size for re-configuration
 144          *
 145          * try 8 column mode
 146          */
 147         size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
 148
 149         udelay (1000);
 150
 151         /*
 152          * try 9 column mode
 153          */
 154         size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
 155
 156         if (size8 < size9) {            /* leave configuration at 9 columns */
 157                 size_b0 = size9;
 158                 memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE;
 159                 udelay (500);
 160         } else {                        /* back to 8 columns            */
 161                 size_b0 = size8;
 162                 memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
 163                 udelay (500);
 164         }
 165
 166         /*
 167          * Final mapping:
 168          */
 169
 170         memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
 171                         OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
 172         memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
 173         udelay (1000);
 174
 175         /* initalize the DSP Host Port Interface */
 176         hpi_init();
 177
 178         /* FRAM Setup */
 179         memctl->memc_or4 = CFG_OR4;
 180         memctl->memc_br4 = CFG_BR4;
 181         udelay(1000);
 182
 183         return (size_b0);
 184 }
 185
 186 /*
 187  * Check memory range for valid RAM. A simple memory test determines
 188  * the actually available RAM size between addresses `base' and
 189  * `base + maxsize'. Some (not all) hardware errors are detected:
 190  * - short between address lines
 191  * - short between data lines
 192  */
 193 static long int dram_size (long int mbmr_value, long int *base,
 194                            long int maxsize)
 195 {
 196         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 197         volatile memctl8xx_t *memctl = &immap->im_memctl;
 198
 199         memctl->memc_mbmr = mbmr_value;
 200
 201         return (get_ram_size (base, maxsize));
 202 }
 203
 204
 205 /************* other stuff ******************/
 206
 207
 208 int board_early_init_f(void)
 209 {
 210         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 211
 212         /* Set Go/NoGo led (PA15) to color red */
 213         immap->im_ioport.iop_papar &= ~0x1;
 214         immap->im_ioport.iop_paodr &= ~0x1;
 215         immap->im_ioport.iop_padir |= 0x1;
 216         immap->im_ioport.iop_padat |= 0x1;
 217
 218 #if 0
 219         /* Turn on LED PD9 */
 220         immap->im_ioport.iop_pdpar &= ~(0x0040);
 221         immap->im_ioport.iop_pddir |= 0x0040;
 222         immap->im_ioport.iop_pddat |= 0x0040;
 223 #endif
 224
 225         /*
 226          * Enable console on SMC1. This requires turning on
 227          * the com2_en signal and SMC1_DISABLE
 228          */
 229
 230         /* SMC1_DISABLE: PB17 */
 231         immap->im_cpm.cp_pbodr &= ~0x4000;
 232         immap->im_cpm.cp_pbpar &= ~0x4000;
 233         immap->im_cpm.cp_pbdir |= 0x4000;
 234         immap->im_cpm.cp_pbdat &= ~0x4000;
 235
 236         /* COM2_EN: PD10 */
 237         immap->im_ioport.iop_pdpar &= ~0x0020;
 238         immap->im_ioport.iop_pddir &= ~0x4000;
 239         immap->im_ioport.iop_pddir |= 0x0020;
 240         immap->im_ioport.iop_pddat |= 0x0020;
 241
 242
 243 #ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
 244         immap->im_cpm.cp_simode |= 0x7000;
 245         immap->im_cpm.cp_simode &= ~(0x8000);
 246 #endif
 247
 248         return 0;
 249 }
 250
 251 int last_stage_init(void)
 252 {
 253 #ifdef CONFIG_SPC1920_HPI_TEST
 254         printf("CMB1920 Host Port Interface Test: %s\n",
 255                hpi_test() ? "Failed!" : "OK");
 256 #endif
 257         return 0;
 258 }
 259
 260 int checkboard (void)
 261 {
 262         puts("Board: SPC1920\n");
 263         return 0;
 264 }