board/smdk2443/smdk2443.c

   1 /*
   2  * (C) Copyright 2006 OpenMoko, Inc.
   3  * Author: Harald Welte <laforge@openmoko.org>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <s3c2440.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define FCLK_SPEED 1
  30
  31 #if FCLK_SPEED==0               /* Fout = 203MHz, Fin = 12MHz for Audio */
  32 #define M_MDIV  0xC3
  33 #define M_PDIV  0x4
  34 #define M_SDIV  0x1
  35 #elif FCLK_SPEED==1             /* Fout = 399.65MHz */
  36 #define M_MDIV  0x6e
  37 #define M_PDIV  0x3
  38 #define M_SDIV  0x1
  39 #endif
  40
  41 #define USB_CLOCK 1
  42
  43 #if USB_CLOCK==0
  44 #define U_M_MDIV        0xA1
  45 #define U_M_PDIV        0x3
  46 #define U_M_SDIV        0x1
  47 #elif USB_CLOCK==1
  48 #define U_M_MDIV        0x3c
  49 #define U_M_PDIV        0x4
  50 #define U_M_SDIV        0x2
  51 #endif
  52
  53 static inline void delay (unsigned long loops)
  54 {
  55         __asm__ volatile ("1:\n"
  56           "subs %0, %1, #1\n"
  57           "bne 1b":"=r" (loops):"0" (loops));
  58 }
  59
  60 /*
  61  * Miscellaneous platform dependent initialisations
  62  */
  63
  64 int board_init (void)
  65 {
  66         S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  67         S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  68
  69         /* to reduce PLL lock time, adjust the LOCKTIME register */
  70         clk_power->LOCKTIME = 0xFFFFFF;
  71
  72         /* configure MPLL */
  73         clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
  74
  75         /* some delay between MPLL and UPLL */
  76         delay (4000);
  77
  78         /* configure UPLL */
  79         clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
  80
  81         /* some delay between MPLL and UPLL */
  82         delay (8000);
  83
  84         /* set up the I/O ports */
  85         gpio->GPACON = 0x007FFFFF;
  86         gpio->GPBCON = 0x00044555;
  87         gpio->GPBUP = 0x000007FF;
  88         gpio->GPCCON = 0xAAAAAAAA;
  89         gpio->GPCUP = 0x0000FFFF;
  90         gpio->GPDCON = 0xAAAAAAAA;
  91         gpio->GPDUP = 0x0000FFFF;
  92         gpio->GPECON = 0xAAAAAAAA;
  93         gpio->GPEUP = 0x0000FFFF;
  94         gpio->GPFCON = 0x000055AA;
  95         gpio->GPFUP = 0x000000FF;
  96         gpio->GPGCON = 0xFD95FFBA;
  97         gpio->GPGUP = 0x0000FFFF;
  98 #ifdef CONFIG_SERIAL3
  99         gpio->GPHCON = 0x002AAAAA;
 100 #else
 101         gpio->GPHCON = 0x002AFAAA;
 102 #endif
 103         gpio->GPHUP = 0x000007FF;
 104
 105 #if 0
 106         /* USB Device Part */
 107         /*GPGCON is reset for USB Device */
 108         gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */
 109         gpio->GPGUP = gpio->GPGUP | ( 1 << 12);                 /* Pull up disable */
 110
 111         gpio->GPGDAT |= ( 1 << 12) ;
 112         gpio->GPGDAT &= ~( 1 << 12) ;
 113         udelay(20000);
 114         gpio->GPGDAT |= ( 1 << 12) ;
 115 #endif
 116
 117         /* arch number of SMDK2440-Board */
 118         gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
 119
 120         /* adress of boot parameters */
 121         gd->bd->bi_boot_params = 0x30000100;
 122
 123         icache_enable();
 124         dcache_enable();
 125
 126         return 0;
 127 }
 128
 129 int dram_init (void)
 130 {
 131         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 132         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 133
 134         return 0;
 135 }
 136
 137 /* The sum of all part_size[]s must equal to the NAND size, i.e., 0x4000000.
 138    "initrd" is sized such that it can hold two uncompressed 16 bit 640*480
 139    images: 640*480*2*2 = 1228800 < 1245184. */
 140
 141 unsigned int dynpart_size[] = {
 142     CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x3d5c000-CFG_UBOOT_SIZE, 0 };
 143
 144 char *dynpart_names[] = {
 145     "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };
 146
 147