2 * SMDK2443 Memory Setup
4 * Copyright (C) 2007 by OpenMoko, Inc.
5 * Author: Harald Welte <laforge@openmoko.org>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* some parameters for the board */
35 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
37 * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
41 #define BWSCON 0x48000000
50 #define B1_BWSCON (DW32)
51 #define B2_BWSCON (DW16)
52 #define B3_BWSCON (DW16 + WAIT + UBLB)
53 #define B4_BWSCON (DW16)
54 #define B5_BWSCON (DW16)
55 #define B6_BWSCON (DW32)
56 #define B7_BWSCON (DW32)
59 #define B0_Tacs 0x0 /* 0clk */
60 #define B0_Tcos 0x0 /* 0clk */
61 #define B0_Tacc 0x7 /* 14clk */
62 #define B0_Tcoh 0x0 /* 0clk */
63 #define B0_Tah 0x0 /* 0clk */
65 #define B0_PMC 0x0 /* normal */
68 #define B1_Tacs 0x0 /* 0clk */
69 #define B1_Tcos 0x0 /* 0clk */
70 #define B1_Tacc 0x7 /* 14clk */
71 #define B1_Tcoh 0x0 /* 0clk */
72 #define B1_Tah 0x0 /* 0clk */
84 #define B3_Tacs 0x0 /* 0clk */
85 #define B3_Tcos 0x3 /* 4clk */
86 #define B3_Tacc 0x7 /* 14clk */
87 #define B3_Tcoh 0x1 /* 1clk */
88 #define B3_Tah 0x0 /* 0clk */
89 #define B3_Tacp 0x3 /* 6clk */
90 #define B3_PMC 0x0 /* normal */
92 #define B4_Tacs 0x0 /* 0clk */
93 #define B4_Tcos 0x0 /* 0clk */
94 #define B4_Tacc 0x7 /* 14clk */
95 #define B4_Tcoh 0x0 /* 0clk */
96 #define B4_Tah 0x0 /* 0clk */
98 #define B4_PMC 0x0 /* normal */
100 #define B5_Tacs 0x0 /* 0clk */
101 #define B5_Tcos 0x0 /* 0clk */
102 #define B5_Tacc 0x7 /* 14clk */
103 #define B5_Tcoh 0x0 /* 0clk */
104 #define B5_Tah 0x0 /* 0clk */
106 #define B5_PMC 0x0 /* normal */
108 #define B6_MT 0x3 /* SDRAM */
110 #define B6_SCAN 0x1 /* 9bit */
112 #define B7_MT 0x3 /* SDRAM */
113 #define B7_Trcd 0x1 /* 3clk */
114 #define B7_SCAN 0x1 /* 9bit */
116 /* REFRESH parameter */
117 #define REFEN 0x1 /* Refresh enable */
118 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
119 #define Trp 0x0 /* 2clk */
120 #define Trc 0x3 /* 7clk */
121 #define Tchr 0x2 /* 3clk */
122 #define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
123 /**************************************/
130 /* memory control configuration */
131 /* make r0 relative the current location so that it */
132 /* reads SMRDATA out of FLASH rather than memory ! */
136 ldr r1, =BWSCON /* Bus Width Status Controller */
144 /* everything is fine now */
148 /* the literal pools origin */
151 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
152 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
153 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
154 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
155 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
156 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
157 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
158 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
159 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
160 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)