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Modified patch originates from Andy Green <andy@openmoko.com>
[u-boot-openmoko/mini2440.git] / board / sandburst / metrobox / metrobox.c
blob86d259fac4a1e2d277472ffc1617c493ae2227ee
1 /*
2 * Copyright (c) 2005
3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23 #include <config.h>
24 #include <common.h>
25 #include <command.h>
26 #include "metrobox.h"
27 #include "metrobox_version.h"
28 #include <asm/processor.h>
29 #include <asm/io.h>
30 #include <spd_sdram.h>
31 #include <i2c.h>
32 #include "../common/ppc440gx_i2c.h"
33 #include "../common/sb_common.h"
34
35 void fpga_init (void);
36
37 METROBOX_BOARD_ID_ST board_id_as[] =
38 { {"Undefined"}, /* Not specified */
39 {"2x10Gb"}, /* 2 ports, 10 GbE */
40 {"20x1Gb"}, /* 20 ports, 1 GbE */
41 {"Reserved"}, /* Reserved for future use */
42 };
43
44 /*************************************************************************
45 * board_early_init_f
46 *
47 * Setup chip selects, initialize the Opto-FPGA, initialize
48 * interrupt polarity and triggers.
49 ************************************************************************/
50 int board_early_init_f (void)
51 {
52 ppc440_gpio_regs_t *gpio_regs;
53
54 /* Enable GPIO interrupts */
55 mtsdr(sdr_pfc0, 0x00103E00);
56
57 /* Setup access for LEDs, and system topology info */
58 gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
59 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
60 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
61
62 /* Turn on all the leds for now */
63 gpio_regs->out = SBCOMMON_GPIO_LEDS;
64
65 /*--------------------------------------------------------------------+
66 | Initialize EBC CONFIG
67 +-------------------------------------------------------------------*/
68 mtebc(xbcfg,
69 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
70 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
71 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
72 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
73 EBC_CFG_PR_32);
74
75 /*--------------------------------------------------------------------+
76 | 1/2 MB FLASH. Initialize bank 0 with default values.
77 +-------------------------------------------------------------------*/
78 mtebc(pb0ap,
79 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
80 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
81 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
82 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
83 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
84 EBC_BXAP_PEN_DISABLED);
85
86 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
87 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
88 /*--------------------------------------------------------------------+
89 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
90 +-------------------------------------------------------------------*/
91 mtebc(pb1ap,
92 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
93 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
94 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
95 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
96 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
97 EBC_BXAP_PEN_DISABLED);
98
99 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
100 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
101
102 /*--------------------------------------------------------------------+
103 | Compact Flash, uses 2 Chip Selects (2 & 6)
104 +-------------------------------------------------------------------*/
105 mtebc(pb2ap,
106 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
107 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
108 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
109 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
110 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
111 EBC_BXAP_PEN_DISABLED);
112
113 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
114 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
115
116 /*--------------------------------------------------------------------+
117 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
118 +-------------------------------------------------------------------*/
119 mtebc(pb3ap,
120 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
121 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
122 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
123 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
124 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
125
126 mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
127 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
128
129 /*--------------------------------------------------------------------+
130 | MAC A for metrobox
131 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
132 | Initialize bank 4 with default values.
133 +-------------------------------------------------------------------*/
134 mtebc(pb4ap,
135 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
136 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
137 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
138 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
139 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
140
141 mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
142 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
143
144 /*--------------------------------------------------------------------+
145 | Metrobox MAC B Initialize bank 5 with default values.
146 | KA REF FPGA Initialize bank 5 with default values.
147 +-------------------------------------------------------------------*/
148 mtebc(pb5ap,
149 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
150 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
151 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
152 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
153 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
154
155 mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
156 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
157
158 /*--------------------------------------------------------------------+
159 | Compact Flash, uses 2 Chip Selects (2 & 6)
160 +-------------------------------------------------------------------*/
161 mtebc(pb6ap,
162 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
163 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
164 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
165 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
166 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
167 EBC_BXAP_PEN_DISABLED);
168
169 mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
170 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
171
172 /*--------------------------------------------------------------------+
173 | BME-32. Initialize bank 7 with default values.
174 +-------------------------------------------------------------------*/
175 mtebc(pb7ap,
176 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
177 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
178 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
179 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
180 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
181
182 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
183 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
184
185 /*--------------------------------------------------------------------+
186 * Setup the interrupt controller polarities, triggers, etc.
187 +-------------------------------------------------------------------*/
188 mtdcr (uic0sr, 0xffffffff); /* clear all */
189 mtdcr (uic0er, 0x00000000); /* disable all */
190 mtdcr (uic0cr, 0x00000000); /* all non- critical */
191 mtdcr (uic0pr, 0xfffffe03); /* polarity */
192 mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
193 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
194 mtdcr (uic0sr, 0xffffffff); /* clear all */
195
196 mtdcr (uic1sr, 0xffffffff); /* clear all */
197 mtdcr (uic1er, 0x00000000); /* disable all */
198 mtdcr (uic1cr, 0x00000000); /* all non-critical */
199 mtdcr (uic1pr, 0xffffc8ff); /* polarity */
200 mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
201 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
202 mtdcr (uic1sr, 0xffffffff); /* clear all */
203
204 mtdcr (uic2sr, 0xffffffff); /* clear all */
205 mtdcr (uic2er, 0x00000000); /* disable all */
206 mtdcr (uic2cr, 0x00000000); /* all non-critical */
207 mtdcr (uic2pr, 0xffff83ff); /* polarity */
208 mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
209 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
210 mtdcr (uic2sr, 0xffffffff); /* clear all */
211
212 mtdcr (uicb0sr, 0xfc000000); /* clear all */
213 mtdcr (uicb0er, 0x00000000); /* disable all */
214 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
215 mtdcr (uicb0pr, 0xfc000000);
216 mtdcr (uicb0tr, 0x00000000);
217 mtdcr (uicb0vr, 0x00000001);
218
219 fpga_init();
220
221 return 0;
222 }
223
224 /*************************************************************************
225 * checkboard
226 *
227 * Dump pertinent info to the console
228 ************************************************************************/
229 int checkboard (void)
230 {
231 sys_info_t sysinfo;
232 unsigned char brd_rev, brd_id;
233 unsigned short sernum;
234 unsigned char opto_rev, opto_id;
235 OPTO_FPGA_REGS_ST *opto_ps;
236
237 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
238
239 opto_rev = (unsigned char)((opto_ps->revision_ul &
240 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
241 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
242
243 opto_id = (unsigned char)((opto_ps->revision_ul &
244 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
245 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
246
247 brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
248 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
249 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
250
251 brd_id = (unsigned char)((opto_ps->boardinfo_ul &
252 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
253 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
254
255 get_sys_info (&sysinfo);
256
257 sernum = sbcommon_get_serial_number();
258 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
259 printf ("%s\n", METROBOX_U_BOOT_REL_STR);
260
261 printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
262 if (sbcommon_get_master()) {
263 printf("Slot 0 - Master\nSlave board");
264 if (sbcommon_secondary_present())
265 printf(" present\n");
266 else
267 printf(" not detected\n");
268 } else {
269 printf("Slot 1 - Slave\n\n");
270 }
271
272 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
273 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
274
275 /* Fix the ack in the bme 32 */
276 udelay(5000);
277 out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
278 asm("eieio");
279
280
281 return (0);
282 }
283
284 /*************************************************************************
285 * misc_init_f
286 *
287 * Initialize I2C bus one to gain access to the fans
288 ************************************************************************/
289 int misc_init_f (void)
290 {
291 /* Turn on i2c bus 1 */
292 puts ("I2C1: ");
293 i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
294 puts ("ready\n");
295
296 /* Turn on fans */
297 sbcommon_fans();
298
299 return (0);
300 }
301
302 /*************************************************************************
303 * misc_init_r
304 *
305 * Do nothing.
306 ************************************************************************/
307 int misc_init_r (void)
308 {
309 unsigned short sernum;
310 char envstr[255];
311 unsigned char opto_rev;
312 OPTO_FPGA_REGS_ST *opto_ps;
313
314 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
315
316 if(NULL != getenv("secondserial")) {
317 puts("secondserial is set, switching to second serial port\n");
318 setenv("stderr", "serial1");
319 setenv("stdout", "serial1");
320 setenv("stdin", "serial1");
321 }
322
323 setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
324
325 memset(envstr, 0, 255);
326 sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
327 setenv("bldstr", envstr);
328 saveenv();
329
330 if( getenv("autorecover")) {
331 setenv("autorecover", NULL);
332 saveenv();
333 sernum = sbcommon_get_serial_number();
334
335 printf("\nSetting up environment for automatic filesystem recovery\n");
336 /*
337 * Setup default bootargs
338 */
339 memset(envstr, 0, 255);
340 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
341 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
342 sernum, sernum);
343 setenv("bootargs", envstr);
344
345 /*
346 * Setup Default boot command
347 */
348 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
349 "fatload ide 0 8100000 pramdisk;"
350 "bootm 8000000 8100000");
351
352 printf("Done. Please type allow the system to continue to boot\n");
353 }
354
355 if( getenv("fakeled")) {
356 setenv("bootdelay", "-1");
357 saveenv();
358 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
359 opto_rev = (unsigned char)((opto_ps->revision_ul &
360 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
361 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
362
363 if(0x12 <= opto_rev) {
364 opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
365 }
366 }
367
368 return (0);
369 }
370
371 /*************************************************************************
372 * ide_set_reset
373 ************************************************************************/
374 #ifdef CONFIG_IDE_RESET
375 void ide_set_reset(int on)
376 {
377 OPTO_FPGA_REGS_ST *opto_ps;
378 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
379
380 if (on) { /* assert RESET */
381 opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
382 } else { /* release RESET */
383 opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
384 }
385 }
386 #endif /* CONFIG_IDE_RESET */
387
388 /*************************************************************************
389 * fpga_init
390 ************************************************************************/
391 void fpga_init(void)
392 {
393 OPTO_FPGA_REGS_ST *opto_ps;
394 unsigned char opto_rev;
395 unsigned long tmp;
396
397 /* Ensure we have power all around */
398 udelay(500);
399
400 /*
401 * Take appropriate hw bits out of reset
402 */
403 opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
404
405 tmp =
406 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
407 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
408 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
409 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
410 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
411 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
412 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
413 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
414 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
415 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
416 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
417 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
418 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
419 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
420 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
421 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
422 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
423 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
424 opto_ps->reset_ul = tmp;
425 /*
426 * Turn on the 'Slow Blink' for the System Error Led.
427 * Ensure FPGA rev is up to at least rev 0x12
428 */
429 opto_rev = (unsigned char)((opto_ps->revision_ul &
430 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
431 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
432 if(0x12 <= opto_rev) {
433 opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
434 }
435
436 asm("eieio");
437
438 return;
439 }
440
441 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
442 {
443 unsigned short sernum;
444 char envstr[255];
445
446 sernum = sbcommon_get_serial_number();
447
448 memset(envstr, 0, 255);
449 /*
450 * Setup our ip address
451 */
452 sprintf(envstr, "10.100.60.%d", sernum);
453
454 setenv("ipaddr", envstr);
455 /*
456 * Setup the host ip address
457 */
458 setenv("serverip", "10.100.17.10");
459
460 /*
461 * Setup default bootargs
462 */
463 memset(envstr, 0, 255);
464
465 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
466 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
467 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
468 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
469 sernum, sernum, sernum);
470
471 setenv("bootargs_nfs", envstr);
472 setenv("bootargs", envstr);
473
474 /*
475 * Setup CF bootargs
476 */
477 memset(envstr, 0, 255);
478 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
479 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
480 sernum, sernum);
481
482 setenv("bootargs_cf", envstr);
483
484 /*
485 * Setup Default boot command
486 */
487 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
488 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
489
490 /*
491 * Setup compact flash boot command
492 */
493 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
494
495 saveenv();
496
497
498 return(1);
499 }
500
501 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
502 {
503 unsigned short sernum;
504 char envstr[255];
505
506 sernum = sbcommon_get_serial_number();
507
508 printf("\nSetting up environment for filesystem recovery\n");
509 /*
510 * Setup default bootargs
511 */
512 memset(envstr, 0, 255);
513 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
514 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
515 sernum, sernum);
516
517 setenv("bootargs", envstr);
518
519 /*
520 * Setup Default boot command
521 */
522 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
523 "fatload ide 0 8100000 pramdisk;"
524 "bootm 8000000 8100000");
525
526 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
527 " please type fsrecover.sh<cr>\n");
528
529 return(1);
530 }
531
532 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
533 "mbsetup - Set environment to factory defaults\n", NULL);
534
535 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
536 "mbrecover - Set environment to allow for fs recovery\n", NULL);
Fork of the u-boot for for Samsung based MINI2440 board