board/sacsng/clkinit.h

   1 /*
   2  * (C) Copyright 2002
   3  * Custom IDEAS, Inc. <www.cideas.com>
   4  * Jon Diekema <diekema@cideas.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef FALSE
  26 #define FALSE 0
  27 #define TRUE (!FALSE)
  28 #endif
  29
  30 #define SLRCLK_EN_MASK  0x00040000 /* PA13 - SLRCLK_EN*     */
  31
  32 #define MIN_SAMPLE_RATE       4000 /* Minimum sample rate */
  33 #define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
  34 #define MAX_64x_SAMPLE_RATE  86805 /* Maximum  64x sample rate */
  35
  36 #define KHZ          ((uint)1000)
  37 #define MHZ          ((uint)(1000 * KHZ))
  38
  39 #define MCLK_BRG     3        /* MCLK, Master CLocK for the A/D & D/A   */
  40 #define SCLK_BRG     7        /* SCLK, Sample CLocK for the A/D & D/A   */
  41 #define LRCLK_BRG    5        /* LRCLK, L/R CLocK for the A/D & D/A     */
  42                               /*   0 == BRG1 (used for SMC1)            */
  43                               /*   1 == BRG2 (used for SMC2)            */
  44                               /*   2 == BRG3 (used for SCC1)            */
  45                               /*   3 == BRG4 (MCLK)                     */
  46                               /*   4 == BRG5                            */
  47                               /*   5 == BRG6 (LRCLK)                    */
  48                               /*   6 == BRG7                            */
  49                               /*   7 == BRG8 (SCLK)                     */
  50
  51 #define MCLK_DIVISOR  4       /*  SCLK = MCLK / MCLK_DIVISOR */
  52 #define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
  53                               /* LRCLK = SCLK / SCLK_DIVISOR */
  54
  55 #define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing      */
  56 #define RUN_SCLK_ON_BRG_INT      /* Run SCLK on BRG_INT instead of MCLK   */
  57                                  /* The 8260 (Mask B.3) seems to have     */
  58                                  /* problems generating SCLK from MCLK    */
  59                                  /* via CLK9.                             */
  60 #define RUN_LRCLK_ON_BRG_INT     /* Run LRCLK on BRG_INT instead of SCLK  */
  61                                  /* The 8260 (Mask B.3) seems to have     */
  62                                  /* problems generating LRCLK from SCLK   */
  63
  64 #define NUM_LRCLKS_TO_STABILIZE 1  /* Number of LRCLK period (sample)     */
  65                                    /* to wait for the clock to stabilize  */
  66
  67 #define CPM_CLK      (gd->bd->bi_cpmfreq)
  68 #define DFBRG        4
  69 #define BRG_INT_CLK  (CPM_CLK * 2 / DFBRG)
  70                               /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
  71                               /* BRG = CPM * 2 / 4                */
  72                               /* BRG = CPM / 2                    */
  73
  74 #define CPM_BRG_EXTC_MASK       ((uint)0x0000C000)
  75 #define CPM_BRG_EXTC_SHIFT      14
  76
  77 #define CPM_BRG_DIV16_MASK      ((uint)0x00000001)
  78 #define CPM_BRG_DIV16_SHIFT     1
  79
  80 #define CPM_BRG_EXTC_BRGCLK     0
  81 #define CPM_BRG_EXTC_CLK3       1
  82 #define CPM_BRG_EXTC_CLK9       CPM_BRG_EXTC_CLK3
  83 #define CPM_BRG_EXTC_CLK5       2
  84 #define CPM_BRG_EXTC_CLK15      CPM_BRG_EXTC_CLK5
  85
  86 #define IM_BRGC1 ((uint *)0xf00119f0)
  87 #define IM_BRGC2 ((uint *)0xf00119f4)
  88 #define IM_BRGC3 ((uint *)0xf00119f8)
  89 #define IM_BRGC4 ((uint *)0xf00119fc)
  90 #define IM_BRGC5 ((uint *)0xf00115f0)
  91 #define IM_BRGC6 ((uint *)0xf00115f4)
  92 #define IM_BRGC7 ((uint *)0xf00115f8)
  93 #define IM_BRGC8 ((uint *)0xf00115fc)
  94
  95 /*
  96  * External declarations
  97  */
  98
  99 extern int Daq64xSampling;
 100
 101 extern void Daq_BRG_Reset(uint brg);
 102 extern void Daq_BRG_Run(uint brg);
 103
 104 extern void Daq_BRG_Disable(uint brg);
 105 extern void Daq_BRG_Enable(uint brg);
 106
 107 extern uint Daq_BRG_Get_Div16(uint brg);
 108 extern void Daq_BRG_Set_Div16(uint brg, uint div16);
 109
 110 extern uint Daq_BRG_Get_Count(uint brg);
 111 extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
 112
 113 extern uint Daq_BRG_Get_ExtClk(uint brg);
 114 extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
 115 extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
 116
 117 extern uint Daq_BRG_Rate(uint brg);
 118
 119 extern uint Daq_Get_SampleRate(void);
 120
 121 extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
 122 extern void Daq_Stop_Clocks(void);
 123 extern void Daq_Start_Clocks(int sample_rate);
 124 extern void Daq_Display_Clocks(void);