Modified patch originates from Andy Green <andy@openmoko.com>
[u-boot-openmoko/mini2440.git] / board / neo1973 / gta01 / pcf50606.c
blob64c75f2e6d51b07014e68db824b8985a8de8596c
2 #include <common.h>
3 #include <pcf50606.h>
5 /* initial register set for PCF50606 in Neo1973 devices */
6 const u_int8_t pcf50606_initial_regs[__NUM_PCF50606_REGS] = {
7 [PCF50606_REG_OOCS] = 0x00,
8 /* gap */
9 [PCF50606_REG_INT1M] = 0x00,
10 [PCF50606_REG_INT2M] = 0x00,
11 [PCF50606_REG_INT3M] = PCF50606_INT3_TSCPRES,
12 [PCF50606_REG_OOCC1] = PCF50606_OOCC1_RTCWAK |
13 PCF50606_OOCC1_CHGWAK |
14 PCF50606_OOCC1_EXTONWAK_HIGH,
15 [PCF50606_REG_OOCC2] = PCF50606_OOCC2_ONKEYDB_14ms |
16 PCF50606_OOCC2_EXTONDB_14ms,
17 /* gap */
18 [PCF50606_REG_PSSC] = 0x00,
19 [PCF50606_REG_PWROKM] = 0x00,
20 /* gap */
21 #if defined(CONFIG_ARCH_GTA01B_v2)
22 [PCF50606_REG_DCDC1] = 0x1e, /* GL_3V3: off */
23 #elif defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4)
24 [PCF50606_REG_DCDC1] = 0x18, /* GL_1V5: off */
25 #endif
26 [PCF50606_REG_DCDC2] = 0x00,
27 [PCF50606_REG_DCDC3] = 0x00,
28 [PCF50606_REG_DCDC4] = 0x30, /* 1.25A */
30 [PCF50606_REG_DCDEC1] = 0xe8, /* IO_3V3: on */
31 [PCF50606_REG_DCDEC2] = 0x00,
33 #if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
34 [PCF50606_REG_DCUDC1] = 0xe3, /* CORE_1V8: 1.8V */
35 #elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
36 [PCF50606_REG_DCUDC1] = 0xe4, /* CORE_1V8: 2.1V */
37 #elif defined(CONFIG_ARCH_GTA01B_v4)
38 [PCF50606_REG_DCUDC1] = 0xc4, /* CORE_1V8: 2.1V if PWREN2 = HIGH */
39 #endif
40 [PCF50606_REG_DCUDC2] = 0x30, /* 1.25A current limit */
42 #if defined(CONFIG_ARCH_GTA01_v3)
43 [PCF50606_REG_IOREGC] = 0x13, /* VTCXO_2V8: off */
44 #elif defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \
45 defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4)
46 //see internal bug 94 [PCF50606_REG_IOREGC] = 0x18, /* CODEC_3V3: off */
47 [PCF50606_REG_IOREGC] = 0xf8, /* CODEC_3V3: on */
48 #endif
50 #if defined(CONFIG_ARCH_GTA01_v3) || defined(CONFIG_ARCH_GTA01_v4)
51 [PCF50606_REG_D1REGC1] = 0x15, /* VRF_3V: off */
52 #elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3) || \
53 defined(CONFIG_ARCH_GTA01B_v4)
54 [PCF50606_REG_D1REGC1] = 0x16, /* BT_3V15: off */
55 #endif
57 #if defined(CONFIG_ARCH_GTA01_v3)
58 [PCF50606_REG_D2REGC1] = 0xf8, /* SD_3V3: on */
59 #elif defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || \
60 defined(CONFIG_ARCH_GTA01B_v3) || defined(CONFIG_ARCH_GTA01B_v4)
61 [PCF50606_REG_D2REGC1] = 0x10, /* GL_2V5: off */
62 #endif
64 #if defined(CONFIG_ARCH_GTA01_v3)
65 [PCF50606_REG_D3REGC1] = 0x18, /* CODEC_3V3: off */
66 #elif defined(CONFIG_ARCH_GTA01_v4)
67 [PCF50606_REG_D3REGC1] = 0x13, /* VTXCO_2V8: off */
68 #elif defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
69 [PCF50606_REG_D3REGC1] = 0x00, /* USER1: off */
70 #elif defined(CONFIG_ARCH_GTA01B_v4)
71 [PCF50606_REG_D3REGC1] = 0xec, /* STBY_1V8: 2.1V */
72 #endif
74 [PCF50606_REG_LPREGC1] = 0xf8, /* LCM_3V3: on */
75 [PCF50606_REG_LPREGC2] = 0x00,
77 [PCF50606_REG_MBCC1] = 0x01, /* CHGAPE */
78 [PCF50606_REG_MBCC2] = 0x00, /* unlimited charging */
79 [PCF50606_REG_MBCC3] = 0x2a, /* 0.2*Ifast, 4.20V */
80 [PCF50606_REG_BBCC] = 0x1f, /* 400uA */
81 [PCF50606_REG_ADCC1] = 0x00,
82 [PCF50606_REG_ADCC2] = 0x00,
83 /* gap */
84 #if defined(CONFIG_ARCH_GTA01B_v4)
85 [PCF50606_REG_ACDC1] = 0x86, /* ACD thresh 1.6V, enabled */
86 #else
87 [PCF50606_REG_ACDC1] = 0x00,
88 #endif
89 [PCF50606_REG_BVMC] = PCF50606_BVMC_THRSHLD_3V3,
90 [PCF50606_REG_PWMC1] = 0x00,
91 [PCF50606_REG_LEDC1] = 0x00,
92 [PCF50606_REG_LEDC2] = 0x00,
93 [PCF50606_REG_GPOC1] = 0x00,
94 [PCF50606_REG_GPOC2] = 0x00,
95 [PCF50606_REG_GPOC3] = 0x00,
96 [PCF50606_REG_GPOC4] = 0x00,
97 [PCF50606_REG_GPOC5] = 0x00,