Modified patch originates from Andy Green <andy@openmoko.com>
[u-boot-openmoko/mini2440.git] / board / csb472 / csb472.c
blob833bbce923d90859f818d76fefcc1b985a82fad6
1 /*
2 * (C) Copyright 2004
3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
5 * See file CREDITS for list of people who contributed to this
6 * project.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
24 #include <common.h>
25 #include <asm/processor.h>
26 #include <i2c.h>
27 #include <miiphy.h>
28 #include <ppc4xx_enet.h>
31 * board_early_init_f: do early board initialization
34 int board_early_init_f(void)
36 /*-------------------------------------------------------------------------+
37 | Interrupt controller setup for the Walnut board.
38 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
39 | IRQ 16 405GP internally generated; active low; level sensitive
40 | IRQ 17-24 RESERVED
41 | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
42 | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
43 | IRQ 27 (EXT IRQ 2) Not Used
44 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
45 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
46 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
47 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
48 | Note for Walnut board:
49 | An interrupt taken for the FPGA (IRQ 25) indicates that either
50 | the Mouse, Keyboard, IRDA, or External Expansion caused the
51 | interrupt. The FPGA must be read to determine which device
52 | caused the interrupt. The default setting of the FPGA clears
54 +-------------------------------------------------------------------------*/
56 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
57 mtdcr (uicer, 0x00000000); /* disable all ints */
58 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
59 mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
60 mtdcr (uictr, 0x10000000); /* set int trigger levels */
61 mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
62 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
64 mtebc (epcr, 0xa8400000); /* EBC always driven */
66 return 0; /* success */
70 * checkboard: identify/verify the board we are running
72 * Remark: we just assume it is correct board here!
75 int checkboard(void)
77 printf("BOARD: Cogent CSB472\n");
79 return 0; /* success */
83 * initram: Determine the size of mounted DRAM
85 * Size is determined by reading SDRAM configuration registers as
86 * configured by initialization code
89 long initdram (int board_type)
91 ulong tot_size;
92 ulong bank_size;
93 ulong tmp;
95 tot_size = 0;
97 mtdcr (memcfga, mem_mb0cf);
98 tmp = mfdcr (memcfgd);
99 if (tmp & 0x00000001) {
100 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
101 tot_size += bank_size;
104 mtdcr (memcfga, mem_mb1cf);
105 tmp = mfdcr (memcfgd);
106 if (tmp & 0x00000001) {
107 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
108 tot_size += bank_size;
111 mtdcr (memcfga, mem_mb2cf);
112 tmp = mfdcr (memcfgd);
113 if (tmp & 0x00000001) {
114 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
115 tot_size += bank_size;
118 mtdcr (memcfga, mem_mb3cf);
119 tmp = mfdcr (memcfgd);
120 if (tmp & 0x00000001) {
121 bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
122 tot_size += bank_size;
125 return tot_size;
129 * last_stage_init: final configurations (such as PHY etc)
132 int last_stage_init(void)
134 /* initialize the PHY */
135 miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
137 /* AUTO neg */
138 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_BMCR,
139 PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
141 /* LEDs */
142 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);
144 return 0; /* success */