board/cogent/flash.h

   1 /**************** DEFINES for Intel 28F008S5 FLASH chip **********************/
   2
   3 /* register addresses, valid only following a I8S5_CMD_RD_ID command */
   4 #define I8S5_ADDR_MAN   0x00000 /* manufacturer's id */
   5 #define I8S5_ADDR_DEV   0x00001 /* device id */
   6 #define I8S5_ADDR_CFGM  0x00003 /* master lock configuration */
   7 #define I8S5_ADDR_CFG(b) (((b)<<16)|2) /* block lock configuration */
   8
   9 /* Commands */
  10 #define I8S5_CMD_RST    0xFF    /* reset flash */
  11 #define I8S5_CMD_RD_ID  0x90    /* read the id and lock bits */
  12 #define I8S5_CMD_RD_STAT 0x70   /* read the status register */
  13 #define I8S5_CMD_CLR_STAT 0x50  /* clear the staus register */
  14 #define I8S5_CMD_ERASE1 0x20    /* first word for block erase */
  15 #define I8S5_CMD_ERASE2 0xD0    /* second word for block erase */
  16 #define I8S5_CMD_PROG   0x40    /* program word command */
  17 #define I8S5_CMD_LOCK   0x60    /* first word for all lock commands */
  18 #define I8S5_CMD_SET_LOCK_BLK 0x01 /* 2nd word for set block lock bit */
  19 #define I8S5_CMD_SET_LOCK_MSTR 0xF1 /* 2nd word for set master lock bit */
  20 #define I8S5_CMD_CLR_LOCK_BLK 0xD0 /* 2nd word for clear block lock bit */
  21
  22 /* status register bits */
  23 #define I8S5_STAT_DPS   0x02    /* Device Protect Status */
  24 #define I8S5_STAT_PSS   0x04    /* Program Suspend Status */
  25 #define I8S5_STAT_VPPS  0x08    /* VPP Status */
  26 #define I8S5_STAT_PSLBS 0x10    /* Program and Set Lock Bit Status */
  27 #define I8S5_STAT_ECLBS 0x20    /* Erase and Clear Lock Bit Status */
  28 #define I8S5_STAT_ESS   0x40    /* Erase Suspend Status */
  29 #define I8S5_STAT_RDY   0x80    /* Write State Machine Status, 1=rdy */
  30
  31 #define I8S5_STAT_ERR   (I8S5_STAT_VPPS | I8S5_STAT_DPS | \
  32                             I8S5_STAT_ECLBS | I8S5_STAT_PSLBS)
  33
  34 /* ID and Lock Configuration */
  35 #define I8S5_RD_ID_LOCK 0x01    /* Bit 0 of each byte */
  36 #define I8S5_RD_ID_MAN  0x89    /* Manufacturer code = 0x89 */
  37 #define I8S5_RD_ID_DEV  0xA6    /* Device code = 0xA6, 28F008S5 */
  38
  39 /* dimensions */
  40 #define I8S5_NBLOCKS    16              /* a 28F008S5 consists of 16 blocks */
  41 #define I8S5_BLKSZ      (64*1024)       /* of 64Kbyte each */
  42 #define I8S5_SIZE       (I8S5_BLKSZ * I8S5_NBLOCKS)
  43
  44 /**************** DEFINES for Intel 28F800B5 FLASH chip **********************/
  45
  46 /* register addresses, valid only following a I8S5_CMD_RD_ID command */
  47 #define I8B5_ADDR_MAN   0x00000 /* manufacturer's id */
  48 #define I8B5_ADDR_DEV   0x00001 /* device id */
  49
  50 /* Commands */
  51 #define I8B5_CMD_RST    0xFF    /* reset flash */
  52 #define I8B5_CMD_RD_ID  0x90    /* read the id and lock bits */
  53 #define I8B5_CMD_RD_STAT 0x70   /* read the status register */
  54 #define I8B5_CMD_CLR_STAT 0x50  /* clear the staus register */
  55 #define I8B5_CMD_ERASE1 0x20    /* first word for block erase */
  56 #define I8B5_CMD_ERASE2 0xD0    /* second word for block erase */
  57 #define I8B5_CMD_PROG   0x40    /* program word command */
  58
  59 /* status register bits */
  60 #define I8B5_STAT_VPPS  0x08    /* VPP Status */
  61 #define I8B5_STAT_DWS   0x10    /* Program and Set Lock Bit Status */
  62 #define I8B5_STAT_ES    0x20    /* Erase and Clear Lock Bit Status */
  63 #define I8B5_STAT_ESS   0x40    /* Erase Suspend Status */
  64 #define I8B5_STAT_RDY   0x80    /* Write State Machine Status, 1=rdy */
  65
  66 #define I8B5_STAT_ERR   (I8B5_STAT_VPPS | I8B5_STAT_DWS | I8B5_STAT_ES)
  67
  68 /* ID Configuration */
  69 #define I8B5_RD_ID_MAN  0x89    /* Manufacturer code = 0x89 */
  70 #define I8B5_RD_ID_DEV1 0x889D  /* Device code = 0x889D, 28F800B5 */
  71
  72 /* dimensions */
  73 #define I8B5_NBLOCKS    8               /* a 28F008S5 consists of 16 blocks */
  74 #define I8B5_BLKSZ      (128*1024)      /* of 64Kbyte each */
  75 #define I8B5_SIZE       (I8B5_BLKSZ * I8B5_NBLOCKS)
  76
  77 /****************** DEFINES for Cogent CMA302 Flash **************************/
  78
  79 /*
  80  * Quoted from the CMA302 manual:
  81  *
  82  * Although the CMA302 supports 64-bit reads, all writes must be done with
  83  * word size only. When programming the CMA302, the FLASH devices appear as 2
  84  * banks of interleaved, 32-bit wide FLASH. Each 32-bit word consists of four
  85  * 28F008S5 devices. The first bank is accessed when the word address is even,
  86  * while the second bank is accessed when the word address is odd. This must
  87  * be taken into account when programming the desired word. Also, when locking
  88  * blocks, software must lock both banks. The CMA302 does not directly support
  89  * byte writing.  Programming and/or erasing individual bytes is done with
  90  * selective use of the Write Command.  By not placing the Write Command value
  91  * on a particular byte lane, that byte will not be written with the following
  92  * Write Data. Also, remember that within a byte lane (i.e. D0-7), there are
  93  * two 28F008S5 devices, one for each bank or every other word.
  94  *
  95  * End quote.
  96  *
  97  * Each 28F008S5 is 8Mbit, with 8 bit wide data. i.e. each is 1Mbyte. The
  98  * chips are arranged on the CMA302 in multiples of two banks, each bank having
  99  * 4 chips. Each bank must be accessed as a single 32 bit wide device (i.e.
 100  * aligned on a 32 bit boundary), with each byte lane within the 32 bits (0-3)
 101  * going to each of the 4 chips and the word address selecting the bank, even
 102  * being the low bank and odd the high bank. For 64bit reads, both banks are
 103  * read simultaneously with the second bank on byte lanes 4-7. Each 28F008S5
 104  * consists of 16 64Kbyte "block"s. Before programming a byte, the block that
 105  * the byte resides within must be erased. So if you want to program contiguous
 106  * memory locations, you must erase all 8 chips at the same time. i.e. the
 107  * flash on the CMA302 can be viewed as a number of 512Kbyte blocks.
 108  *
 109  * Note: I am going to treat banks as 8 Mbytes (1Meg of 64bit words), whereas
 110  * the example code treats them as a pair of interleaved 1 Mbyte x 32bit banks.
 111  */
 112
 113 typedef unsigned long c302f_word_t;     /* 32 or 64 bit unsigned integer */
 114 typedef volatile c302f_word_t *c302f_addr_t;
 115 typedef unsigned long c302f_size_t;     /* want this big - at least 32 bit */
 116
 117 /* layout of banks on cma302 board */
 118 #define C302F_BNK_WIDTH         8       /* each bank is 8 chips wide */
 119 #define C302F_BNK_WSHIFT        3       /* log base 2 of C302F_BNK_WIDTH */
 120 #define C302F_BNK_NBLOCKS       I8S5_NBLOCKS
 121 #define C302F_BNK_BLKSZ         (I8S5_BLKSZ * C302F_BNK_WIDTH)
 122 #define C302F_BNK_SIZE          (I8S5_SIZE * C302F_BNK_WIDTH)
 123
 124 #define C302F_MAX_BANKS         2       /* up to 2 banks (8M each) on CMA302 */
 125
 126 /* align addresses and sizes to bank boundaries */
 127 #define C302F_BNK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \
 128                                     & ~(C302F_BNK_WIDTH - 1)))
 129 #define C302F_BNK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BNK_ADDR_ALIGN( \
 130                                     (c302f_size_t)(s) + (C302F_BNK_WIDTH - 1)))
 131
 132 /* align addresses and sizes to block boundaries */
 133 #define C302F_BLK_ADDR_ALIGN(a) ((c302f_addr_t)((c302f_size_t)(a) \
 134                                     & ~(C302F_BNK_BLKSZ - 1)))
 135 #define C302F_BLK_SIZE_ALIGN(s) ((c302f_size_t)C302F_BLK_ADDR_ALIGN( \
 136                                     (c302f_size_t)(s) + (C302F_BNK_BLKSZ - 1)))
 137
 138 /* add a byte offset to a flash address */
 139 #define C302F_ADDR_ADD_BYTEOFF(a,o) \
 140                                 (c302f_addr_t)((c302f_size_t)(a) + (o))
 141
 142 /* get base address of bank b, given flash base address a */
 143 #define C302F_BNK_ADDR_BASE(a,b) \
 144                                 C302F_ADDR_ADD_BYTEOFF((a), \
 145                                     (c302f_size_t)(b) * C302F_BNK_SIZE)
 146
 147 /* adjust an address a (within a bank) to next word, block or bank */
 148 #define C302F_BNK_ADDR_NEXT_WORD(a) \
 149                                 C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_WIDTH)
 150 #define C302F_BNK_ADDR_NEXT_BLK(a) \
 151                                 C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_BLKSZ)
 152 #define C302F_BNK_ADDR_NEXT_BNK(a) \
 153                                 C302F_ADDR_ADD_BYTEOFF((a), C302F_BNK_SIZE)
 154
 155 /* get bank address of chip register r given a bank base address a */
 156 #define C302F_BNK_ADDR_I8S5REG(a,r) \
 157                                 C302F_ADDR_ADD_BYTEOFF((a), \
 158                                     (r) << C302F_BNK_WSHIFT)
 159
 160 /* make a bank representation for each chip address */
 161
 162 #define C302F_BNK_ADDR_MAN(a)   C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_MAN)
 163 #define C302F_BNK_ADDR_DEV(a)   C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_DEV)
 164 #define C302F_BNK_ADDR_CFGM(a)  C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFGM)
 165 #define C302F_BNK_ADDR_CFG(b,a) C302F_BNK_ADDR_I8S5REG((a), I8S5_ADDR_CFG(b))
 166
 167 /*
 168  * replicate a chip cmd/stat/rd value into each byte position within a word
 169  * so that multiple chips are accessed in a single word i/o operation
 170  *
 171  * this must be as wide as the c302f_word_t type
 172  */
 173 #define C302F_FILL_WORD(o)      (((unsigned long)(o) << 24) | \
 174                                     ((unsigned long)(o) << 16) | \
 175                                     ((unsigned long)(o) << 8) | \
 176                                     (unsigned long)(o))
 177
 178 /* make a bank representation for each chip cmd/stat/rd value */
 179
 180 /* Commands */
 181 #define C302F_BNK_CMD_RST       C302F_FILL_WORD(I8S5_CMD_RST)
 182 #define C302F_BNK_CMD_RD_ID     C302F_FILL_WORD(I8S5_CMD_RD_ID)
 183 #define C302F_BNK_CMD_RD_STAT   C302F_FILL_WORD(I8S5_CMD_RD_STAT)
 184 #define C302F_BNK_CMD_CLR_STAT  C302F_FILL_WORD(I8S5_CMD_CLR_STAT)
 185 #define C302F_BNK_CMD_ERASE1    C302F_FILL_WORD(I8S5_CMD_ERASE1)
 186 #define C302F_BNK_CMD_ERASE2    C302F_FILL_WORD(I8S5_CMD_ERASE2)
 187 #define C302F_BNK_CMD_PROG      C302F_FILL_WORD(I8S5_CMD_PROG)
 188 #define C302F_BNK_CMD_LOCK      C302F_FILL_WORD(I8S5_CMD_LOCK)
 189 #define C302F_BNK_CMD_SET_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_SET_LOCK_BLK)
 190 #define C302F_BNK_CMD_SET_LOCK_MSTR C302F_FILL_WORD(I8S5_CMD_SET_LOCK_MSTR)
 191 #define C302F_BNK_CMD_CLR_LOCK_BLK C302F_FILL_WORD(I8S5_CMD_CLR_LOCK_BLK)
 192
 193 /* status register bits */
 194 #define C302F_BNK_STAT_DPS      C302F_FILL_WORD(I8S5_STAT_DPS)
 195 #define C302F_BNK_STAT_PSS      C302F_FILL_WORD(I8S5_STAT_PSS)
 196 #define C302F_BNK_STAT_VPPS     C302F_FILL_WORD(I8S5_STAT_VPPS)
 197 #define C302F_BNK_STAT_PSLBS    C302F_FILL_WORD(I8S5_STAT_PSLBS)
 198 #define C302F_BNK_STAT_ECLBS    C302F_FILL_WORD(I8S5_STAT_ECLBS)
 199 #define C302F_BNK_STAT_ESS      C302F_FILL_WORD(I8S5_STAT_ESS)
 200 #define C302F_BNK_STAT_RDY      C302F_FILL_WORD(I8S5_STAT_RDY)
 201
 202 #define C302F_BNK_STAT_ERR      C302F_FILL_WORD(I8S5_STAT_ERR)
 203
 204 /* ID and Lock Configuration */
 205 #define C302F_BNK_RD_ID_LOCK    C302F_FILL_WORD(I8S5_RD_ID_LOCK)
 206 #define C302F_BNK_RD_ID_MAN     C302F_FILL_WORD(I8S5_RD_ID_MAN)
 207 #define C302F_BNK_RD_ID_DEV     C302F_FILL_WORD(I8S5_RD_ID_DEV)
 208
 209 /*************** DEFINES for Cogent Motherboard Flash ************************/
 210
 211 typedef unsigned short cmbf_word_t;     /* 16 bit unsigned integer */
 212 typedef volatile cmbf_word_t *cmbf_addr_t;
 213 typedef unsigned long cmbf_size_t;      /* want this big - at least 32 bit */
 214
 215 /* layout of banks on cogent motherboard - only 1 bank, 16 bit wide */
 216 #define CMBF_BNK_WIDTH          1       /* each bank is one chip wide */
 217 #define CMBF_BNK_WSHIFT 0       /* log base 2 of CMBF_BNK_WIDTH */
 218 #define CMBF_BNK_NBLOCKS        I8B5_NBLOCKS
 219 #define CMBF_BNK_BLKSZ          (I8B5_BLKSZ * CMBF_BNK_WIDTH)
 220 #define CMBF_BNK_SIZE           (I8B5_SIZE * CMBF_BNK_WIDTH)
 221
 222 #define CMBF_MAX_BANKS          1       /* only 1 x 1Mbyte bank on cogent m/b */
 223
 224 /* align addresses and sizes to bank boundaries */
 225 #define CMBF_BNK_ADDR_ALIGN(a)  ((c302f_addr_t)((c302f_size_t)(a) \
 226                                     & ~(CMBF_BNK_WIDTH - 1)))
 227 #define CMBF_BNK_SIZE_ALIGN(s)  ((c302f_size_t)CMBF_BNK_ADDR_ALIGN( \
 228                                     (c302f_size_t)(s) + (CMBF_BNK_WIDTH - 1)))
 229
 230 /* align addresses and sizes to block boundaries */
 231 #define CMBF_BLK_ADDR_ALIGN(a)  ((c302f_addr_t)((c302f_size_t)(a) \
 232                                     & ~(CMBF_BNK_BLKSZ - 1)))
 233 #define CMBF_BLK_SIZE_ALIGN(s)  ((c302f_size_t)CMBF_BLK_ADDR_ALIGN( \
 234                                     (c302f_size_t)(s) + (CMBF_BNK_BLKSZ - 1)))
 235
 236 /* add a byte offset to a flash address */
 237 #define CMBF_ADDR_ADD_BYTEOFF(a,o) \
 238                                 (c302f_addr_t)((c302f_size_t)(a) + (o))
 239
 240 /* get base address of bank b, given flash base address a */
 241 #define CMBF_BNK_ADDR_BASE(a,b) \
 242                                 CMBF_ADDR_ADD_BYTEOFF((a), \
 243                                     (c302f_size_t)(b) * CMBF_BNK_SIZE)
 244
 245 /* adjust an address a (within a bank) to next word, block or bank */
 246 #define CMBF_BNK_ADDR_NEXT_WORD(a) \
 247                                 CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_WIDTH)
 248 #define CMBF_BNK_ADDR_NEXT_BLK(a) \
 249                                 CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_BLKSZ)
 250 #define CMBF_BNK_ADDR_NEXT_BNK(a) \
 251                                 CMBF_ADDR_ADD_BYTEOFF((a), CMBF_BNK_SIZE)
 252
 253 /* get bank address of chip register r given a bank base address a */
 254 #define CMBF_BNK_ADDR_I8B5REG(a,r) \
 255                                 CMBF_ADDR_ADD_BYTEOFF((a), \
 256                                     (r) << CMBF_BNK_WSHIFT)
 257
 258 /* make a bank representation for each chip address */
 259
 260 #define CMBF_BNK_ADDR_MAN(a)    CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_MAN)
 261 #define CMBF_BNK_ADDR_DEV(a)    CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_DEV)
 262 #define CMBF_BNK_ADDR_CFGM(a)   CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFGM)
 263 #define CMBF_BNK_ADDR_CFG(b,a)  CMBF_BNK_ADDR_I8B5REG((a), I8B5_ADDR_CFG(b))
 264
 265 /*
 266  * replicate a chip cmd/stat/rd value into each byte position within a word
 267  * so that multiple chips are accessed in a single word i/o operation
 268  *
 269  * this must be as wide as the c302f_word_t type
 270  */
 271 #define CMBF_FILL_WORD(o)       (((unsigned long)(o) << 24) | \
 272                                     ((unsigned long)(o) << 16) | \
 273                                     ((unsigned long)(o) << 8) | \
 274                                     (unsigned long)(o))
 275
 276 /* make a bank representation for each chip cmd/stat/rd value */
 277
 278 /* Commands */
 279 #define CMBF_BNK_CMD_RST        CMBF_FILL_WORD(I8B5_CMD_RST)
 280 #define CMBF_BNK_CMD_RD_ID      CMBF_FILL_WORD(I8B5_CMD_RD_ID)
 281 #define CMBF_BNK_CMD_RD_STAT    CMBF_FILL_WORD(I8B5_CMD_RD_STAT)
 282 #define CMBF_BNK_CMD_CLR_STAT   CMBF_FILL_WORD(I8B5_CMD_CLR_STAT)
 283 #define CMBF_BNK_CMD_ERASE1     CMBF_FILL_WORD(I8B5_CMD_ERASE1)
 284 #define CMBF_BNK_CMD_ERASE2     CMBF_FILL_WORD(I8B5_CMD_ERASE2)
 285 #define CMBF_BNK_CMD_PROG       CMBF_FILL_WORD(I8B5_CMD_PROG)
 286 #define CMBF_BNK_CMD_LOCK       CMBF_FILL_WORD(I8B5_CMD_LOCK)
 287 #define CMBF_BNK_CMD_SET_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_BLK)
 288 #define CMBF_BNK_CMD_SET_LOCK_MSTR CMBF_FILL_WORD(I8B5_CMD_SET_LOCK_MSTR)
 289 #define CMBF_BNK_CMD_CLR_LOCK_BLK CMBF_FILL_WORD(I8B5_CMD_CLR_LOCK_BLK)
 290
 291 /* status register bits */
 292 #define CMBF_BNK_STAT_DPS       CMBF_FILL_WORD(I8B5_STAT_DPS)
 293 #define CMBF_BNK_STAT_PSS       CMBF_FILL_WORD(I8B5_STAT_PSS)
 294 #define CMBF_BNK_STAT_VPPS      CMBF_FILL_WORD(I8B5_STAT_VPPS)
 295 #define CMBF_BNK_STAT_PSLBS     CMBF_FILL_WORD(I8B5_STAT_PSLBS)
 296 #define CMBF_BNK_STAT_ECLBS     CMBF_FILL_WORD(I8B5_STAT_ECLBS)
 297 #define CMBF_BNK_STAT_ESS       CMBF_FILL_WORD(I8B5_STAT_ESS)
 298 #define CMBF_BNK_STAT_RDY       CMBF_FILL_WORD(I8B5_STAT_RDY)
 299
 300 #define CMBF_BNK_STAT_ERR       CMBF_FILL_WORD(I8B5_STAT_ERR)
 301
 302 /* ID and Lock Configuration */
 303 #define CMBF_BNK_RD_ID_LOCK     CMBF_FILL_WORD(I8B5_RD_ID_LOCK)
 304 #define CMBF_BNK_RD_ID_MAN      CMBF_FILL_WORD(I8B5_RD_ID_MAN)
 305 #define CMBF_BNK_RD_ID_DEV      CMBF_FILL_WORD(I8B5_RD_ID_DEV)