3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
5 * Copyright 2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/immap_fsl_pci.h>
33 #include <spd_sdram.h>
36 #include <fdt_support.h>
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size
);
42 long int fixed_sdram(void);
44 int board_early_init_f (void)
51 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
52 volatile ccsr_lbc_t
*lbc
= (void *)(CFG_MPC85xx_LBC_ADDR
);
53 volatile ccsr_local_ecm_t
*ecm
= (void *)(CFG_MPC85xx_ECM_ADDR
);
55 if ((uint
)&gur
->porpllsr
!= 0xe00e0000) {
56 printf("immap size error %x\n",&gur
->porpllsr
);
58 printf ("Board: ATUM8548\n");
60 lbc
->ltesr
= 0xffffffff; /* Clear LBC error interrupts */
61 lbc
->lteir
= 0xffffffff; /* Enable LBC error interrupts */
62 ecm
->eedr
= 0xffffffff; /* Clear ecm errors */
63 ecm
->eeer
= 0xffffffff; /* Enable ecm errors */
68 #if !defined(CONFIG_SPD_EEPROM)
69 /*************************************************************************
70 * fixed sdram init -- doesn't use serial presence detect.
71 ************************************************************************/
72 long int fixed_sdram (void)
74 volatile ccsr_ddr_t
*ddr
= (void *)(CFG_MPC85xx_DDR_ADDR
);
76 ddr
->cs0_bnds
= CFG_DDR_CS0_BNDS
;
77 ddr
->cs0_config
= CFG_DDR_CS0_CONFIG
;
78 ddr
->timing_cfg_0
= CFG_DDR_TIMING_0
;
79 ddr
->timing_cfg_1
= CFG_DDR_TIMING_1
;
80 ddr
->timing_cfg_2
= CFG_DDR_TIMING_2
;
81 ddr
->sdram_mode
= CFG_DDR_MODE
;
82 ddr
->sdram_interval
= CFG_DDR_INTERVAL
;
83 #if defined (CONFIG_DDR_ECC)
84 ddr
->err_disable
= 0x0000000D;
85 ddr
->err_sbe
= 0x00ff0000;
87 asm("sync;isync;msync");
89 #if defined (CONFIG_DDR_ECC)
90 /* Enable ECC checking */
91 ddr
->sdram_cfg
= (CFG_DDR_CONTROL
| 0x20000000);
93 ddr
->sdram_cfg
= CFG_DDR_CONTROL
;
95 asm("sync; isync; msync");
97 return CFG_SDRAM_SIZE
* 1024 * 1024;
99 #endif /* !defined(CONFIG_SPD_EEPROM) */
102 initdram(int board_type
)
106 puts("Initializing\n");
108 #if defined(CONFIG_SPD_EEPROM)
110 dram_size
= spd_sdram ();
112 puts("fixed_sdram\n");
113 dram_size
= fixed_sdram ();
116 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
118 * Initialize and enable DDR ECC.
120 ddr_enable_ecc(dram_size
);
126 #if defined(CFG_DRAM_TEST)
130 uint
*pstart
= (uint
*) CFG_MEMTEST_START
;
131 uint
*pend
= (uint
*) CFG_MEMTEST_END
;
134 printf("Testing DRAM from 0x%08x to 0x%08x\n",
138 printf("DRAM test phase 1:\n");
139 for (p
= pstart
; p
< pend
; p
++) {
140 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint
) p
);
144 for (p
= pstart
; p
< pend
; p
++) {
145 if (*p
!= 0xaaaaaaaa) {
146 printf ("DRAM test fails at: %08x\n", (uint
) p
);
151 printf("DRAM test phase 2:\n");
152 for (p
= pstart
; p
< pend
; p
++)
155 for (p
= pstart
; p
< pend
; p
++) {
156 if (*p
!= 0x55555555) {
157 printf ("DRAM test fails at: %08x\n", (uint
) p
);
162 printf("DRAM test passed.\n");
168 static struct pci_controller pci1_hose
;
172 static struct pci_controller pci2_hose
;
176 static struct pci_controller pcie1_hose
;
179 int first_free_busno
=0;
184 volatile ccsr_gur_t
*gur
= (void *)(CFG_MPC85xx_GUTS_ADDR
);
186 uint devdisr
= gur
->devdisr
;
187 uint io_sel
= (gur
->pordevsr
& MPC85xx_PORDEVSR_IO_SEL
) >> 19;
188 uint host_agent
= (gur
->porbmsr
& MPC85xx_PORBMSR_HA
) >> 16;
190 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
191 devdisr
, io_sel
, host_agent
);
193 /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
194 gur
->clkocr
|= MPC85xx_ATUM_CLKOCR
;
197 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII1_DIS
))
198 printf (" eTSEC1 is in sgmii mode.\n");
199 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII2_DIS
))
200 printf (" eTSEC2 is in sgmii mode.\n");
201 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
202 printf (" eTSEC3 is in sgmii mode.\n");
203 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII4_DIS
))
204 printf (" eTSEC4 is in sgmii mode.\n");
209 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCIE1_ADDR
;
210 extern void fsl_pci_init(struct pci_controller
*hose
);
211 struct pci_controller
*hose
= &pcie1_hose
;
212 int pcie_ep
= (host_agent
== 5);
213 int pcie_configured
= io_sel
& 6;
215 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
216 printf ("\n PCIE1 connected to slot as %s (base address %x)",
217 pcie_ep
? "End Point" : "Root Complex",
219 if (pci
->pme_msg_det
) {
220 pci
->pme_msg_det
= 0xffffffff;
221 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
226 pci_set_region(hose
->regions
+ 0,
230 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
232 /* outbound memory */
233 pci_set_region(hose
->regions
+ 1,
240 pci_set_region(hose
->regions
+ 2,
246 hose
->region_count
= 3;
247 #ifdef CFG_PCIE1_MEM_BASE2
248 /* outbound memory */
249 pci_set_region(hose
->regions
+ 3,
254 hose
->region_count
++;
256 hose
->first_busno
=first_free_busno
;
258 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
262 first_free_busno
=hose
->last_busno
+1;
263 printf(" PCIE1 on bus %02x - %02x\n",
264 hose
->first_busno
,hose
->last_busno
);
267 printf (" PCIE1: disabled\n");
272 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE
; /* disable */
277 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCI1_ADDR
;
278 extern void fsl_pci_init(struct pci_controller
*hose
);
279 struct pci_controller
*hose
= &pci1_hose
;
281 uint pci_agent
= (host_agent
== 6);
282 uint pci_speed
= 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
283 uint pci_32
= gur
->pordevsr
& MPC85xx_PORDEVSR_PCI1_PCI32
; /* PORDEVSR[15] */
284 uint pci_arb
= gur
->pordevsr
& MPC85xx_PORDEVSR_PCI1_ARB
; /* PORDEVSR[14] */
285 uint pci_clk_sel
= gur
->porpllsr
& MPC85xx_PORDEVSR_PCI1_SPD
; /* PORPLLSR[16] */
287 if (!(devdisr
& MPC85xx_DEVDISR_PCI1
)) {
288 printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
290 (pci_speed
== 33333000) ? "33" :
291 (pci_speed
== 66666000) ? "66" : "unknown",
292 pci_clk_sel
? "sync" : "async",
293 pci_agent
? "agent" : "host",
294 pci_arb
? "arbiter" : "external-arbiter",
299 pci_set_region(hose
->regions
+ 0,
303 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
305 /* outbound memory */
306 pci_set_region(hose
->regions
+ 1,
313 pci_set_region(hose
->regions
+ 2,
318 hose
->region_count
= 3;
319 hose
->first_busno
=first_free_busno
;
320 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
323 first_free_busno
=hose
->last_busno
+1;
324 printf ("PCI1 on bus %02x - %02x\n",
325 hose
->first_busno
,hose
->last_busno
);
327 printf (" PCI1: disabled\n");
331 gur
->devdisr
|= MPC85xx_DEVDISR_PCI1
; /* disable */
336 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCI2_ADDR
;
337 extern void fsl_pci_init(struct pci_controller
*hose
);
338 struct pci_controller
*hose
= &pci2_hose
;
340 if (!(devdisr
& MPC85xx_DEVDISR_PCI2
)) {
341 pci_set_region(hose
->regions
+ 0,
345 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
347 pci_set_region(hose
->regions
+ 1,
353 pci_set_region(hose
->regions
+ 2,
358 hose
->region_count
= 3;
359 hose
->first_busno
=first_free_busno
;
360 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
363 first_free_busno
=hose
->last_busno
+1;
364 printf ("PCI2 on bus %02x - %02x\n",
365 hose
->first_busno
,hose
->last_busno
);
367 printf (" PCI2: disabled\n");
371 gur
->devdisr
|= MPC85xx_DEVDISR_PCI2
;
376 int last_stage_init(void)
378 int ic
= icache_status ();
379 printf ("icache_status: %d\n", ic
);
383 #if defined(CONFIG_OF_BOARD_SETUP)
386 ft_board_setup(void *blob
, bd_t
*bd
)
391 ft_cpu_setup(blob
, bd
);
393 node
= fdt_path_offset(blob
, "/aliases");
397 path
= fdt_getprop(blob
, node
, "pci0", NULL
);
399 tmp
[1] = pci1_hose
.last_busno
- pci1_hose
.first_busno
;
400 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
404 path
= fdt_getprop(blob
, node
, "pci1", NULL
);
406 tmp
[1] = pci2_hose
.last_busno
- pci2_hose
.first_busno
;
407 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);
411 path
= fdt_getprop(blob
, node
, "pci2", NULL
);
413 tmp
[1] = pcie1_hose
.last_busno
- pcie1_hose
.first_busno
;
414 do_fixup_by_path(blob
, path
, "bus-range", &tmp
, 8, 1);