board/amcc/kilauea/kilauea.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ppc4xx.h>
  26 #include <ppc405.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/processor.h>
  30 #include <asm/io.h>
  31
  32 #if defined(CONFIG_PCI)
  33 #include <pci.h>
  34 #include <asm/4xx_pcie.h>
  35 #endif
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
  40
  41 /*
  42  * Board early initialization function
  43  */
  44 int board_early_init_f (void)
  45 {
  46         u32 val;
  47
  48         /*--------------------------------------------------------------------+
  49          | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
  50          +--------------------------------------------------------------------+
  51         +---------------------------------------------------------------------+
  52         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
  53         +---------+-----------------------------------+-------+-------+-------+
  54         | IRQ 00  | UART0                             | High  | Level | Non   |
  55         | IRQ 01  | UART1                             | High  | Level | Non   |
  56         | IRQ 02  | IIC0                              | High  | Level | Non   |
  57         | IRQ 03  | TBD                               | High  | Level | Non   |
  58         | IRQ 04  | TBD                               | High  | Level | Non   |
  59         | IRQ 05  | EBM                               | High  | Level | Non   |
  60         | IRQ 06  | BGI                               | High  | Level | Non   |
  61         | IRQ 07  | IIC1                              | Rising| Edge  | Non   |
  62         | IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
  63         | IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
  64         | IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
  65         | IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
  66         | IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
  67         | IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
  68         | IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
  69         | IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
  70         | IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
  71         | IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
  72         | IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
  73         | IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
  74         | IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
  75         | IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
  76         | IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
  77         | IRQ 23  | Security EIP-94                   | High  | Level | Non   |
  78         | IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
  79         | IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
  80         | IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
  81         | IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
  82         | IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
  83         | IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
  84         | IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
  85         | IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
  86         |----------------------------------------------------------------------
  87         | IRQ 32  | MAL Serr                          | High  | Level | Non   |
  88         | IRQ 33  | MAL Txde                          | High  | Level | Non   |
  89         | IRQ 34  | MAL Rxde                          | High  | Level | Non   |
  90         | IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
  91         | IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
  92         | IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
  93         | IRQ 38  | NDFC                              | High  | Level | Non   |
  94         | IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
  95         | IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
  96         | IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
  97         | IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
  98         | IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
  99         | IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
 100         | IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
 101         | IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
 102         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
 103         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
 104         | IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
 105         | IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
 106         | IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
 107         | IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
 108         | IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
 109         | IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
 110         | IRQ 55  | Serial ROM                        | High  | Level | Non   |
 111         | IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
 112         | IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
 113         | IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
 114         | IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
 115         | IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
 116         | IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
 117         | IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
 118         |----------------------------------------------------------------------
 119         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
 120         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
 121         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 122         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 123         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
 124         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 125         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
 126         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
 127         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
 128         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
 129         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 130         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 131         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
 132         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 133         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
 134         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
 135         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
 136         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
 137         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 138         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 139         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
 140         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 141         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
 142         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
 143         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
 144         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 145         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 146         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 147         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 148         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 149         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
 150         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
 151         |---------------------------------------------------------------------
 152         +---------+-----------------------------------+-------+-------+------*/
 153         /*--------------------------------------------------------------------+
 154          | Initialise UIC registers.  Clear all interrupts.  Disable all
 155          | interrupts.
 156          | Set critical interrupt values.  Set interrupt polarities.  Set
 157          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 158          | interrupts again.
 159          +-------------------------------------------------------------------*/
 160
 161         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
 162         mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
 163         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
 164         mtdcr (uic2pr, 0xf7ffffff);     /* Set Interrupt Polarities */
 165         mtdcr (uic2tr, 0x01e1fff8);     /* Set Interrupt Trigger Levels */
 166         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
 167         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
 168         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
 169
 170         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
 171         mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
 172         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
 173         mtdcr (uic1pr, 0xfffac785);     /* Set Interrupt Polarities */
 174         mtdcr (uic1tr, 0x001d0040);     /* Set Interrupt Trigger Levels */
 175         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
 176         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
 177         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
 178
 179         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
 180         mtdcr (uic0er, 0x0000000a);     /* Disable all interrupts */
 181                                         /* Except cascade UIC0 and UIC1 */
 182         mtdcr (uic0cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
 183         mtdcr (uic0pr, 0xffbfefef);     /* Set Interrupt Polarities */
 184         mtdcr (uic0tr, 0x00007000);     /* Set Interrupt Trigger Levels */
 185         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
 186         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
 187         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
 188
 189         /*
 190          * Note: Some cores are still in reset when the chip starts, so
 191          * take them out of reset
 192          */
 193         mtsdr(SDR0_SRST, 0);
 194
 195         /* Configure 405EX for NAND usage */
 196         val = SDR0_CUST0_MUX_NDFC_SEL |
 197                 SDR0_CUST0_NDFC_ENABLE |
 198                 SDR0_CUST0_NDFC_BW_8_BIT |
 199                 SDR0_CUST0_NRB_BUSY |
 200                 (0x80000000 >> (28 + CFG_NAND_CS));
 201         mtsdr(SDR0_CUST0, val);
 202
 203         /*
 204          * Configure PFC (Pin Function Control) registers
 205          * -> Enable USB
 206          */
 207         val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
 208         mtsdr(SDR0_PFC1, val);
 209
 210         /*
 211          * Configure FPGA register with PCIe reset
 212          */
 213         out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);    /* assert PCIe reset */
 214         mdelay(50);
 215         out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);    /* deassert PCIe reset */
 216
 217         return 0;
 218 }
 219
 220 int misc_init_r(void)
 221 {
 222 #ifdef CFG_ENV_IS_IN_FLASH
 223         /* Monitor protection ON by default */
 224         flash_protect(FLAG_PROTECT_SET,
 225                       -CFG_MONITOR_LEN,
 226                       0xffffffff,
 227                       &flash_info[0]);
 228 #endif
 229
 230         return 0;
 231 }
 232
 233 int board_emac_count(void)
 234 {
 235         u32 pvr = get_pvr();
 236
 237         /*
 238          * 405EXr only has one EMAC interface, 405EX has two
 239          */
 240         if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
 241                 return 1;
 242         else
 243                 return 2;
 244 }
 245
 246 static int board_pcie_count(void)
 247 {
 248         u32 pvr = get_pvr();
 249
 250         /*
 251          * 405EXr only has one EMAC interface, 405EX has two
 252          */
 253         if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
 254                 return 1;
 255         else
 256                 return 2;
 257 }
 258
 259 int checkboard (void)
 260 {
 261         char *s = getenv("serial#");
 262         u32 pvr = get_pvr();
 263
 264         if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
 265                 printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
 266         else
 267                 printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
 268
 269         if (s != NULL) {
 270                 puts(", serial# ");
 271                 puts(s);
 272         }
 273         putc('\n');
 274
 275         return (0);
 276 }
 277
 278 /*************************************************************************
 279  *  pci_pre_init
 280  *
 281  *  This routine is called just prior to registering the hose and gives
 282  *  the board the opportunity to check things. Returning a value of zero
 283  *  indicates that things are bad & PCI initialization should be aborted.
 284  *
 285  *      Different boards may wish to customize the pci controller structure
 286  *      (add regions, override default access routines, etc) or perform
 287  *      certain pre-initialization actions.
 288  *
 289  ************************************************************************/
 290 #if defined(CONFIG_PCI)
 291 int pci_pre_init(struct pci_controller * hose )
 292 {
 293         return 0;
 294 }
 295 #endif  /* defined(CONFIG_PCI) */
 296
 297 #ifdef CONFIG_PCI
 298 static struct pci_controller pcie_hose[2] = {{0},{0}};
 299
 300 void pcie_setup_hoses(int busno)
 301 {
 302         struct pci_controller *hose;
 303         int i, bus;
 304         int ret = 0;
 305         bus = busno;
 306         char *env;
 307         unsigned int delay;
 308
 309         for (i = 0; i < board_pcie_count(); i++) {
 310
 311                 if (is_end_point(i))
 312                         ret = ppc4xx_init_pcie_endport(i);
 313                 else
 314                         ret = ppc4xx_init_pcie_rootport(i);
 315                 if (ret) {
 316                         printf("PCIE%d: initialization as %s failed\n", i,
 317                                is_end_point(i) ? "endpoint" : "root-complex");
 318                         continue;
 319                 }
 320
 321                 hose = &pcie_hose[i];
 322                 hose->first_busno = bus;
 323                 hose->last_busno = bus;
 324                 hose->current_busno = bus;
 325
 326                 /* setup mem resource */
 327                 pci_set_region(hose->regions + 0,
 328                                CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 329                                CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 330                                CFG_PCIE_MEMSIZE,
 331                                PCI_REGION_MEM);
 332                 hose->region_count = 1;
 333                 pci_register_hose(hose);
 334
 335                 if (is_end_point(i)) {
 336                         ppc4xx_setup_pcie_endpoint(hose, i);
 337                         /*
 338                          * Reson for no scanning is endpoint can not generate
 339                          * upstream configuration accesses.
 340                          */
 341                 } else {
 342                         ppc4xx_setup_pcie_rootpoint(hose, i);
 343                         env = getenv ("pciscandelay");
 344                         if (env != NULL) {
 345                                 delay = simple_strtoul(env, NULL, 10);
 346                                 if (delay > 5)
 347                                         printf("Warning, expect noticable delay before "
 348                                                "PCIe scan due to 'pciscandelay' value!\n");
 349                                 mdelay(delay * 1000);
 350                         }
 351
 352                         /*
 353                          * Config access can only go down stream
 354                          */
 355                         hose->last_busno = pci_hose_scan(hose);
 356                         bus = hose->last_busno + 1;
 357                 }
 358         }
 359 }
 360 #endif
 361
 362 #if defined(CONFIG_POST)
 363 /*
 364  * Returns 1 if keys pressed to start the power-on long-running tests
 365  * Called from board_init_f().
 366  */
 367 int post_hotkeys_pressed(void)
 368 {
 369         return 0;       /* No hotkeys supported */
 370 }
 371 #endif /* CONFIG_POST */
 372
 373 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 374 void ft_board_setup(void *blob, bd_t *bd)
 375 {
 376         u32 val[4];
 377         int rc;
 378
 379         ft_cpu_setup(blob, bd);
 380
 381         /* Fixup NOR mapping */
 382         val[0] = 0;                             /* chip select number */
 383         val[1] = 0;                             /* always 0 */
 384         val[2] = gd->bd->bi_flashstart;
 385         val[3] = gd->bd->bi_flashsize;
 386         rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 387                                   val, sizeof(val), 1);
 388         if (rc)
 389                 printf("Unable to update property NOR mapping, err=%s\n",
 390                        fdt_strerror(rc));
 391 }
 392 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */