include/mpc86xx.h

   1 /*
   2  * Copyright 2006 Freescale Semiconductor.
   3  * Jeffrey Brown
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  */
   6
   7 #ifndef __MPC86xx_H__
   8 #define __MPC86xx_H__
   9
  10 #define EXC_OFF_SYS_RESET       0x0100  /* System reset offset */
  11 #define _START_OFFSET           EXC_OFF_SYS_RESET
  12
  13 /*
  14  * platform register addresses
  15  */
  16
  17 #define GUTS_SVR        (CFG_CCSRBAR + 0xE00A4)
  18 #define MCM_ABCR        (CFG_CCSRBAR + 0x01000)
  19 #define MCM_DBCR        (CFG_CCSRBAR + 0x01008)
  20
  21 /*
  22  * l2cr values.  Look in config_<BOARD>.h for the actual setup
  23  */
  24 #define l2cr             1017
  25
  26 #define L2CR_L2E         0x80000000 /* bit 0 - enable */
  27 #define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
  28 #define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
  29 #define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
  30 #define L2CR_L2DO        0x00010000 /* bit 15 - data-only mode */
  31 #define L2CR_REP         0x00001000 /* bit 19 - l2 replacement alg */
  32 #define L2CR_HWF         0x00000800 /* bit 20 - hardware flush */
  33 #define L2CR_L2IP        0x00000001 /* global invalidate in progress */
  34
  35 /*
  36  * BAT settings.  Look in config_<BOARD>.h for the actual setup
  37  */
  38
  39 #define BATU_BL_128K            0x00000000
  40 #define BATU_BL_256K            0x00000004
  41 #define BATU_BL_512K            0x0000000c
  42 #define BATU_BL_1M              0x0000001c
  43 #define BATU_BL_2M              0x0000003c
  44 #define BATU_BL_4M              0x0000007c
  45 #define BATU_BL_8M              0x000000fc
  46 #define BATU_BL_16M             0x000001fc
  47 #define BATU_BL_32M             0x000003fc
  48 #define BATU_BL_64M             0x000007fc
  49 #define BATU_BL_128M            0x00000ffc
  50 #define BATU_BL_256M            0x00001ffc
  51 #define BATU_BL_512M            0x00003ffc
  52 #define BATU_BL_1G              0x00007ffc
  53 #define BATU_BL_2G              0x0000fffc
  54 #define BATU_BL_4G              0x0001fffc
  55
  56 #define BATU_VS                 0x00000002
  57 #define BATU_VP                 0x00000001
  58 #define BATU_INVALID            0x00000000
  59
  60 #define BATL_WRITETHROUGH       0x00000040
  61 #define BATL_CACHEINHIBIT       0x00000020
  62 #define BATL_MEMCOHERENCE       0x00000010
  63 #define BATL_GUARDEDSTORAGE     0x00000008
  64 #define BATL_NO_ACCESS          0x00000000
  65
  66 #define BATL_PP_MSK             0x00000003
  67 #define BATL_PP_00              0x00000000 /* No access */
  68 #define BATL_PP_01              0x00000001 /* Read-only */
  69 #define BATL_PP_10              0x00000002 /* Read-write */
  70 #define BATL_PP_11              0x00000003
  71
  72 #define BATL_PP_NO_ACCESS       BATL_PP_00
  73 #define BATL_PP_RO              BATL_PP_01
  74 #define BATL_PP_RW              BATL_PP_10
  75
  76 #define HID0_XBSEN              0x00000100
  77 #define HID0_HIGH_BAT_EN        0x00800000
  78 #define HID0_XAEN               0x00020000
  79
  80 #ifndef __ASSEMBLY__
  81
  82 typedef struct {
  83         unsigned long freqProcessor;
  84         unsigned long freqSystemBus;
  85 } MPC86xx_SYS_INFO;
  86
  87 #define l1icache_enable icache_enable
  88
  89 void l2cache_enable(void);
  90 void l1dcache_enable(void);
  91
  92 static __inline__ unsigned long get_hid0 (void)
  93 {
  94         unsigned long hid0;
  95         asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
  96         return hid0;
  97 }
  98
  99 static __inline__ unsigned long get_hid1 (void)
 100 {
 101         unsigned long hid1;
 102         asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
 103         return hid1;
 104 }
 105
 106 static __inline__ void set_hid0 (unsigned long hid0)
 107 {
 108         asm volatile("mtspr 1008, %0" : : "r" (hid0));
 109 }
 110
 111 static __inline__ void set_hid1 (unsigned long hid1)
 112 {
 113         asm volatile("mtspr 1009, %0" : : "r" (hid1));
 114 }
 115
 116
 117 static __inline__ unsigned long get_l2cr (void)
 118 {
 119    unsigned long l2cr_val;
 120    asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
 121    return l2cr_val;
 122 }
 123
 124 #endif  /* _ASMLANGUAGE */
 125 #endif  /* __MPC86xx_H__ */