drivers/net/bfin_mac.h

   1 /*
   2  * bfin_mac.h - some defines/structures for the Blackfin on-chip MAC.
   3  *
   4  * Copyright (c) 2005-2008 Analog Device, Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __BFIN_MAC_H__
  10 #define __BFIN_MAC_H__
  11
  12 #define PHYADDR                 0x01
  13 #define NO_PHY_REGS             0x20
  14
  15 #define DEFAULT_PHY_PHYID1      0x0007
  16 #define DEFAULT_PHY_PHYID2      0xC0A3
  17 #define PHY_MODECTL             0x00
  18 #define PHY_MODESTAT            0x01
  19 #define PHY_PHYID1              0x02
  20 #define PHY_PHYID2              0x03
  21 #define PHY_ANAR                0x04
  22 #define PHY_ANLPAR              0x05
  23 #define PHY_ANER                0x06
  24
  25 #define PHY_RESET               0x8000
  26 #define PHY_ANEG_EN             0x1000
  27 #define PHY_DUPLEX              0x0100
  28 #define PHY_SPD_SET             0x2000
  29
  30 #define RECV_BUFSIZE            (0x614)
  31
  32 typedef volatile u32 reg32;
  33 typedef volatile u16 reg16;
  34
  35 typedef struct ADI_DMA_CONFIG_REG {
  36         u16 b_DMA_EN:1;         /* 0    Enabled                         */
  37         u16 b_WNR:1;            /* 1    Direction                       */
  38         u16 b_WDSIZE:2;         /* 2:3  Transfer word size              */
  39         u16 b_DMA2D:1;          /* 4    DMA mode                        */
  40         u16 b_RESTART:1;        /* 5    Retain FIFO                     */
  41         u16 b_DI_SEL:1;         /* 6    Data interrupt timing select    */
  42         u16 b_DI_EN:1;          /* 7    Data interrupt enabled          */
  43         u16 b_NDSIZE:4;         /* 8:11 Flex descriptor size            */
  44         u16 b_FLOW:3;           /* 12:14Flow                            */
  45 } ADI_DMA_CONFIG_REG;
  46
  47 typedef struct adi_ether_frame_buffer {
  48         u16 NoBytes;            /* the no. of following bytes   */
  49         u8 Dest[6];             /* destination MAC address      */
  50         u8 Srce[6];             /* source MAC address           */
  51         u16 LTfield;            /* length/type field            */
  52         u8 Data[0];             /* payload bytes                */
  53 } ADI_ETHER_FRAME_BUFFER;
  54 /* 16 bytes/struct      */
  55
  56 typedef struct dma_descriptor {
  57         struct dma_descriptor *NEXT_DESC_PTR;
  58         u32 START_ADDR;
  59         ADI_DMA_CONFIG_REG CONFIG;
  60 } DMA_DESCRIPTOR;
  61 /* 10 bytes/struct in 12 bytes */
  62
  63 typedef struct adi_ether_buffer {
  64         DMA_DESCRIPTOR Dma[2];          /* first for the frame, second for the status */
  65         ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
  66         struct adi_ether_buffer *pNext; /* next buffer */
  67         struct adi_ether_buffer *pPrev; /* prev buffer */
  68         u16 IPHdrChksum;                /* the IP header checksum */
  69         u16 IPPayloadChksum;            /* the IP header and payload checksum */
  70         volatile u32 StatusWord;        /* the frame status word */
  71 } ADI_ETHER_BUFFER;
  72 /* 40 bytes/struct in 44 bytes */
  73
  74 static ADI_ETHER_BUFFER *SetupRxBuffer(int no);
  75 static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
  76
  77 static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
  78 static void bfin_EMAC_halt(struct eth_device *dev);
  79 static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length);
  80 static int bfin_EMAC_recv(struct eth_device *dev);
  81
  82 static void PollMdcDone(void);
  83 static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
  84 static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
  85 static int SetupSystemRegs(int *opmode);
  86
  87 static void bfin_EMAC_setup_addr(bd_t *bd);
  88
  89 #endif