cpu/mpc86xx/cpu_init.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Jeff Brown
   4  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * cpu_init.c - low level cpu init
  27  */
  28
  29 #include <common.h>
  30 #include <mpc86xx.h>
  31 #include <asm/fsl_law.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 /*
  36  * Breathe some life into the CPU...
  37  *
  38  * Set up the memory map
  39  * initialize a bunch of registers
  40  */
  41
  42 void cpu_init_f(void)
  43 {
  44         volatile immap_t    *immap = (immap_t *)CFG_IMMR;
  45         volatile ccsr_lbc_t *memctl = &immap->im_lbc;
  46
  47         /* Pointer is writable since we allocated a register for it */
  48         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
  49
  50         /* Clear initial global data */
  51         memset ((void *) gd, 0, sizeof (gd_t));
  52
  53 #ifdef CONFIG_FSL_LAW
  54         init_laws();
  55 #endif
  56
  57         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
  58          * addresses - these have to be modified later when FLASH size
  59          * has been determined
  60          */
  61
  62 #if defined(CFG_OR0_REMAP)
  63         memctl->or0 = CFG_OR0_REMAP;
  64 #endif
  65 #if defined(CFG_OR1_REMAP)
  66         memctl->or1 = CFG_OR1_REMAP;
  67 #endif
  68
  69         /* now restrict to preliminary range */
  70 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
  71         memctl->br0 = CFG_BR0_PRELIM;
  72         memctl->or0 = CFG_OR0_PRELIM;
  73 #endif
  74
  75 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
  76         memctl->or1 = CFG_OR1_PRELIM;
  77         memctl->br1 = CFG_BR1_PRELIM;
  78 #endif
  79
  80 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
  81         memctl->or2 = CFG_OR2_PRELIM;
  82         memctl->br2 = CFG_BR2_PRELIM;
  83 #endif
  84
  85 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
  86         memctl->or3 = CFG_OR3_PRELIM;
  87         memctl->br3 = CFG_BR3_PRELIM;
  88 #endif
  89
  90 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
  91         memctl->or4 = CFG_OR4_PRELIM;
  92         memctl->br4 = CFG_BR4_PRELIM;
  93 #endif
  94
  95 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
  96         memctl->or5 = CFG_OR5_PRELIM;
  97         memctl->br5 = CFG_BR5_PRELIM;
  98 #endif
  99
 100 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
 101         memctl->or6 = CFG_OR6_PRELIM;
 102         memctl->br6 = CFG_BR6_PRELIM;
 103 #endif
 104
 105 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
 106         memctl->or7 = CFG_OR7_PRELIM;
 107         memctl->br7 = CFG_BR7_PRELIM;
 108 #endif
 109
 110         /* enable the timebase bit in HID0 */
 111         set_hid0(get_hid0() | 0x4000000);
 112
 113         /* enable EMCP, SYNCBE | ABE bits in HID1 */
 114         set_hid1(get_hid1() | 0x80000C00);
 115 }
 116
 117 /*
 118  * initialize higher level parts of CPU like timers
 119  */
 120 int cpu_init_r(void)
 121 {
 122 #ifdef CONFIG_FSL_LAW
 123         disable_law(0);
 124 #endif
 125         return 0;
 126 }