| blob | c1669dcb10bbbc9b1c73438e67cb07dbc5c174e1 |
1 /*
2 * mcf5329.h -- Definitions for Freescale Coldfire 5329
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
26 #ifndef mcf5329_h
27 #define mcf5329_h
28 /****************************************************************************/
30 /*********************************************************************
31 * System Control Module (SCM)
32 *********************************************************************/
33 /* Bit definitions and macros for SCM_MPR */
34 #define SCM_MPR_MPROT0(x) (((x)&0x0F)<<28)
35 #define SCM_MPR_MPROT1(x) (((x)&0x0F)<<24)
36 #define SCM_MPR_MPROT2(x) (((x)&0x0F)<<20)
37 #define SCM_MPR_MPROT4(x) (((x)&0x0F)<<12)
38 #define SCM_MPR_MPROT5(x) (((x)&0x0F)<<8)
39 #define SCM_MPR_MPROT6(x) (((x)&0x0F)<<4)
40 #define MPROT_MTR 4
41 #define MPROT_MTW 2
42 #define MPROT_MPL 1
44 /* Bit definitions and macros for SCM_BMT */
45 #define BMT_BME (0x08)
46 #define BMT_8 (0x07)
47 #define BMT_16 (0x06)
48 #define BMT_32 (0x05)
49 #define BMT_64 (0x04)
50 #define BMT_128 (0x03)
51 #define BMT_256 (0x02)
52 #define BMT_512 (0x01)
53 #define BMT_1024 (0x00)
55 /* Bit definitions and macros for SCM_PACRA */
56 #define SCM_PACRA_PACR0(x) (((x)&0x0F)<<28)
57 #define SCM_PACRA_PACR1(x) (((x)&0x0F)<<24)
58 #define SCM_PACRA_PACR2(x) (((x)&0x0F)<<20)
59 #define PACR_SP 4
60 #define PACR_WP 2
61 #define PACR_TP 1
63 /* Bit definitions and macros for SCM_PACRB */
64 #define SCM_PACRB_PACR8(x) (((x)&0x0F)<<28)
65 #define SCM_PACRB_PACR12(x) (((x)&0x0F)<<12)
67 /* Bit definitions and macros for SCM_PACRC */
68 #define SCM_PACRC_PACR16(x) (((x)&0x0F)<<28)
69 #define SCM_PACRC_PACR17(x) (((x)&0x0F)<<24)
70 #define SCM_PACRC_PACR18(x) (((x)&0x0F)<<20)
71 #define SCM_PACRC_PACR19(x) (((x)&0x0F)<<16)
72 #define SCM_PACRC_PACR21(x) (((x)&0x0F)<<8)
73 #define SCM_PACRC_PACR22(x) (((x)&0x0F)<<4)
74 #define SCM_PACRC_PACR23(x) (((x)&0x0F)<<0)
76 /* Bit definitions and macros for SCM_PACRD */
77 #define SCM_PACRD_PACR24(x) (((x)&0x0F)<<28)
78 #define SCM_PACRD_PACR25(x) (((x)&0x0F)<<24)
79 #define SCM_PACRD_PACR26(x) (((x)&0x0F)<<20)
80 #define SCM_PACRD_PACR28(x) (((x)&0x0F)<<12)
81 #define SCM_PACRD_PACR29(x) (((x)&0x0F)<<8)
82 #define SCM_PACRD_PACR30(x) (((x)&0x0F)<<4)
83 #define SCM_PACRD_PACR31(x) (((x)&0x0F)<<0)
85 /* Bit definitions and macros for SCM_PACRE */
86 #define SCM_PACRE_PACR32(x) (((x)&0x0F)<<28)
87 #define SCM_PACRE_PACR33(x) (((x)&0x0F)<<24)
88 #define SCM_PACRE_PACR34(x) (((x)&0x0F)<<20)
89 #define SCM_PACRE_PACR35(x) (((x)&0x0F)<<16)
90 #define SCM_PACRE_PACR36(x) (((x)&0x0F)<<12)
91 #define SCM_PACRE_PACR37(x) (((x)&0x0F)<<8)
92 #define SCM_PACRE_PACR38(x) (((x)&0x0F)<<4)
94 /* Bit definitions and macros for SCM_PACRF */
95 #define SCM_PACRF_PACR40(x) (((x)&0x0F)<<28)
96 #define SCM_PACRF_PACR41(x) (((x)&0x0F)<<24)
97 #define SCM_PACRF_PACR42(x) (((x)&0x0F)<<20)
98 #define SCM_PACRF_PACR43(x) (((x)&0x0F)<<16)
99 #define SCM_PACRF_PACR44(x) (((x)&0x0F)<<12)
100 #define SCM_PACRF_PACR45(x) (((x)&0x0F)<<8)
101 #define SCM_PACRF_PACR46(x) (((x)&0x0F)<<4)
102 #define SCM_PACRF_PACR47(x) (((x)&0x0F)<<0)
104 /* Bit definitions and macros for SCM_PACRG */
105 #define SCM_PACRG_PACR48(x) (((x)&0x0F)<<28)
107 /* Bit definitions and macros for SCM_PACRH */
108 #define SCM_PACRH_PACR56(x) (((x)&0x0F)<<28)
109 #define SCM_PACRH_PACR57(x) (((x)&0x0F)<<24)
110 #define SCM_PACRH_PACR58(x) (((x)&0x0F)<<20)
112 /* PACRn Assignments */
113 #define PACR0(x) SCM_PACRA_PACR0(x)
114 #define PACR1(x) SCM_PACRA_PACR1(x)
115 #define PACR2(x) SCM_PACRA_PACR2(x)
116 #define PACR8(x) SCM_PACRB_PACR8(x)
117 #define PACR12(x) SCM_PACRB_PACR12(x)
118 #define PACR16(x) SCM_PACRC_PACR16(x)
119 #define PACR17(x) SCM_PACRC_PACR17(x)
120 #define PACR18(x) SCM_PACRC_PACR18(x)
121 #define PACR19(x) SCM_PACRC_PACR19(x)
122 #define PACR21(x) SCM_PACRC_PACR21(x)
123 #define PACR22(x) SCM_PACRC_PACR22(x)
124 #define PACR23(x) SCM_PACRC_PACR23(x)
125 #define PACR24(x) SCM_PACRD_PACR24(x)
126 #define PACR25(x) SCM_PACRD_PACR25(x)
127 #define PACR26(x) SCM_PACRD_PACR26(x)
128 #define PACR28(x) SCM_PACRD_PACR28(x)
129 #define PACR29(x) SCM_PACRD_PACR29(x)
130 #define PACR30(x) SCM_PACRD_PACR30(x)
131 #define PACR31(x) SCM_PACRD_PACR31(x)
132 #define PACR32(x) SCM_PACRE_PACR32(x)
133 #define PACR33(x) SCM_PACRE_PACR33(x)
134 #define PACR34(x) SCM_PACRE_PACR34(x)
135 #define PACR35(x) SCM_PACRE_PACR35(x)
136 #define PACR36(x) SCM_PACRE_PACR36(x)
137 #define PACR37(x) SCM_PACRE_PACR37(x)
138 #define PACR38(x) SCM_PACRE_PACR38(x)
139 #define PACR40(x) SCM_PACRF_PACR40(x)
140 #define PACR41(x) SCM_PACRF_PACR41(x)
141 #define PACR42(x) SCM_PACRF_PACR42(x)
142 #define PACR43(x) SCM_PACRF_PACR43(x)
143 #define PACR44(x) SCM_PACRF_PACR44(x)
144 #define PACR45(x) SCM_PACRF_PACR45(x)
145 #define PACR46(x) SCM_PACRF_PACR46(x)
146 #define PACR47(x) SCM_PACRF_PACR47(x)
147 #define PACR48(x) SCM_PACRG_PACR48(x)
148 #define PACR56(x) SCM_PACRH_PACR56(x)
149 #define PACR57(x) SCM_PACRH_PACR57(x)
150 #define PACR58(x) SCM_PACRH_PACR58(x)
152 /* Bit definitions and macros for SCM_CWCR */
153 #define CWCR_RO (0x8000)
154 #define CWCR_CWR_WH (0x0100)
155 #define CWCR_CWE (0x0080)
156 #define CWRI_WINDOW (0x0060)
157 #define CWRI_RESET (0x0040)
158 #define CWRI_INT_RESET (0x0020)
159 #define CWRI_INT (0x0000)
160 #define CWCR_CWT(x) (((x)&0x001F))
162 /* Bit definitions and macros for SCM_ISR */
163 #define SCMISR_CFEI (0x02)
164 #define SCMISR_CWIC (0x01)
166 /* Bit definitions and macros for SCM_BCR */
167 #define BCR_GBR (0x00000200)
168 #define BCR_GBW (0x00000100)
169 #define BCR_S7 (0x00000080)
170 #define BCR_S6 (0x00000040)
171 #define BCR_S4 (0x00000010)
172 #define BCR_S1 (0x00000002)
174 /* Bit definitions and macros for SCM_CFIER */
175 #define CFIER_ECFEI (0x01)
177 /* Bit definitions and macros for SCM_CFLOC */
178 #define CFLOC_LOC (0x80)
180 /* Bit definitions and macros for SCM_CFATR */
181 #define CFATR_WRITE (0x80)
182 #define CFATR_SZ32 (0x20)
183 #define CFATR_SZ16 (0x10)
184 #define CFATR_SZ08 (0x00)
185 #define CFATR_CACHE (0x08)
186 #define CFATR_MODE (0x02)
187 #define CFATR_TYPE (0x01)
189 /*********************************************************************
190 * FlexBus Chip Selects (FBCS)
191 *********************************************************************/
192 /* Bit definitions and macros for FBCS_CSAR */
193 #define CSAR_BA(x) (((x)&0xFFFF)<<16)
195 /* Bit definitions and macros for FBCS_CSMR */
196 #define CSMR_BAM(x) (((x)&0xFFFF)<<16)
197 #define CSMR_BAM_4G (0xFFFF0000)
198 #define CSMR_BAM_2G (0x7FFF0000)
199 #define CSMR_BAM_1G (0x3FFF0000)
200 #define CSMR_BAM_1024M (0x3FFF0000)
201 #define CSMR_BAM_512M (0x1FFF0000)
202 #define CSMR_BAM_256M (0x0FFF0000)
203 #define CSMR_BAM_128M (0x07FF0000)
204 #define CSMR_BAM_64M (0x03FF0000)
205 #define CSMR_BAM_32M (0x01FF0000)
206 #define CSMR_BAM_16M (0x00FF0000)
207 #define CSMR_BAM_8M (0x007F0000)
208 #define CSMR_BAM_4M (0x003F0000)
209 #define CSMR_BAM_2M (0x001F0000)
210 #define CSMR_BAM_1M (0x000F0000)
211 #define CSMR_BAM_1024K (0x000F0000)
212 #define CSMR_BAM_512K (0x00070000)
213 #define CSMR_BAM_256K (0x00030000)
214 #define CSMR_BAM_128K (0x00010000)
215 #define CSMR_BAM_64K (0x00000000)
216 #define CSMR_WP (0x00000100)
217 #define CSMR_V (0x00000001)
219 /* Bit definitions and macros for FBCS_CSCR */
220 #define CSCR_SWS(x) (((x)&0x3F)<<26)
221 #define CSCR_ASET(x) (((x)&0x03)<<20)
222 #define CSCR_SWSEN (0x00800000)
223 #define CSCR_ASET_4CLK (0x00300000)
224 #define CSCR_ASET_3CLK (0x00200000)
225 #define CSCR_ASET_2CLK (0x00100000)
226 #define CSCR_ASET_1CLK (0x00000000)
227 #define CSCR_RDAH(x) (((x)&0x03)<<18)
228 #define CSCR_RDAH_4CYC (0x000C0000)
229 #define CSCR_RDAH_3CYC (0x00080000)
230 #define CSCR_RDAH_2CYC (0x00040000)
231 #define CSCR_RDAH_1CYC (0x00000000)
232 #define CSCR_WRAH(x) (((x)&0x03)<<16)
233 #define CSCR_WDAH_4CYC (0x00003000)
234 #define CSCR_WDAH_3CYC (0x00002000)
235 #define CSCR_WDAH_2CYC (0x00001000)
236 #define CSCR_WDAH_1CYC (0x00000000)
237 #define CSCR_WS(x) (((x)&0x3F)<<10)
238 #define CSCR_SBM (0x00000200)
239 #define CSCR_AA (0x00000100)
240 #define CSCR_PS_MASK (0x000000C0)
241 #define CSCR_PS_32 (0x00000000)
242 #define CSCR_PS_16 (0x00000080)
243 #define CSCR_PS_8 (0x00000040)
244 #define CSCR_BEM (0x00000020)
245 #define CSCR_BSTR (0x00000010)
246 #define CSCR_BSTW (0x00000008)
248 /*********************************************************************
249 * Reset Controller Module (RCM)
250 *********************************************************************/
252 /* Bit definitions and macros for RCR */
253 #define RCM_RCR_FRCRSTOUT (0x40)
254 #define RCM_RCR_SOFTRST (0x80)
256 /* Bit definitions and macros for RSR */
257 #define RCM_RSR_LOL (0x01)
258 #define RCM_RSR_WDR_CORE (0x02)
259 #define RCM_RSR_EXT (0x04)
260 #define RCM_RSR_POR (0x08)
261 #define RCM_RSR_SOFT (0x20)
263 /*********************************************************************
264 * FlexCAN Module (CAN)
265 *********************************************************************/
266 /* Bit definitions and macros for CAN_CANMCR */
267 #define CANMCR_MDIS (0x80000000)
268 #define CANMCR_FRZ (0x40000000)
269 #define CANMCR_HALT (0x10000000)
270 #define CANMCR_NORDY (0x08000000)
271 #define CANMCR_SOFTRST (0x02000000)
272 #define CANMCR_FRZACK (0x01000000)
273 #define CANMCR_SUPV (0x00800000)
274 #define CANMCR_LPMACK (0x00100000)
275 #define CANMCR_MAXMB(x) (((x)&0x0F))
277 /* Bit definitions and macros for CAN_CANCTRL */
278 #define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
279 #define CANCTRL_RJW(x) (((x)&0x03)<<22)
280 #define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
281 #define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
282 #define CANCTRL_BOFFMSK (0x00008000)
283 #define CANCTRL_ERRMSK (0x00004000)
284 #define CANCTRL_CLKSRC (0x00002000)
285 #define CANCTRL_LPB (0x00001000)
286 #define CANCTRL_SMP (0x00000080)
287 #define CANCTRL_BOFFREC (0x00000040)
288 #define CANCTRL_TSYNC (0x00000020)
289 #define CANCTRL_LBUF (0x00000010)
290 #define CANCTRL_LOM (0x00000008)
291 #define CANCTRL_PROPSEG(x) (((x)&0x07))
293 /* Bit definitions and macros for CAN_TIMER */
294 #define TIMER_TIMER(x) ((x)&0xFFFF)
296 /* Bit definitions and macros for CAN_RXGMASK */
297 #define RXGMASK_MI(x) ((x)&0x1FFFFFFF)
299 /* Bit definitions and macros for CAN_ERRCNT */
300 #define ERRCNT_TXECTR(x) (((x)&0xFF))
301 #define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
303 /* Bit definitions and macros for CAN_ERRSTAT */
304 #define ERRSTAT_BITERR1 (0x00008000)
305 #define ERRSTAT_BITERR0 (0x00004000)
306 #define ERRSTAT_ACKERR (0x00002000)
307 #define ERRSTAT_CRCERR (0x00001000)
308 #define ERRSTAT_FRMERR (0x00000800)
309 #define ERRSTAT_STFERR (0x00000400)
310 #define ERRSTAT_TXWRN (0x00000200)
311 #define ERRSTAT_RXWRN (0x00000100)
312 #define ERRSTAT_IDLE (0x00000080)
313 #define ERRSTAT_TXRX (0x00000040)
314 #define ERRSTAT_FLT_BUSOFF (0x00000020)
315 #define ERRSTAT_FLT_PASSIVE (0x00000010)
316 #define ERRSTAT_FLT_ACTIVE (0x00000000)
317 #define ERRSTAT_BOFFINT (0x00000004)
318 #define ERRSTAT_ERRINT (0x00000002)
319 #define ERRSTAT_WAKINT (0x00000001)
321 /* Bit definitions and macros for CAN_IMASK */
322 #define IMASK_BUF15M (0x00008000)
323 #define IMASK_BUF14M (0x00004000)
324 #define IMASK_BUF13M (0x00002000)
325 #define IMASK_BUF12M (0x00001000)
326 #define IMASK_BUF11M (0x00000800)
327 #define IMASK_BUF10M (0x00000400)
328 #define IMASK_BUF9M (0x00000200)
329 #define IMASK_BUF8M (0x00000100)
330 #define IMASK_BUF7M (0x00000080)
331 #define IMASK_BUF6M (0x00000040)
332 #define IMASK_BUF5M (0x00000020)
333 #define IMASK_BUF4M (0x00000010)
334 #define IMASK_BUF3M (0x00000008)
335 #define IMASK_BUF2M (0x00000004)
336 #define IMASK_BUF1M (0x00000002)
337 #define IMASK_BUF0M (0x00000001)
339 /* Bit definitions and macros for CAN_IFLAG */
340 #define IFLAG_BUF15I (0x00008000)
341 #define IFLAG_BUF14I (0x00004000)
342 #define IFLAG_BUF13I (0x00002000)
343 #define IFLAG_BUF12I (0x00001000)
344 #define IFLAG_BUF11I (0x00000800)
345 #define IFLAG_BUF10I (0x00000400)
346 #define IFLAG_BUF9I (0x00000200)
347 #define IFLAG_BUF8I (0x00000100)
348 #define IFLAG_BUF7I (0x00000080)
349 #define IFLAG_BUF6I (0x00000040)
350 #define IFLAG_BUF5I (0x00000020)
351 #define IFLAG_BUF4I (0x00000010)
352 #define IFLAG_BUF3I (0x00000008)
353 #define IFLAG_BUF2I (0x00000004)
354 #define IFLAG_BUF1I (0x00000002)
355 #define IFLAG_BUF0I (0x00000001)
357 /*********************************************************************
358 * Interrupt Controller (INTC)
359 *********************************************************************/
360 #define INTC0_EPORT INTC_IPRL_INT1
362 #define INT0_LO_RSVD0 (0)
363 #define INT0_LO_EPORT1 (1)
364 #define INT0_LO_EPORT2 (2)
365 #define INT0_LO_EPORT3 (3)
366 #define INT0_LO_EPORT4 (4)
367 #define INT0_LO_EPORT5 (5)
368 #define INT0_LO_EPORT6 (6)
369 #define INT0_LO_EPORT7 (7)
370 #define INT0_LO_EDMA_00 (8)
371 #define INT0_LO_EDMA_01 (9)
372 #define INT0_LO_EDMA_02 (10)
373 #define INT0_LO_EDMA_03 (11)
374 #define INT0_LO_EDMA_04 (12)
375 #define INT0_LO_EDMA_05 (13)
376 #define INT0_LO_EDMA_06 (14)
377 #define INT0_LO_EDMA_07 (15)
378 #define INT0_LO_EDMA_08 (16)
379 #define INT0_LO_EDMA_09 (17)
380 #define INT0_LO_EDMA_10 (18)
381 #define INT0_LO_EDMA_11 (19)
382 #define INT0_LO_EDMA_12 (20)
383 #define INT0_LO_EDMA_13 (21)
384 #define INT0_LO_EDMA_14 (22)
385 #define INT0_LO_EDMA_15 (23)
386 #define INT0_LO_EDMA_ERR (24)
387 #define INT0_LO_SCM (25)
388 #define INT0_LO_UART0 (26)
389 #define INT0_LO_UART1 (27)
390 #define INT0_LO_UART2 (28)
391 #define INT0_LO_RSVD1 (29)
392 #define INT0_LO_I2C (30)
393 #define INT0_LO_QSPI (31)
394 #define INT0_HI_DTMR0 (32)
395 #define INT0_HI_DTMR1 (33)
396 #define INT0_HI_DTMR2 (34)
397 #define INT0_HI_DTMR3 (35)
398 #define INT0_HI_FEC_TXF (36)
399 #define INT0_HI_FEC_TXB (37)
400 #define INT0_HI_FEC_UN (38)
401 #define INT0_HI_FEC_RL (39)
402 #define INT0_HI_FEC_RXF (40)
403 #define INT0_HI_FEC_RXB (41)
404 #define INT0_HI_FEC_MII (42)
405 #define INT0_HI_FEC_LC (43)
406 #define INT0_HI_FEC_HBERR (44)
407 #define INT0_HI_FEC_GRA (45)
408 #define INT0_HI_FEC_EBERR (46)
409 #define INT0_HI_FEC_BABT (47)
410 #define INT0_HI_FEC_BABR (48)
411 /* 49 - 61 Reserved */
412 #define INT0_HI_SCM (62)
414 /* Bit definitions and macros for INTC_IPRH */
415 #define INTC_IPRH_INT63 (0x80000000)
416 #define INTC_IPRH_INT62 (0x40000000)
417 #define INTC_IPRH_INT61 (0x20000000)
418 #define INTC_IPRH_INT60 (0x10000000)
419 #define INTC_IPRH_INT59 (0x08000000)
420 #define INTC_IPRH_INT58 (0x04000000)
421 #define INTC_IPRH_INT57 (0x02000000)
422 #define INTC_IPRH_INT56 (0x01000000)
423 #define INTC_IPRH_INT55 (0x00800000)
424 #define INTC_IPRH_INT54 (0x00400000)
425 #define INTC_IPRH_INT53 (0x00200000)
426 #define INTC_IPRH_INT52 (0x00100000)
427 #define INTC_IPRH_INT51 (0x00080000)
428 #define INTC_IPRH_INT50 (0x00040000)
429 #define INTC_IPRH_INT49 (0x00020000)
430 #define INTC_IPRH_INT48 (0x00010000)
431 #define INTC_IPRH_INT47 (0x00008000)
432 #define INTC_IPRH_INT46 (0x00004000)
433 #define INTC_IPRH_INT45 (0x00002000)
434 #define INTC_IPRH_INT44 (0x00001000)
435 #define INTC_IPRH_INT43 (0x00000800)
436 #define INTC_IPRH_INT42 (0x00000400)
437 #define INTC_IPRH_INT41 (0x00000200)
438 #define INTC_IPRH_INT40 (0x00000100)
439 #define INTC_IPRH_INT39 (0x00000080)
440 #define INTC_IPRH_INT38 (0x00000040)
441 #define INTC_IPRH_INT37 (0x00000020)
442 #define INTC_IPRH_INT36 (0x00000010)
443 #define INTC_IPRH_INT35 (0x00000008)
444 #define INTC_IPRH_INT34 (0x00000004)
445 #define INTC_IPRH_INT33 (0x00000002)
446 #define INTC_IPRH_INT32 (0x00000001)
448 /* Bit definitions and macros for INTC_IPRL */
449 #define INTC_IPRL_INT31 (0x80000000)
450 #define INTC_IPRL_INT30 (0x40000000)
451 #define INTC_IPRL_INT29 (0x20000000)
452 #define INTC_IPRL_INT28 (0x10000000)
453 #define INTC_IPRL_INT27 (0x08000000)
454 #define INTC_IPRL_INT26 (0x04000000)
455 #define INTC_IPRL_INT25 (0x02000000)
456 #define INTC_IPRL_INT24 (0x01000000)
457 #define INTC_IPRL_INT23 (0x00800000)
458 #define INTC_IPRL_INT22 (0x00400000)
459 #define INTC_IPRL_INT21 (0x00200000)
460 #define INTC_IPRL_INT20 (0x00100000)
461 #define INTC_IPRL_INT19 (0x00080000)
462 #define INTC_IPRL_INT18 (0x00040000)
463 #define INTC_IPRL_INT17 (0x00020000)
464 #define INTC_IPRL_INT16 (0x00010000)
465 #define INTC_IPRL_INT15 (0x00008000)
466 #define INTC_IPRL_INT14 (0x00004000)
467 #define INTC_IPRL_INT13 (0x00002000)
468 #define INTC_IPRL_INT12 (0x00001000)
469 #define INTC_IPRL_INT11 (0x00000800)
470 #define INTC_IPRL_INT10 (0x00000400)
471 #define INTC_IPRL_INT9 (0x00000200)
472 #define INTC_IPRL_INT8 (0x00000100)
473 #define INTC_IPRL_INT7 (0x00000080)
474 #define INTC_IPRL_INT6 (0x00000040)
475 #define INTC_IPRL_INT5 (0x00000020)
476 #define INTC_IPRL_INT4 (0x00000010)
477 #define INTC_IPRL_INT3 (0x00000008)
478 #define INTC_IPRL_INT2 (0x00000004)
479 #define INTC_IPRL_INT1 (0x00000002)
480 #define INTC_IPRL_INT0 (0x00000001)
482 /* Bit definitions and macros for INTC_ICONFIG */
483 #define INTC_ICFG_ELVLPRI7 (0x8000)
484 #define INTC_ICFG_ELVLPRI6 (0x4000)
485 #define INTC_ICFG_ELVLPRI5 (0x2000)
486 #define INTC_ICFG_ELVLPRI4 (0x1000)
487 #define INTC_ICFG_ELVLPRI3 (0x0800)
488 #define INTC_ICFG_ELVLPRI2 (0x0400)
489 #define INTC_ICFG_ELVLPRI1 (0x0200)
490 #define INTC_ICFG_EMASK (0x0020)
492 /* Bit definitions and macros for INTC_SIMR */
493 #define INTC_SIMR_SALL (0x40)
494 #define INTC_SIMR_SIMR(x) ((x)&0x3F)
496 /* Bit definitions and macros for INTC_CIMR */
497 #define INTC_CIMR_CALL (0x40)
498 #define INTC_CIMR_CIMR(x) ((x)&0x3F)
500 /* Bit definitions and macros for INTC_CLMASK */
501 #define INTC_CLMASK_CLMASK(x) ((x)&0x0F)
503 /* Bit definitions and macros for INTC_SLMASK */
504 #define INTC_SLMASK_SLMASK(x) ((x)&0x0F)
506 /* Bit definitions and macros for INTC_ICR */
507 #define INTC_ICR_IL(x) ((x)&0x07)
509 /*********************************************************************
510 * Queued Serial Peripheral Interface (QSPI)
511 *********************************************************************/
512 /* Bit definitions and macros for QSPI_QMR */
513 #define QSPI_QMR_MSTR (0x8000)
514 #define QSPI_QMR_DOHIE (0x4000)
515 #define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
516 #define QSPI_QMR_CPOL (0x0200)
517 #define QSPI_QMR_CPHA (0x0100)
518 #define QSPI_QMR_BAUD(x) ((x)&0x00FF)
520 /* Bit definitions and macros for QSPI_QDLYR */
521 #define QSPI_QDLYR_SPE (0x8000)
522 #define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
523 #define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
525 /* Bit definitions and macros for QSPI_QWR */
526 #define QSPI_QWR_NEWQP(x) ((x)&0x000F)
527 #define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
528 #define QSPI_QWR_CSIV (0x1000)
529 #define QSPI_QWR_WRTO (0x2000)
530 #define QSPI_QWR_WREN (0x4000)
531 #define QSPI_QWR_HALT (0x8000)
533 /* Bit definitions and macros for QSPI_QIR */
534 #define QSPI_QIR_WCEFB (0x8000)
535 #define QSPI_QIR_ABRTB (0x4000)
536 #define QSPI_QIR_ABRTL (0x1000)
537 #define QSPI_QIR_WCEFE (0x0800)
538 #define QSPI_QIR_ABRTE (0x0400)
539 #define QSPI_QIR_SPIFE (0x0100)
540 #define QSPI_QIR_WCEF (0x0008)
541 #define QSPI_QIR_ABRT (0x0004)
542 #define QSPI_QIR_SPIF (0x0001)
544 /* Bit definitions and macros for QSPI_QAR */
545 #define QSPI_QAR_ADDR(x) ((x)&0x003F)
546 #define QSPI_QAR_TRANS (0x0000)
547 #define QSPI_QAR_RECV (0x0010)
548 #define QSPI_QAR_CMD (0x0020)
550 /* Bit definitions and macros for QSPI_QDR */
551 #define QSPI_QDR_CONT (0x8000)
552 #define QSPI_QDR_BITSE (0x4000)
553 #define QSPI_QDR_DT (0x2000)
554 #define QSPI_QDR_DSCK (0x1000)
555 #define QSPI_QDR_QSPI_CS3 (0x0800)
556 #define QSPI_QDR_QSPI_CS2 (0x0400)
557 #define QSPI_QDR_QSPI_CS1 (0x0200)
558 #define QSPI_QDR_QSPI_CS0 (0x0100)
560 /*********************************************************************
561 * Pulse Width Modulation (PWM)
562 *********************************************************************/
563 /* Bit definitions and macros for PWM_E */
564 #define PWM_EN_PWME7 (0x80)
565 #define PWM_EN_PWME5 (0x20)
566 #define PWM_EN_PWME3 (0x08)
567 #define PWM_EN_PWME1 (0x02)
569 /* Bit definitions and macros for PWM_POL */
570 #define PWM_POL_PPOL7 (0x80)
571 #define PWM_POL_PPOL5 (0x20)
572 #define PWM_POL_PPOL3 (0x08)
573 #define PWM_POL_PPOL1 (0x02)
575 /* Bit definitions and macros for PWM_CLK */
576 #define PWM_CLK_PCLK7 (0x80)
577 #define PWM_CLK_PCLK5 (0x20)
578 #define PWM_CLK_PCLK3 (0x08)
579 #define PWM_CLK_PCLK1 (0x02)
581 /* Bit definitions and macros for PWM_PRCLK */
582 #define PWM_PRCLK_PCKB(x) (((x)&0x07)<<4)
583 #define PWM_PRCLK_PCKA(x) ((x)&0x07)
585 /* Bit definitions and macros for PWM_CAE */
586 #define PWM_CAE_CAE7 (0x80)
587 #define PWM_CAE_CAE5 (0x20)
588 #define PWM_CAE_CAE3 (0x08)
589 #define PWM_CAE_CAE1 (0x02)
591 /* Bit definitions and macros for PWM_CTL */
592 #define PWM_CTL_CON67 (0x80)
593 #define PWM_CTL_CON45 (0x40)
594 #define PWM_CTL_CON23 (0x20)
595 #define PWM_CTL_CON01 (0x10)
596 #define PWM_CTL_PSWAR (0x08)
597 #define PWM_CTL_PFRZ (0x04)
599 /* Bit definitions and macros for PWM_SDN */
600 #define PWM_SDN_IF (0x80)
601 #define PWM_SDN_IE (0x40)
602 #define PWM_SDN_RESTART (0x20)
603 #define PWM_SDN_LVL (0x10)
604 #define PWM_SDN_PWM7IN (0x04)
605 #define PWM_SDN_PWM7IL (0x02)
606 #define PWM_SDN_SDNEN (0x01)
608 /*********************************************************************
609 * Watchdog Timer Modules (WTM)
610 *********************************************************************/
611 /* Bit definitions and macros for WTM_WCR */
612 #define WTM_WCR_WAIT (0x0008)
613 #define WTM_WCR_DOZE (0x0004)
614 #define WTM_WCR_HALTED (0x0002)
615 #define WTM_WCR_EN (0x0001)
617 /*********************************************************************
618 * Chip Configuration Module (CCM)
619 *********************************************************************/
620 /* Bit definitions and macros for CCM_CCR */
621 #define CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001)
622 #define CCM_CCR_LIMP (0x0041)
623 #define CCM_CCR_LOAD (0x0021)
624 #define CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
625 #define CCM_CCR_OSC_MODE (0x0005)
626 #define CCM_CCR_PLL_MODE (0x0003)
627 #define CCM_CCR_RESERVED (0x0001)
629 /* Bit definitions and macros for CCM_RCON */
630 #define CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001)
631 #define CCM_RCON_LIMP (0x0041)
632 #define CCM_RCON_LOAD (0x0021)
633 #define CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001)
634 #define CCM_RCON_OSC_MODE (0x0005)
635 #define CCM_RCON_PLL_MODE (0x0003)
636 #define CCM_RCON_RESERVED (0x0001)
638 /* Bit definitions and macros for CCM_CIR */
639 #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6)
640 #define CCM_CIR_PRN(x) ((x)&0x003F)
642 /* Bit definitions and macros for CCM_MISCCR */
643 #define CCM_MISCCR_PLL_LOCK (0x2000)
644 #define CCM_MISCCR_LIMP (0x1000)
645 #define CCM_MISCCR_LCD_CHEN (0x0100)
646 #define CCM_MISCCR_SSI_PUE (0x0080)
647 #define CCM_MISCCR_SSI_PUS (0x0040)
648 #define CCM_MISCCR_TIM_DMA (0x0020)
649 #define CCM_MISCCR_SSI_SRC (0x0010)
650 #define CCM_MISCCR_USBDIV (0x0002)
651 #define CCM_MISCCR_USBSRC (0x0001)
653 /* Bit definitions and macros for CCM_CDR */
654 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8)
655 #define CCM_CDR_SSIDIV(x) ((x)&0x000F)
657 /* Bit definitions and macros for CCM_UHCSR */
658 #define CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14)
659 #define CCM_UHCSR_WKUP (0x0004)
660 #define CCM_UHCSR_UHMIE (0x0002)
661 #define CCM_UHCSR_XPDE (0x0001)
663 /* Bit definitions and macros for CCM_UOCSR */
664 #define CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14)
665 #define CCM_UOCSR_DPPD (0x2000)
666 #define CCM_UOCSR_DMPD (0x1000)
667 #define CCM_UOCSR_DRV_VBUS (0x0800)
668 #define CCM_UOCSR_CRG_VBUS (0x0400)
669 #define CCM_UOCSR_DCR_VBUS (0x0200)
670 #define CCM_UOCSR_DPPU (0x0100)
671 #define CCM_UOCSR_AVLD (0x0080)
672 #define CCM_UOCSR_BVLD (0x0040)
673 #define CCM_UOCSR_VVLD (0x0020)
674 #define CCM_UOCSR_SEND (0x0010)
675 #define CCM_UOCSR_PWRFLT (0x0008)
676 #define CCM_UOCSR_WKUP (0x0004)
677 #define CCM_UOCSR_UOMIE (0x0002)
678 #define CCM_UOCSR_XPDE (0x0001)
680 /* not done yet */
681 /*********************************************************************
682 * General Purpose I/O (GPIO)
683 *********************************************************************/
684 /* Bit definitions and macros for GPIO_PODR_FECH_L */
685 #define GPIO_PODR_FECH_L7 (0x80)
686 #define GPIO_PODR_FECH_L6 (0x40)
687 #define GPIO_PODR_FECH_L5 (0x20)
688 #define GPIO_PODR_FECH_L4 (0x10)
689 #define GPIO_PODR_FECH_L3 (0x08)
690 #define GPIO_PODR_FECH_L2 (0x04)
691 #define GPIO_PODR_FECH_L1 (0x02)
692 #define GPIO_PODR_FECH_L0 (0x01)
694 /* Bit definitions and macros for GPIO_PODR_SSI */
695 #define GPIO_PODR_SSI_4 (0x10)
696 #define GPIO_PODR_SSI_3 (0x08)
697 #define GPIO_PODR_SSI_2 (0x04)
698 #define GPIO_PODR_SSI_1 (0x02)
699 #define GPIO_PODR_SSI_0 (0x01)
701 /* Bit definitions and macros for GPIO_PODR_BUSCTL */
702 #define GPIO_PODR_BUSCTL_3 (0x08)
703 #define GPIO_PODR_BUSCTL_2 (0x04)
704 #define GPIO_PODR_BUSCTL_1 (0x02)
705 #define GPIO_PODR_BUSCTL_0 (0x01)
707 /* Bit definitions and macros for GPIO_PODR_BE */
708 #define GPIO_PODR_BE_3 (0x08)
709 #define GPIO_PODR_BE_2 (0x04)
710 #define GPIO_PODR_BE_1 (0x02)
711 #define GPIO_PODR_BE_0 (0x01)
713 /* Bit definitions and macros for GPIO_PODR_CS */
714 #define GPIO_PODR_CS_5 (0x20)
715 #define GPIO_PODR_CS_4 (0x10)
716 #define GPIO_PODR_CS_3 (0x08)
717 #define GPIO_PODR_CS_2 (0x04)
718 #define GPIO_PODR_CS_1 (0x02)
720 /* Bit definitions and macros for GPIO_PODR_PWM */
721 #define GPIO_PODR_PWM_5 (0x20)
722 #define GPIO_PODR_PWM_4 (0x10)
723 #define GPIO_PODR_PWM_3 (0x08)
724 #define GPIO_PODR_PWM_2 (0x04)
726 /* Bit definitions and macros for GPIO_PODR_FECI2C */
727 #define GPIO_PODR_FECI2C_3 (0x08)
728 #define GPIO_PODR_FECI2C_2 (0x04)
729 #define GPIO_PODR_FECI2C_1 (0x02)
730 #define GPIO_PODR_FECI2C_0 (0x01)
732 /* Bit definitions and macros for GPIO_PODR_UART */
733 #define GPIO_PODR_UART_7 (0x80)
734 #define GPIO_PODR_UART_6 (0x40)
735 #define GPIO_PODR_UART_5 (0x20)
736 #define GPIO_PODR_UART_4 (0x10)
737 #define GPIO_PODR_UART_3 (0x08)
738 #define GPIO_PODR_UART_2 (0x04)
739 #define GPIO_PODR_UART_1 (0x02)
740 #define GPIO_PODR_UART_0 (0x01)
742 /* Bit definitions and macros for GPIO_PODR_QSPI */
743 #define GPIO_PODR_QSPI_5 (0x20)
744 #define GPIO_PODR_QSPI_4 (0x10)
745 #define GPIO_PODR_QSPI_3 (0x08)
746 #define GPIO_PODR_QSPI_2 (0x04)
747 #define GPIO_PODR_QSPI_1 (0x02)
748 #define GPIO_PODR_QSPI_0 (0x01)
750 /* Bit definitions and macros for GPIO_PODR_TIMER */
751 #define GPIO_PODR_TIMER_3 (0x08)
752 #define GPIO_PODR_TIMER_2 (0x04)
753 #define GPIO_PODR_TIMER_1 (0x02)
754 #define GPIO_PODR_TIMER_0 (0x01)
756 /* Bit definitions and macros for GPIO_PODR_LCDDATAH */
757 #define GPIO_PODR_LCDDATAH_1 (0x02)
758 #define GPIO_PODR_LCDDATAH_0 (0x01)
760 /* Bit definitions and macros for GPIO_PODR_LCDDATAM */
761 #define GPIO_PODR_LCDDATAM_7 (0x80)
762 #define GPIO_PODR_LCDDATAM_6 (0x40)
763 #define GPIO_PODR_LCDDATAM_5 (0x20)
764 #define GPIO_PODR_LCDDATAM_4 (0x10)
765 #define GPIO_PODR_LCDDATAM_3 (0x08)
766 #define GPIO_PODR_LCDDATAM_2 (0x04)
767 #define GPIO_PODR_LCDDATAM_1 (0x02)
768 #define GPIO_PODR_LCDDATAM_0 (0x01)
770 /* Bit definitions and macros for GPIO_PODR_LCDDATAL */
771 #define GPIO_PODR_LCDDATAL_7 (0x80)
772 #define GPIO_PODR_LCDDATAL_6 (0x40)
773 #define GPIO_PODR_LCDDATAL_5 (0x20)
774 #define GPIO_PODR_LCDDATAL_4 (0x10)
775 #define GPIO_PODR_LCDDATAL_3 (0x08)
776 #define GPIO_PODR_LCDDATAL_2 (0x04)
777 #define GPIO_PODR_LCDDATAL_1 (0x02)
778 #define GPIO_PODR_LCDDATAL_0 (0x01)
780 /* Bit definitions and macros for GPIO_PODR_LCDCTLH */
781 #define GPIO_PODR_LCDCTLH_0 (0x01)
783 /* Bit definitions and macros for GPIO_PODR_LCDCTLL */
784 #define GPIO_PODR_LCDCTLL_7 (0x80)
785 #define GPIO_PODR_LCDCTLL_6 (0x40)
786 #define GPIO_PODR_LCDCTLL_5 (0x20)
787 #define GPIO_PODR_LCDCTLL_4 (0x10)
788 #define GPIO_PODR_LCDCTLL_3 (0x08)
789 #define GPIO_PODR_LCDCTLL_2 (0x04)
790 #define GPIO_PODR_LCDCTLL_1 (0x02)
791 #define GPIO_PODR_LCDCTLL_0 (0x01)
793 /* Bit definitions and macros for GPIO_PDDR_FECH */
794 #define GPIO_PDDR_FECH_L7 (0x80)
795 #define GPIO_PDDR_FECH_L6 (0x40)
796 #define GPIO_PDDR_FECH_L5 (0x20)
797 #define GPIO_PDDR_FECH_L4 (0x10)
798 #define GPIO_PDDR_FECH_L3 (0x08)
799 #define GPIO_PDDR_FECH_L2 (0x04)
800 #define GPIO_PDDR_FECH_L1 (0x02)
801 #define GPIO_PDDR_FECH_L0 (0x01)
803 /* Bit definitions and macros for GPIO_PDDR_SSI */
804 #define GPIO_PDDR_SSI_4 (0x10)
805 #define GPIO_PDDR_SSI_3 (0x08)
806 #define GPIO_PDDR_SSI_2 (0x04)
807 #define GPIO_PDDR_SSI_1 (0x02)
808 #define GPIO_PDDR_SSI_0 (0x01)
810 /* Bit definitions and macros for GPIO_PDDR_BUSCTL */
811 #define GPIO_PDDR_BUSCTL_3 (0x08)
812 #define GPIO_PDDR_BUSCTL_2 (0x04)
813 #define GPIO_PDDR_BUSCTL_1 (0x02)
814 #define GPIO_PDDR_BUSCTL_0 (0x01)
816 /* Bit definitions and macros for GPIO_PDDR_BE */
817 #define GPIO_PDDR_BE_3 (0x08)
818 #define GPIO_PDDR_BE_2 (0x04)
819 #define GPIO_PDDR_BE_1 (0x02)
820 #define GPIO_PDDR_BE_0 (0x01)
822 /* Bit definitions and macros for GPIO_PDDR_CS */
823 #define GPIO_PDDR_CS_1 (0x02)
824 #define GPIO_PDDR_CS_2 (0x04)
825 #define GPIO_PDDR_CS_3 (0x08)
826 #define GPIO_PDDR_CS_4 (0x10)
827 #define GPIO_PDDR_CS_5 (0x20)
829 /* Bit definitions and macros for GPIO_PDDR_PWM */
830 #define GPIO_PDDR_PWM_2 (0x04)
831 #define GPIO_PDDR_PWM_3 (0x08)
832 #define GPIO_PDDR_PWM_4 (0x10)
833 #define GPIO_PDDR_PWM_5 (0x20)
835 /* Bit definitions and macros for GPIO_PDDR_FECI2C */
836 #define GPIO_PDDR_FECI2C_0 (0x01)
837 #define GPIO_PDDR_FECI2C_1 (0x02)
838 #define GPIO_PDDR_FECI2C_2 (0x04)
839 #define GPIO_PDDR_FECI2C_3 (0x08)
841 /* Bit definitions and macros for GPIO_PDDR_UART */
842 #define GPIO_PDDR_UART_0 (0x01)
843 #define GPIO_PDDR_UART_1 (0x02)
844 #define GPIO_PDDR_UART_2 (0x04)
845 #define GPIO_PDDR_UART_3 (0x08)
846 #define GPIO_PDDR_UART_4 (0x10)
847 #define GPIO_PDDR_UART_5 (0x20)
848 #define GPIO_PDDR_UART_6 (0x40)
849 #define GPIO_PDDR_UART_7 (0x80)
851 /* Bit definitions and macros for GPIO_PDDR_QSPI */
852 #define GPIO_PDDR_QSPI_0 (0x01)
853 #define GPIO_PDDR_QSPI_1 (0x02)
854 #define GPIO_PDDR_QSPI_2 (0x04)
855 #define GPIO_PDDR_QSPI_3 (0x08)
856 #define GPIO_PDDR_QSPI_4 (0x10)
857 #define GPIO_PDDR_QSPI_5 (0x20)
859 /* Bit definitions and macros for GPIO_PDDR_TIMER */
860 #define GPIO_PDDR_TIMER_0 (0x01)
861 #define GPIO_PDDR_TIMER_1 (0x02)
862 #define GPIO_PDDR_TIMER_2 (0x04)
863 #define GPIO_PDDR_TIMER_3 (0x08)
865 /* Bit definitions and macros for GPIO_PDDR_LCDDATAH */
866 #define GPIO_PDDR_LCDDATAH_0 (0x01)
867 #define GPIO_PDDR_LCDDATAH_1 (0x02)
869 /* Bit definitions and macros for GPIO_PDDR_LCDDATAM */
870 #define GPIO_PDDR_LCDDATAM_0 (0x01)
871 #define GPIO_PDDR_LCDDATAM_1 (0x02)
872 #define GPIO_PDDR_LCDDATAM_2 (0x04)
873 #define GPIO_PDDR_LCDDATAM_3 (0x08)
874 #define GPIO_PDDR_LCDDATAM_4 (0x10)
875 #define GPIO_PDDR_LCDDATAM_5 (0x20)
876 #define GPIO_PDDR_LCDDATAM_6 (0x40)
877 #define GPIO_PDDR_LCDDATAM_7 (0x80)
879 /* Bit definitions and macros for GPIO_PDDR_LCDDATAL */
880 #define GPIO_PDDR_LCDDATAL_0 (0x01)
881 #define GPIO_PDDR_LCDDATAL_1 (0x02)
882 #define GPIO_PDDR_LCDDATAL_2 (0x04)
883 #define GPIO_PDDR_LCDDATAL_3 (0x08)
884 #define GPIO_PDDR_LCDDATAL_4 (0x10)
885 #define GPIO_PDDR_LCDDATAL_5 (0x20)
886 #define GPIO_PDDR_LCDDATAL_6 (0x40)
887 #define GPIO_PDDR_LCDDATAL_7 (0x80)
889 /* Bit definitions and macros for GPIO_PDDR_LCDCTLH */
890 #define GPIO_PDDR_LCDCTLH_0 (0x01)
892 /* Bit definitions and macros for GPIO_PDDR_LCDCTLL */
893 #define GPIO_PDDR_LCDCTLL_0 (0x01)
894 #define GPIO_PDDR_LCDCTLL_1 (0x02)
895 #define GPIO_PDDR_LCDCTLL_2 (0x04)
896 #define GPIO_PDDR_LCDCTLL_3 (0x08)
897 #define GPIO_PDDR_LCDCTLL_4 (0x10)
898 #define GPIO_PDDR_LCDCTLL_5 (0x20)
899 #define GPIO_PDDR_LCDCTLL_6 (0x40)
900 #define GPIO_PDDR_LCDCTLL_7 (0x80)
902 /* Bit definitions and macros for GPIO_PPDSDR_FECH */
903 #define GPIO_PPDSDR_FECH_L0 (0x01)
904 #define GPIO_PPDSDR_FECH_L1 (0x02)
905 #define GPIO_PPDSDR_FECH_L2 (0x04)
906 #define GPIO_PPDSDR_FECH_L3 (0x08)
907 #define GPIO_PPDSDR_FECH_L4 (0x10)
908 #define GPIO_PPDSDR_FECH_L5 (0x20)
909 #define GPIO_PPDSDR_FECH_L6 (0x40)
910 #define GPIO_PPDSDR_FECH_L7 (0x80)
912 /* Bit definitions and macros for GPIO_PPDSDR_SSI */
913 #define GPIO_PPDSDR_SSI_0 (0x01)
914 #define GPIO_PPDSDR_SSI_1 (0x02)
915 #define GPIO_PPDSDR_SSI_2 (0x04)
916 #define GPIO_PPDSDR_SSI_3 (0x08)
917 #define GPIO_PPDSDR_SSI_4 (0x10)
919 /* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */
920 #define GPIO_PPDSDR_BUSCTL_0 (0x01)
921 #define GPIO_PPDSDR_BUSCTL_1 (0x02)
922 #define GPIO_PPDSDR_BUSCTL_2 (0x04)
923 #define GPIO_PPDSDR_BUSCTL_3 (0x08)
925 /* Bit definitions and macros for GPIO_PPDSDR_BE */
926 #define GPIO_PPDSDR_BE_0 (0x01)
927 #define GPIO_PPDSDR_BE_1 (0x02)
928 #define GPIO_PPDSDR_BE_2 (0x04)
929 #define GPIO_PPDSDR_BE_3 (0x08)
931 /* Bit definitions and macros for GPIO_PPDSDR_CS */
932 #define GPIO_PPDSDR_CS_1 (0x02)
933 #define GPIO_PPDSDR_CS_2 (0x04)
934 #define GPIO_PPDSDR_CS_3 (0x08)
935 #define GPIO_PPDSDR_CS_4 (0x10)
936 #define GPIO_PPDSDR_CS_5 (0x20)
938 /* Bit definitions and macros for GPIO_PPDSDR_PWM */
939 #define GPIO_PPDSDR_PWM_2 (0x04)
940 #define GPIO_PPDSDR_PWM_3 (0x08)
941 #define GPIO_PPDSDR_PWM_4 (0x10)
942 #define GPIO_PPDSDR_PWM_5 (0x20)
944 /* Bit definitions and macros for GPIO_PPDSDR_FECI2C */
945 #define GPIO_PPDSDR_FECI2C_0 (0x01)
946 #define GPIO_PPDSDR_FECI2C_1 (0x02)
947 #define GPIO_PPDSDR_FECI2C_2 (0x04)
948 #define GPIO_PPDSDR_FECI2C_3 (0x08)
950 /* Bit definitions and macros for GPIO_PPDSDR_UART */
951 #define GPIO_PPDSDR_UART_0 (0x01)
952 #define GPIO_PPDSDR_UART_1 (0x02)
953 #define GPIO_PPDSDR_UART_2 (0x04)
954 #define GPIO_PPDSDR_UART_3 (0x08)
955 #define GPIO_PPDSDR_UART_4 (0x10)
956 #define GPIO_PPDSDR_UART_5 (0x20)
957 #define GPIO_PPDSDR_UART_6 (0x40)
958 #define GPIO_PPDSDR_UART_7 (0x80)
960 /* Bit definitions and macros for GPIO_PPDSDR_QSPI */
961 #define GPIO_PPDSDR_QSPI_0 (0x01)
962 #define GPIO_PPDSDR_QSPI_1 (0x02)
963 #define GPIO_PPDSDR_QSPI_2 (0x04)
964 #define GPIO_PPDSDR_QSPI_3 (0x08)
965 #define GPIO_PPDSDR_QSPI_4 (0x10)
966 #define GPIO_PPDSDR_QSPI_5 (0x20)
968 /* Bit definitions and macros for GPIO_PPDSDR_TIMER */
969 #define GPIO_PPDSDR_TIMER_0 (0x01)
970 #define GPIO_PPDSDR_TIMER_1 (0x02)
971 #define GPIO_PPDSDR_TIMER_2 (0x04)
972 #define GPIO_PPDSDR_TIMER_3 (0x08)
974 /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */
975 #define GPIO_PPDSDR_LCDDATAH_0 (0x01)
976 #define GPIO_PPDSDR_LCDDATAH_1 (0x02)
978 /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */
979 #define GPIO_PPDSDR_LCDDATAM_0 (0x01)
980 #define GPIO_PPDSDR_LCDDATAM_1 (0x02)
981 #define GPIO_PPDSDR_LCDDATAM_2 (0x04)
982 #define GPIO_PPDSDR_LCDDATAM_3 (0x08)
983 #define GPIO_PPDSDR_LCDDATAM_4 (0x10)
984 #define GPIO_PPDSDR_LCDDATAM_5 (0x20)
985 #define GPIO_PPDSDR_LCDDATAM_6 (0x40)
986 #define GPIO_PPDSDR_LCDDATAM_7 (0x80)
988 /* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */
989 #define GPIO_PPDSDR_LCDDATAL_0 (0x01)
990 #define GPIO_PPDSDR_LCDDATAL_1 (0x02)
991 #define GPIO_PPDSDR_LCDDATAL_2 (0x04)
992 #define GPIO_PPDSDR_LCDDATAL_3 (0x08)
993 #define GPIO_PPDSDR_LCDDATAL_4 (0x10)
994 #define GPIO_PPDSDR_LCDDATAL_5 (0x20)
995 #define GPIO_PPDSDR_LCDDATAL_6 (0x40)
996 #define GPIO_PPDSDR_LCDDATAL_7 (0x80)
998 /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */
999 #define GPIO_PPDSDR_LCDCTLH_0 (0x01)
1001 /* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */
1002 #define GPIO_PPDSDR_LCDCTLL_0 (0x01)
1003 #define GPIO_PPDSDR_LCDCTLL_1 (0x02)
1004 #define GPIO_PPDSDR_LCDCTLL_2 (0x04)
1005 #define GPIO_PPDSDR_LCDCTLL_3 (0x08)
1006 #define GPIO_PPDSDR_LCDCTLL_4 (0x10)
1007 #define GPIO_PPDSDR_LCDCTLL_5 (0x20)
1008 #define GPIO_PPDSDR_LCDCTLL_6 (0x40)
1009 #define GPIO_PPDSDR_LCDCTLL_7 (0x80)
1011 /* Bit definitions and macros for GPIO_PCLRR_FECH */
1012 #define GPIO_PCLRR_FECH_L0 (0x01)
1013 #define GPIO_PCLRR_FECH_L1 (0x02)
1014 #define GPIO_PCLRR_FECH_L2 (0x04)
1015 #define GPIO_PCLRR_FECH_L3 (0x08)
1016 #define GPIO_PCLRR_FECH_L4 (0x10)
1017 #define GPIO_PCLRR_FECH_L5 (0x20)
1018 #define GPIO_PCLRR_FECH_L6 (0x40)
1019 #define GPIO_PCLRR_FECH_L7 (0x80)
1021 /* Bit definitions and macros for GPIO_PCLRR_SSI */
1022 #define GPIO_PCLRR_SSI_0 (0x01)
1023 #define GPIO_PCLRR_SSI_1 (0x02)
1024 #define GPIO_PCLRR_SSI_2 (0x04)
1025 #define GPIO_PCLRR_SSI_3 (0x08)
1026 #define GPIO_PCLRR_SSI_4 (0x10)
1028 /* Bit definitions and macros for GPIO_PCLRR_BUSCTL */
1029 #define GPIO_PCLRR_BUSCTL_L0 (0x01)
1030 #define GPIO_PCLRR_BUSCTL_L1 (0x02)
1031 #define GPIO_PCLRR_BUSCTL_L2 (0x04)
1032 #define GPIO_PCLRR_BUSCTL_L3 (0x08)
1034 /* Bit definitions and macros for GPIO_PCLRR_BE */
1035 #define GPIO_PCLRR_BE_0 (0x01)
1036 #define GPIO_PCLRR_BE_1 (0x02)
1037 #define GPIO_PCLRR_BE_2 (0x04)
1038 #define GPIO_PCLRR_BE_3 (0x08)
1040 /* Bit definitions and macros for GPIO_PCLRR_CS */
1041 #define GPIO_PCLRR_CS_1 (0x02)
1042 #define GPIO_PCLRR_CS_2 (0x04)
1043 #define GPIO_PCLRR_CS_3 (0x08)
1044 #define GPIO_PCLRR_CS_4 (0x10)
1045 #define GPIO_PCLRR_CS_5 (0x20)
1047 /* Bit definitions and macros for GPIO_PCLRR_PWM */
1048 #define GPIO_PCLRR_PWM_2 (0x04)
1049 #define GPIO_PCLRR_PWM_3 (0x08)
1050 #define GPIO_PCLRR_PWM_4 (0x10)
1051 #define GPIO_PCLRR_PWM_5 (0x20)
1053 /* Bit definitions and macros for GPIO_PCLRR_FECI2C */
1054 #define GPIO_PCLRR_FECI2C_0 (0x01)
1055 #define GPIO_PCLRR_FECI2C_1 (0x02)
1056 #define GPIO_PCLRR_FECI2C_2 (0x04)
1057 #define GPIO_PCLRR_FECI2C_3 (0x08)
1059 /* Bit definitions and macros for GPIO_PCLRR_UART */
1060 #define GPIO_PCLRR_UART0 (0x01)
1061 #define GPIO_PCLRR_UART1 (0x02)
1062 #define GPIO_PCLRR_UART2 (0x04)
1063 #define GPIO_PCLRR_UART3 (0x08)
1064 #define GPIO_PCLRR_UART4 (0x10)
1065 #define GPIO_PCLRR_UART5 (0x20)
1066 #define GPIO_PCLRR_UART6 (0x40)
1067 #define GPIO_PCLRR_UART7 (0x80)
1069 /* Bit definitions and macros for GPIO_PCLRR_QSPI */
1070 #define GPIO_PCLRR_QSPI0 (0x01)
1071 #define GPIO_PCLRR_QSPI1 (0x02)
1072 #define GPIO_PCLRR_QSPI2 (0x04)
1073 #define GPIO_PCLRR_QSPI3 (0x08)
1074 #define GPIO_PCLRR_QSPI4 (0x10)
1075 #define GPIO_PCLRR_QSPI5 (0x20)
1077 /* Bit definitions and macros for GPIO_PCLRR_TIMER */
1078 #define GPIO_PCLRR_TIMER0 (0x01)
1079 #define GPIO_PCLRR_TIMER1 (0x02)
1080 #define GPIO_PCLRR_TIMER2 (0x04)
1081 #define GPIO_PCLRR_TIMER3 (0x08)
1083 /* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */
1084 #define GPIO_PCLRR_LCDDATAH0 (0x01)
1085 #define GPIO_PCLRR_LCDDATAH1 (0x02)
1087 /* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */
1088 #define GPIO_PCLRR_LCDDATAM0 (0x01)
1089 #define GPIO_PCLRR_LCDDATAM1 (0x02)
1090 #define GPIO_PCLRR_LCDDATAM2 (0x04)
1091 #define GPIO_PCLRR_LCDDATAM3 (0x08)
1092 #define GPIO_PCLRR_LCDDATAM4 (0x10)
1093 #define GPIO_PCLRR_LCDDATAM5 (0x20)
1094 #define GPIO_PCLRR_LCDDATAM6 (0x40)
1095 #define GPIO_PCLRR_LCDDATAM7 (0x80)
1097 /* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */
1098 #define GPIO_PCLRR_LCDDATAL0 (0x01)
1099 #define GPIO_PCLRR_LCDDATAL1 (0x02)
1100 #define GPIO_PCLRR_LCDDATAL2 (0x04)
1101 #define GPIO_PCLRR_LCDDATAL3 (0x08)
1102 #define GPIO_PCLRR_LCDDATAL4 (0x10)
1103 #define GPIO_PCLRR_LCDDATAL5 (0x20)
1104 #define GPIO_PCLRR_LCDDATAL6 (0x40)
1105 #define GPIO_PCLRR_LCDDATAL7 (0x80)
1107 /* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */
1108 #define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01)
1110 /* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */
1111 #define GPIO_PCLRR_LCDCTLL0 (0x01)
1112 #define GPIO_PCLRR_LCDCTLL1 (0x02)
1113 #define GPIO_PCLRR_LCDCTLL2 (0x04)
1114 #define GPIO_PCLRR_LCDCTLL3 (0x08)
1115 #define GPIO_PCLRR_LCDCTLL4 (0x10)
1116 #define GPIO_PCLRR_LCDCTLL5 (0x20)
1117 #define GPIO_PCLRR_LCDCTLL6 (0x40)
1118 #define GPIO_PCLRR_LCDCTLL7 (0x80)
1120 /* Bit definitions and macros for GPIO_PAR_FEC */
1121 #ifdef CONFIG_M5329
1122 #define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
1123 #define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
1124 #define GPIO_PAR_FEC_7W_GPIO (0x00)
1125 #define GPIO_PAR_FEC_7W_URTS1 (0x04)
1126 #define GPIO_PAR_FEC_7W_FEC (0x0C)
1127 #define GPIO_PAR_FEC_MII_GPIO (0x00)
1128 #define GPIO_PAR_FEC_MII_UART (0x01)
1129 #define GPIO_PAR_FEC_MII_FEC (0x03)
1130 #else
1131 #define GPIO_PAR_FEC_7W_FEC (0x08)
1132 #define GPIO_PAR_FEC_MII_FEC (0x02)
1133 #endif
1135 /* Bit definitions and macros for GPIO_PAR_PWM */
1136 #define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
1137 #define GPIO_PAR_PWM3(x) (((x)&0x03)<<2)
1138 #define GPIO_PAR_PWM5 (0x10)
1139 #define GPIO_PAR_PWM7 (0x20)
1141 /* Bit definitions and macros for GPIO_PAR_BUSCTL */
1142 #define GPIO_PAR_BUSCTL_TS(x) (((x)&0x03)<<3)
1143 #define GPIO_PAR_BUSCTL_RWB (0x20)
1144 #define GPIO_PAR_BUSCTL_TA (0x40)
1145 #define GPIO_PAR_BUSCTL_OE (0x80)
1146 #define GPIO_PAR_BUSCTL_OE_GPIO (0x00)
1147 #define GPIO_PAR_BUSCTL_OE_OE (0x80)
1148 #define GPIO_PAR_BUSCTL_TA_GPIO (0x00)
1149 #define GPIO_PAR_BUSCTL_TA_TA (0x40)
1150 #define GPIO_PAR_BUSCTL_RWB_GPIO (0x00)
1151 #define GPIO_PAR_BUSCTL_RWB_RWB (0x20)
1152 #define GPIO_PAR_BUSCTL_TS_GPIO (0x00)
1153 #define GPIO_PAR_BUSCTL_TS_DACK0 (0x10)
1154 #define GPIO_PAR_BUSCTL_TS_TS (0x18)
1156 /* Bit definitions and macros for GPIO_PAR_FECI2C */
1157 #define GPIO_PAR_FECI2C_SDA(x) (((x)&0x03)<<0)
1158 #define GPIO_PAR_FECI2C_SCL(x) (((x)&0x03)<<2)
1159 #define GPIO_PAR_FECI2C_MDIO(x) (((x)&0x03)<<4)
1160 #define GPIO_PAR_FECI2C_MDC(x) (((x)&0x03)<<6)
1161 #define GPIO_PAR_FECI2C_MDC_GPIO (0x00)
1162 #define GPIO_PAR_FECI2C_MDC_UTXD2 (0x40)
1163 #define GPIO_PAR_FECI2C_MDC_SCL (0x80)
1164 #define GPIO_PAR_FECI2C_MDC_EMDC (0xC0)
1165 #define GPIO_PAR_FECI2C_MDIO_GPIO (0x00)
1166 #define GPIO_PAR_FECI2C_MDIO_URXD2 (0x10)
1167 #define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
1168 #define GPIO_PAR_FECI2C_MDIO_EMDIO (0x30)
1169 #define GPIO_PAR_FECI2C_SCL_GPIO (0x00)
1170 #define GPIO_PAR_FECI2C_SCL_UTXD2 (0x04)
1171 #define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
1172 #define GPIO_PAR_FECI2C_SDA_GPIO (0x00)
1173 #define GPIO_PAR_FECI2C_SDA_URXD2 (0x02)
1174 #define GPIO_PAR_FECI2C_SDA_SDA (0x03)
1176 /* Bit definitions and macros for GPIO_PAR_BE */
1177 #define GPIO_PAR_BE0 (0x01)
1178 #define GPIO_PAR_BE1 (0x02)
1179 #define GPIO_PAR_BE2 (0x04)
1180 #define GPIO_PAR_BE3 (0x08)
1182 /* Bit definitions and macros for GPIO_PAR_CS */
1183 #define GPIO_PAR_CS1 (0x02)
1184 #define GPIO_PAR_CS2 (0x04)
1185 #define GPIO_PAR_CS3 (0x08)
1186 #define GPIO_PAR_CS4 (0x10)
1187 #define GPIO_PAR_CS5 (0x20)
1188 #define GPIO_PAR_CS1_GPIO (0x00)
1189 #define GPIO_PAR_CS1_SDCS1 (0x01)
1190 #define GPIO_PAR_CS1_CS1 (0x03)
1192 /* Bit definitions and macros for GPIO_PAR_SSI */
1193 #define GPIO_PAR_SSI_MCLK (0x0080)
1194 #define GPIO_PAR_SSI_TXD(x) (((x)&0x0003)<<8)
1195 #define GPIO_PAR_SSI_RXD(x) (((x)&0x0003)<<10)
1196 #define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<12)
1197 #define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<14)
1199 /* Bit definitions and macros for GPIO_PAR_UART */
1200 #define GPIO_PAR_UART_TXD0 (0x0001)
1201 #define GPIO_PAR_UART_RXD0 (0x0002)
1202 #define GPIO_PAR_UART_RTS0 (0x0004)
1203 #define GPIO_PAR_UART_CTS0 (0x0008)
1204 #define GPIO_PAR_UART_TXD1(x) (((x)&0x0003)<<4)
1205 #define GPIO_PAR_UART_RXD1(x) (((x)&0x0003)<<6)
1206 #define GPIO_PAR_UART_RTS1(x) (((x)&0x0003)<<8)
1207 #define GPIO_PAR_UART_CTS1(x) (((x)&0x0003)<<10)
1208 #define GPIO_PAR_UART_CTS1_GPIO (0x0000)
1209 #define GPIO_PAR_UART_CTS1_SSI_BCLK (0x0800)
1210 #define GPIO_PAR_UART_CTS1_ULPI_D7 (0x0400)
1211 #define GPIO_PAR_UART_CTS1_UCTS1 (0x0C00)
1212 #define GPIO_PAR_UART_RTS1_GPIO (0x0000)
1213 #define GPIO_PAR_UART_RTS1_SSI_FS (0x0200)
1214 #define GPIO_PAR_UART_RTS1_ULPI_D6 (0x0100)
1215 #define GPIO_PAR_UART_RTS1_URTS1 (0x0300)
1216 #define GPIO_PAR_UART_RXD1_GPIO (0x0000)
1217 #define GPIO_PAR_UART_RXD1_SSI_RXD (0x0080)
1218 #define GPIO_PAR_UART_RXD1_ULPI_D5 (0x0040)
1219 #define GPIO_PAR_UART_RXD1_URXD1 (0x00C0)
1220 #define GPIO_PAR_UART_TXD1_GPIO (0x0000)
1221 #define GPIO_PAR_UART_TXD1_SSI_TXD (0x0020)
1222 #define GPIO_PAR_UART_TXD1_ULPI_D4 (0x0010)
1223 #define GPIO_PAR_UART_TXD1_UTXD1 (0x0030)
1225 /* Bit definitions and macros for GPIO_PAR_QSPI */
1226 #define GPIO_PAR_QSPI_SCK(x) (((x)&0x0003)<<4)
1227 #define GPIO_PAR_QSPI_DOUT(x) (((x)&0x0003)<<6)
1228 #define GPIO_PAR_QSPI_DIN(x) (((x)&0x0003)<<8)
1229 #define GPIO_PAR_QSPI_PCS0(x) (((x)&0x0003)<<10)
1230 #define GPIO_PAR_QSPI_PCS1(x) (((x)&0x0003)<<12)
1231 #define GPIO_PAR_QSPI_PCS2(x) (((x)&0x0003)<<14)
1233 /* Bit definitions and macros for GPIO_PAR_TIMER */
1234 #define GPIO_PAR_TIN0(x) (((x)&0x03)<<0)
1235 #define GPIO_PAR_TIN1(x) (((x)&0x03)<<2)
1236 #define GPIO_PAR_TIN2(x) (((x)&0x03)<<4)
1237 #define GPIO_PAR_TIN3(x) (((x)&0x03)<<6)
1238 #define GPIO_PAR_TIN3_GPIO (0x00)
1239 #define GPIO_PAR_TIN3_TOUT3 (0x80)
1240 #define GPIO_PAR_TIN3_URXD2 (0x40)
1241 #define GPIO_PAR_TIN3_TIN3 (0xC0)
1242 #define GPIO_PAR_TIN2_GPIO (0x00)
1243 #define GPIO_PAR_TIN2_TOUT2 (0x20)
1244 #define GPIO_PAR_TIN2_UTXD2 (0x10)
1245 #define GPIO_PAR_TIN2_TIN2 (0x30)
1246 #define GPIO_PAR_TIN1_GPIO (0x00)
1247 #define GPIO_PAR_TIN1_TOUT1 (0x08)
1248 #define GPIO_PAR_TIN1_DACK1 (0x04)
1249 #define GPIO_PAR_TIN1_TIN1 (0x0C)
1250 #define GPIO_PAR_TIN0_GPIO (0x00)
1251 #define GPIO_PAR_TIN0_TOUT0 (0x02)
1252 #define GPIO_PAR_TIN0_DREQ0 (0x01)
1253 #define GPIO_PAR_TIN0_TIN0 (0x03)
1255 /* Bit definitions and macros for GPIO_PAR_LCDDATA */
1256 #define GPIO_PAR_LCDDATA_LD7_0(x) ((x)&0x03)
1257 #define GPIO_PAR_LCDDATA_LD15_8(x) (((x)&0x03)<<2)
1258 #define GPIO_PAR_LCDDATA_LD16(x) (((x)&0x03)<<4)
1259 #define GPIO_PAR_LCDDATA_LD17(x) (((x)&0x03)<<6)
1261 /* Bit definitions and macros for GPIO_PAR_LCDCTL */
1262 #define GPIO_PAR_LCDCTL_CLS (0x0001)
1263 #define GPIO_PAR_LCDCTL_PS (0x0002)
1264 #define GPIO_PAR_LCDCTL_REV (0x0004)
1265 #define GPIO_PAR_LCDCTL_SPL_SPR (0x0008)
1266 #define GPIO_PAR_LCDCTL_CONTRAST (0x0010)
1267 #define GPIO_PAR_LCDCTL_LSCLK (0x0020)
1268 #define GPIO_PAR_LCDCTL_LP_HSYNC (0x0040)
1269 #define GPIO_PAR_LCDCTL_FLM_VSYNC (0x0080)
1270 #define GPIO_PAR_LCDCTL_ACD_OE (0x0100)
1272 /* Bit definitions and macros for GPIO_PAR_IRQ */
1273 #define GPIO_PAR_IRQ1(x) (((x)&0x0003)<<4)
1274 #define GPIO_PAR_IRQ2(x) (((x)&0x0003)<<6)
1275 #define GPIO_PAR_IRQ4(x) (((x)&0x0003)<<8)
1276 #define GPIO_PAR_IRQ5(x) (((x)&0x0003)<<10)
1277 #define GPIO_PAR_IRQ6(x) (((x)&0x0003)<<12)
1279 /* Bit definitions and macros for GPIO_MSCR_FLEXBUS */
1280 #define GPIO_MSCR_FLEXBUS_ADDRCTL(x) ((x)&0x03)
1281 #define GPIO_MSCR_FLEXBUS_DLOWER(x) (((x)&0x03)<<2)
1282 #define GPIO_MSCR_FLEXBUS_DUPPER(x) (((x)&0x03)<<4)
1284 /* Bit definitions and macros for GPIO_MSCR_SDRAM */
1285 #define GPIO_MSCR_SDRAM_SDRAM(x) ((x)&0x03)
1286 #define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
1287 #define GPIO_MSCR_SDRAM_SDCLKB(x) (((x)&0x03)<<4)
1289 /* Bit definitions and macros for GPIO_DSCR_I2C */
1290 #define GPIO_DSCR_I2C_DSE(x) ((x)&0x03)
1292 /* Bit definitions and macros for GPIO_DSCR_PWM */
1293 #define GPIO_DSCR_PWM_DSE(x) ((x)&0x03)
1295 /* Bit definitions and macros for GPIO_DSCR_FEC */
1296 #define GPIO_DSCR_FEC_DSE(x) ((x)&0x03)
1298 /* Bit definitions and macros for GPIO_DSCR_UART */
1299 #define GPIO_DSCR_UART0_DSE(x) ((x)&0x03)
1300 #define GPIO_DSCR_UART1_DSE(x) (((x)&0x03)<<2)
1302 /* Bit definitions and macros for GPIO_DSCR_QSPI */
1303 #define GPIO_DSCR_QSPI_DSE(x) ((x)&0x03)
1305 /* Bit definitions and macros for GPIO_DSCR_TIMER */
1306 #define GPIO_DSCR_TIMER_DSE(x) ((x)&0x03)
1308 /* Bit definitions and macros for GPIO_DSCR_SSI */
1309 #define GPIO_DSCR_SSI_DSE(x) ((x)&0x03)
1311 /* Bit definitions and macros for GPIO_DSCR_LCD */
1312 #define GPIO_DSCR_LCD_DSE(x) ((x)&0x03)
1314 /* Bit definitions and macros for GPIO_DSCR_DEBUG */
1315 #define GPIO_DSCR_DEBUG_DSE(x) ((x)&0x03)
1317 /* Bit definitions and macros for GPIO_DSCR_CLKRST */
1318 #define GPIO_DSCR_CLKRST_DSE(x) ((x)&0x03)
1320 /* Bit definitions and macros for GPIO_DSCR_IRQ */
1321 #define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03)
1323 /*********************************************************************
1324 * SDRAM Controller (SDRAMC)
1325 *********************************************************************/
1326 /* Bit definitions and macros for SDRAMC_SDMR */
1327 #define SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
1328 #define SDRAMC_SDMR_BNKAD_LMR (0x00000000)
1329 #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
1330 #define SDRAMC_SDMR_CMD (0x00010000)
1332 /* Bit definitions and macros for SDRAMC_SDCR */
1333 #define SDRAMC_SDCR_MODE_EN (0x80000000)
1334 #define SDRAMC_SDCR_CKE (0x40000000)
1335 #define SDRAMC_SDCR_DDR (0x20000000)
1336 #define SDRAMC_SDCR_REF (0x10000000)
1337 #define SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
1338 #define SDRAMC_SDCR_OE_RULE (0x00400000)
1339 #define SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
1340 #define SDRAMC_SDCR_PS_32 (0x00000000)
1341 #define SDRAMC_SDCR_PS_16 (0x00002000)
1342 #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
1343 #define SDRAMC_SDCR_IREF (0x00000004)
1344 #define SDRAMC_SDCR_IPALL (0x00000002)
1346 /* Bit definitions and macros for SDRAMC_SDCFG1 */
1347 #define SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
1348 #define SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
1349 #define SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
1350 #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
1351 #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
1352 #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
1353 #define SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
1355 /* Bit definitions and macros for SDRAMC_SDCFG2 */
1356 #define SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
1357 #define SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
1358 #define SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
1359 #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
1361 /* Bit definitions and macros for SDRAMC_SDDS */
1362 #define SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8)
1363 #define SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6)
1364 #define SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4)
1365 #define SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2)
1366 #define SDRAMC_SDDS_SB_D(x) ((x)&0x00000003)
1368 /* Bit definitions and macros for SDRAMC_SDCS */
1369 #define SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20)
1370 #define SDRAMC_SDCS_CSSZ(x) ((x)&0x0000001F)
1371 #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
1372 #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
1373 #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
1374 #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
1375 #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
1376 #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
1377 #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
1378 #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
1379 #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
1380 #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
1381 #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
1382 #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
1383 #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
1384 #define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
1386 /*********************************************************************
1387 * Phase Locked Loop (PLL)
1388 *********************************************************************/
1389 /* Bit definitions and macros for PLL_PODR */
1390 #define PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4)
1391 #define PLL_PODR_BUSDIV(x) ((x)&0x0F)
1393 /* Bit definitions and macros for PLL_PLLCR */
1394 #define PLL_PLLCR_DITHEN (0x80)
1395 #define PLL_PLLCR_DITHDEV(x) ((x)&0x07)