include/asm-m68k/immap.h

   1 /*
   2  * ColdFire Internal Memory Map and Defines
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __IMMAP_H
  27 #define __IMMAP_H
  28
  29 #ifdef CONFIG_M52277
  30 #include <asm/immap_5227x.h>
  31 #include <asm/m5227x.h>
  32
  33 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
  34
  35 #define CFG_MCFRTC_BASE         (MMAP_RTC)
  36
  37 #ifdef CONFIG_LCD
  38 #define CFG_LCD_BASE            (MMAP_LCD)
  39 #endif
  40
  41 /* Timer */
  42 #ifdef CONFIG_MCFTMR
  43 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
  44 #define CFG_TMR_BASE            (MMAP_DTMR1)
  45 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
  46 #define CFG_TMRINTR_NO          (INT0_HI_DTMR1)
  47 #define CFG_TMRINTR_MASK        (INTC_IPRH_INT33)
  48 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
  49 #define CFG_TMRINTR_PRI         (6)
  50 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
  51 #endif
  52
  53 #ifdef CONFIG_MCFPIT
  54 #define CFG_UDELAY_BASE         (MMAP_PIT0)
  55 #define CFG_PIT_BASE            (MMAP_PIT1)
  56 #define CFG_PIT_PRESCALE        (6)
  57 #endif
  58
  59 #define CFG_INTR_BASE           (MMAP_INTC0)
  60 #define CFG_NUM_IRQS            (128)
  61 #endif                          /* CONFIG_M52277 */
  62
  63 #ifdef CONFIG_M5235
  64 #include <asm/immap_5235.h>
  65 #include <asm/m5235.h>
  66
  67 #define CFG_FEC0_IOBASE         (MMAP_FEC)
  68 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x40))
  69
  70 /* Timer */
  71 #ifdef CONFIG_MCFTMR
  72 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
  73 #define CFG_TMR_BASE            (MMAP_DTMR3)
  74 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
  75 #define CFG_TMRINTR_NO          (INT0_LO_DTMR3)
  76 #define CFG_TMRINTR_MASK        (INTC_IPRL_INT22)
  77 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
  78 #define CFG_TMRINTR_PRI         (0x1E)          /* Level must include inorder to work */
  79 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
  80 #endif
  81
  82 #ifdef CONFIG_MCFPIT
  83 #define CFG_UDELAY_BASE         (MMAP_PIT0)
  84 #define CFG_PIT_BASE            (MMAP_PIT1)
  85 #define CFG_PIT_PRESCALE        (6)
  86 #endif
  87
  88 #define CFG_INTR_BASE           (MMAP_INTC0)
  89 #define CFG_NUM_IRQS            (128)
  90 #endif                          /* CONFIG_M5235 */
  91
  92 #ifdef CONFIG_M5249
  93 #include <asm/immap_5249.h>
  94 #include <asm/m5249.h>
  95
  96 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x40))
  97
  98 #define CFG_INTR_BASE           (MMAP_INTC)
  99 #define CFG_NUM_IRQS            (64)
 100
 101 /* Timer */
 102 #ifdef CONFIG_MCFTMR
 103 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
 104 #define CFG_TMR_BASE            (MMAP_DTMR1)
 105 #define CFG_TMRPND_REG          (mbar_readLong(MCFSIM_IPR))
 106 #define CFG_TMRINTR_NO          (31)
 107 #define CFG_TMRINTR_MASK        (0x00000400)
 108 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 109 #define CFG_TMRINTR_PRI         (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
 110 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 2000000) - 1) << 8)
 111 #endif
 112 #endif                          /* CONFIG_M5249 */
 113
 114 #ifdef CONFIG_M5253
 115 #include <asm/immap_5253.h>
 116 #include <asm/m5249.h>
 117 #include <asm/m5253.h>
 118
 119 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x40))
 120
 121 #define CFG_INTR_BASE           (MMAP_INTC)
 122 #define CFG_NUM_IRQS            (64)
 123
 124 /* Timer */
 125 #ifdef CONFIG_MCFTMR
 126 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
 127 #define CFG_TMR_BASE            (MMAP_DTMR1)
 128 #define CFG_TMRPND_REG          (mbar_readLong(MCFSIM_IPR))
 129 #define CFG_TMRINTR_NO          (27)
 130 #define CFG_TMRINTR_MASK        (0x00000400)
 131 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 132 #define CFG_TMRINTR_PRI         (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
 133 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 2000000) - 1) << 8)
 134 #endif
 135 #endif                          /* CONFIG_M5253 */
 136
 137 #ifdef CONFIG_M5271
 138 #include <asm/immap_5271.h>
 139 #include <asm/m5271.h>
 140
 141 #define CFG_FEC0_IOBASE         (MMAP_FEC)
 142 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x40))
 143
 144 /* Timer */
 145 #ifdef CONFIG_MCFTMR
 146 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
 147 #define CFG_TMR_BASE            (MMAP_DTMR3)
 148 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
 149 #define CFG_TMRINTR_NO          (INT0_LO_DTMR3)
 150 #define CFG_TMRINTR_MASK        (INTC_IPRL_INT22)
 151 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 152 #define CFG_TMRINTR_PRI         (0)             /* Level must include inorder to work */
 153 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
 154 #endif
 155
 156 #define CFG_INTR_BASE           (MMAP_INTC0)
 157 #define CFG_NUM_IRQS            (128)
 158 #endif                          /* CONFIG_M5271 */
 159
 160 #ifdef CONFIG_M5272
 161 #include <asm/immap_5272.h>
 162 #include <asm/m5272.h>
 163
 164 #define CFG_FEC0_IOBASE         (MMAP_FEC)
 165 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x40))
 166
 167 #define CFG_INTR_BASE           (MMAP_INTC)
 168 #define CFG_NUM_IRQS            (64)
 169
 170 /* Timer */
 171 #ifdef CONFIG_MCFTMR
 172 #define CFG_UDELAY_BASE         (MMAP_TMR0)
 173 #define CFG_TMR_BASE            (MMAP_TMR3)
 174 #define CFG_TMRPND_REG          (((volatile intctrl_t *)(CFG_INTR_BASE))->int_isr)
 175 #define CFG_TMRINTR_NO          (INT_TMR3)
 176 #define CFG_TMRINTR_MASK        (INT_ISR_INT24)
 177 #define CFG_TMRINTR_PEND        (0)
 178 #define CFG_TMRINTR_PRI         (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
 179 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
 180 #endif
 181 #endif                          /* CONFIG_M5272 */
 182
 183 #ifdef CONFIG_M5275
 184 #include <asm/immap_5275.h>
 185 #include <asm/m5275.h>
 186
 187 #define CFG_FEC0_IOBASE         (MMAP_FEC0)
 188 #define CFG_FEC1_IOBASE         (MMAP_FEC1)
 189 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x40))
 190
 191 #define CFG_INTR_BASE           (MMAP_INTC0)
 192 #define CFG_NUM_IRQS            (192)
 193
 194 /* Timer */
 195 #ifdef CONFIG_MCFTMR
 196 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
 197 #define CFG_TMR_BASE            (MMAP_DTMR3)
 198 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
 199 #define CFG_TMRINTR_NO          (INT0_LO_DTMR3)
 200 #define CFG_TMRINTR_MASK        (INTC_IPRL_INT22)
 201 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 202 #define CFG_TMRINTR_PRI         (0x1E)
 203 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
 204 #endif
 205 #endif                          /* CONFIG_M5275 */
 206
 207 #ifdef CONFIG_M5282
 208 #include <asm/immap_5282.h>
 209 #include <asm/m5282.h>
 210
 211 #define CFG_FEC0_IOBASE         (MMAP_FEC)
 212 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x40))
 213
 214 #define CFG_INTR_BASE           (MMAP_INTC0)
 215 #define CFG_NUM_IRQS            (128)
 216
 217 /* Timer */
 218 #ifdef CONFIG_MCFTMR
 219 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
 220 #define CFG_TMR_BASE            (MMAP_DTMR3)
 221 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprl0)
 222 #define CFG_TMRINTR_NO          (INT0_LO_DTMR3)
 223 #define CFG_TMRINTR_MASK        (1 << INT0_LO_DTMR3)
 224 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 225 #define CFG_TMRINTR_PRI         (0x1E)          /* Level must include inorder to work */
 226 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
 227 #endif
 228 #endif                          /* CONFIG_M5282 */
 229
 230 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 231 #include <asm/immap_5329.h>
 232 #include <asm/m5329.h>
 233
 234 #define CFG_FEC0_IOBASE         (MMAP_FEC)
 235 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
 236 #define CFG_MCFRTC_BASE         (MMAP_RTC)
 237
 238 /* Timer */
 239 #ifdef CONFIG_MCFTMR
 240 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
 241 #define CFG_TMR_BASE            (MMAP_DTMR1)
 242 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
 243 #define CFG_TMRINTR_NO          (INT0_HI_DTMR1)
 244 #define CFG_TMRINTR_MASK        (INTC_IPRH_INT33)
 245 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 246 #define CFG_TMRINTR_PRI         (6)
 247 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
 248 #endif
 249
 250 #ifdef CONFIG_MCFPIT
 251 #define CFG_UDELAY_BASE         (MMAP_PIT0)
 252 #define CFG_PIT_BASE            (MMAP_PIT1)
 253 #define CFG_PIT_PRESCALE        (6)
 254 #endif
 255
 256 #define CFG_INTR_BASE           (MMAP_INTC0)
 257 #define CFG_NUM_IRQS            (128)
 258 #endif                          /* CONFIG_M5329 && CONFIG_M5373 */
 259
 260 #ifdef CONFIG_M54455
 261 #include <asm/immap_5445x.h>
 262 #include <asm/m5445x.h>
 263
 264 #define CFG_FEC0_IOBASE         (MMAP_FEC0)
 265 #define CFG_FEC1_IOBASE         (MMAP_FEC1)
 266
 267 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
 268
 269 #define CFG_MCFRTC_BASE         (MMAP_RTC)
 270
 271 /* Timer */
 272 #ifdef CONFIG_MCFTMR
 273 #define CFG_UDELAY_BASE         (MMAP_DTMR0)
 274 #define CFG_TMR_BASE            (MMAP_DTMR1)
 275 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
 276 #define CFG_TMRINTR_NO          (INT0_HI_DTMR1)
 277 #define CFG_TMRINTR_MASK        (INTC_IPRH_INT33)
 278 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 279 #define CFG_TMRINTR_PRI         (6)
 280 #define CFG_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
 281 #endif
 282
 283 #ifdef CONFIG_MCFPIT
 284 #define CFG_UDELAY_BASE         (MMAP_PIT0)
 285 #define CFG_PIT_BASE            (MMAP_PIT1)
 286 #define CFG_PIT_PRESCALE        (6)
 287 #endif
 288
 289 #define CFG_INTR_BASE           (MMAP_INTC0)
 290 #define CFG_NUM_IRQS            (128)
 291
 292 #ifdef CONFIG_PCI
 293 #define CFG_PCI_BAR0            (CFG_MBAR)
 294 #define CFG_PCI_BAR5            (CFG_SDRAM_BASE)
 295 #define CFG_PCI_TBATR0          (CFG_MBAR)
 296 #define CFG_PCI_TBATR5          (CFG_SDRAM_BASE)
 297 #endif
 298 #endif                          /* CONFIG_M54455 */
 299
 300 #ifdef CONFIG_M547x
 301 #include <asm/immap_547x_8x.h>
 302 #include <asm/m547x_8x.h>
 303
 304 #ifdef CONFIG_FSLDMAFEC
 305 #define CFG_FEC0_IOBASE         (MMAP_FEC0)
 306 #define CFG_FEC1_IOBASE         (MMAP_FEC1)
 307
 308 #define FEC0_RX_TASK            0
 309 #define FEC0_TX_TASK            1
 310 #define FEC0_RX_PRIORITY        6
 311 #define FEC0_TX_PRIORITY        7
 312 #define FEC0_RX_INIT            16
 313 #define FEC0_TX_INIT            17
 314 #define FEC1_RX_TASK            2
 315 #define FEC1_TX_TASK            3
 316 #define FEC1_RX_PRIORITY        6
 317 #define FEC1_TX_PRIORITY        7
 318 #define FEC1_RX_INIT            30
 319 #define FEC1_TX_INIT            31
 320 #endif
 321
 322 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x100))
 323
 324 #ifdef CONFIG_SLTTMR
 325 #define CFG_UDELAY_BASE         (MMAP_SLT1)
 326 #define CFG_TMR_BASE            (MMAP_SLT0)
 327 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
 328 #define CFG_TMRINTR_NO          (INT0_HI_SLT0)
 329 #define CFG_TMRINTR_MASK        (INTC_IPRH_INT54)
 330 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 331 #define CFG_TMRINTR_PRI         (0x1E)
 332 #define CFG_TIMER_PRESCALER     (gd->bus_clk / 1000000)
 333 #endif
 334
 335 #define CFG_INTR_BASE           (MMAP_INTC0)
 336 #define CFG_NUM_IRQS            (128)
 337
 338 #ifdef CONFIG_PCI
 339 #define CFG_PCI_BAR0            (0x40000000)
 340 #define CFG_PCI_BAR1            (CFG_SDRAM_BASE)
 341 #define CFG_PCI_TBATR0          (CFG_MBAR)
 342 #define CFG_PCI_TBATR1          (CFG_SDRAM_BASE)
 343 #endif
 344 #endif                          /* CONFIG_M547x */
 345
 346 #ifdef CONFIG_M548x
 347 #include <asm/immap_547x_8x.h>
 348 #include <asm/m547x_8x.h>
 349
 350 #ifdef CONFIG_FSLDMAFEC
 351 #define CFG_FEC0_IOBASE         (MMAP_FEC0)
 352 #define CFG_FEC1_IOBASE         (MMAP_FEC1)
 353
 354 #define FEC0_RX_TASK            0
 355 #define FEC0_TX_TASK            1
 356 #define FEC0_RX_PRIORITY        6
 357 #define FEC0_TX_PRIORITY        7
 358 #define FEC0_RX_INIT            16
 359 #define FEC0_TX_INIT            17
 360 #define FEC1_RX_TASK            2
 361 #define FEC1_TX_TASK            3
 362 #define FEC1_RX_PRIORITY        6
 363 #define FEC1_TX_PRIORITY        7
 364 #define FEC1_RX_INIT            30
 365 #define FEC1_TX_INIT            31
 366 #endif
 367
 368 #define CFG_UART_BASE           (MMAP_UART0 + (CFG_UART_PORT * 0x100))
 369
 370 /* Timer */
 371 #ifdef CONFIG_SLTTMR
 372 #define CFG_UDELAY_BASE         (MMAP_SLT1)
 373 #define CFG_TMR_BASE            (MMAP_SLT0)
 374 #define CFG_TMRPND_REG          (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
 375 #define CFG_TMRINTR_NO          (INT0_HI_SLT0)
 376 #define CFG_TMRINTR_MASK        (INTC_IPRH_INT54)
 377 #define CFG_TMRINTR_PEND        (CFG_TMRINTR_MASK)
 378 #define CFG_TMRINTR_PRI         (0x1E)
 379 #define CFG_TIMER_PRESCALER     (gd->bus_clk / 1000000)
 380 #endif
 381
 382 #define CFG_INTR_BASE           (MMAP_INTC0)
 383 #define CFG_NUM_IRQS            (128)
 384
 385 #ifdef CONFIG_PCI
 386 #define CFG_PCI_BAR0            (CFG_MBAR)
 387 #define CFG_PCI_BAR1            (CFG_SDRAM_BASE)
 388 #define CFG_PCI_TBATR0          (CFG_MBAR)
 389 #define CFG_PCI_TBATR1          (CFG_SDRAM_BASE)
 390 #endif
 391 #endif                          /* CONFIG_M548x */
 392
 393 #endif                          /* __IMMAP_H */