MINI2440: Auto probe for SDRAM size
[u-boot-openmoko/mini2440.git] / board / sbc8349 / sbc8349.c
blobe89b6e824866e9217f0836ecd53a977f2443561b
1 /*
2 * sbc8349.c -- WindRiver SBC8349 board support.
3 * Copyright (c) 2006-2007 Wind River Systems, Inc.
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
8 * See file CREDITS for list of people who contributed to this
9 * project.
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
28 #include <common.h>
29 #include <ioports.h>
30 #include <mpc83xx.h>
31 #include <asm/mpc8349_pci.h>
32 #include <i2c.h>
33 #include <spd_sdram.h>
34 #include <miiphy.h>
35 #if defined(CONFIG_OF_LIBFDT)
36 #include <libfdt.h>
37 #endif
39 int fixed_sdram(void);
40 void sdram_init(void);
42 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
43 void ddr_enable_ecc(unsigned int dram_size);
44 #endif
46 #ifdef CONFIG_BOARD_EARLY_INIT_F
47 int board_early_init_f (void)
49 return 0;
51 #endif
53 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
55 long int initdram (int board_type)
57 volatile immap_t *im = (immap_t *)CFG_IMMR;
58 u32 msize = 0;
60 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
61 return -1;
63 /* DDR SDRAM - Main SODIMM */
64 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
65 #if defined(CONFIG_SPD_EEPROM)
66 msize = spd_sdram();
67 #else
68 msize = fixed_sdram();
69 #endif
71 * Initialize SDRAM if it is on local bus.
73 sdram_init();
75 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
77 * Initialize and enable DDR ECC.
79 ddr_enable_ecc(msize * 1024 * 1024);
80 #endif
81 /* return total bus SDRAM size(bytes) -- DDR */
82 return (msize * 1024 * 1024);
85 #if !defined(CONFIG_SPD_EEPROM)
86 /*************************************************************************
87 * fixed sdram init -- doesn't use serial presence detect.
88 ************************************************************************/
89 int fixed_sdram(void)
91 volatile immap_t *im = (immap_t *)CFG_IMMR;
92 u32 msize = 0;
93 u32 ddr_size;
94 u32 ddr_size_log2;
96 msize = CFG_DDR_SIZE;
97 for (ddr_size = msize << 20, ddr_size_log2 = 0;
98 (ddr_size > 1);
99 ddr_size = ddr_size>>1, ddr_size_log2++) {
100 if (ddr_size & 1) {
101 return -1;
104 im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
105 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
107 #if (CFG_DDR_SIZE != 256)
108 #warning Currently any ddr size other than 256 is not supported
109 #endif
110 im->ddr.csbnds[2].csbnds = 0x0000000f;
111 im->ddr.cs_config[2] = CFG_DDR_CONFIG;
113 /* currently we use only one CS, so disable the other banks */
114 im->ddr.cs_config[0] = 0;
115 im->ddr.cs_config[1] = 0;
116 im->ddr.cs_config[3] = 0;
118 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
119 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
121 im->ddr.sdram_cfg =
122 SDRAM_CFG_SREN
123 #if defined(CONFIG_DDR_2T_TIMING)
124 | SDRAM_CFG_2T_EN
125 #endif
126 | SDRAM_CFG_SDRAM_TYPE_DDR1;
127 #if defined (CONFIG_DDR_32BIT)
128 /* for 32-bit mode burst length is 8 */
129 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
130 #endif
131 im->ddr.sdram_mode = CFG_DDR_MODE;
133 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
134 udelay(200);
136 /* enable DDR controller */
137 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
138 return msize;
140 #endif/*!CFG_SPD_EEPROM*/
143 int checkboard (void)
145 puts("Board: Wind River SBC834x\n");
146 return 0;
150 * if board is fitted with SDRAM
152 #if defined(CFG_BR2_PRELIM) \
153 && defined(CFG_OR2_PRELIM) \
154 && defined(CFG_LBLAWBAR2_PRELIM) \
155 && defined(CFG_LBLAWAR2_PRELIM)
157 * Initialize SDRAM memory on the Local Bus.
160 void sdram_init(void)
162 volatile immap_t *immap = (immap_t *)CFG_IMMR;
163 volatile lbus83xx_t *lbc= &immap->lbus;
164 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
166 puts("\n SDRAM on Local Bus: ");
167 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
170 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
173 /* setup mtrpt, lsrt and lbcr for LB bus */
174 lbc->lbcr = CFG_LBC_LBCR;
175 lbc->mrtpr = CFG_LBC_MRTPR;
176 lbc->lsrt = CFG_LBC_LSRT;
177 asm("sync");
180 * Configure the SDRAM controller Machine Mode Register.
182 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
184 lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
185 asm("sync");
186 *sdram_addr = 0xff;
187 udelay(100);
189 lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
190 asm("sync");
191 /*1 times*/
192 *sdram_addr = 0xff;
193 udelay(100);
194 /*2 times*/
195 *sdram_addr = 0xff;
196 udelay(100);
197 /*3 times*/
198 *sdram_addr = 0xff;
199 udelay(100);
200 /*4 times*/
201 *sdram_addr = 0xff;
202 udelay(100);
203 /*5 times*/
204 *sdram_addr = 0xff;
205 udelay(100);
206 /*6 times*/
207 *sdram_addr = 0xff;
208 udelay(100);
209 /*7 times*/
210 *sdram_addr = 0xff;
211 udelay(100);
212 /*8 times*/
213 *sdram_addr = 0xff;
214 udelay(100);
216 /* 0x58636733; mode register write operation */
217 lbc->lsdmr = CFG_LBC_LSDMR_4;
218 asm("sync");
219 *sdram_addr = 0xff;
220 udelay(100);
222 lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
223 asm("sync");
224 *sdram_addr = 0xff;
225 udelay(100);
227 #else
228 void sdram_init(void)
230 puts(" SDRAM on Local Bus: Disabled in config\n");
232 #endif
234 #if defined(CONFIG_OF_BOARD_SETUP)
235 void ft_board_setup(void *blob, bd_t *bd)
237 ft_cpu_setup(blob, bd);
238 #ifdef CONFIG_PCI
239 ft_pci_setup(blob, bd);
240 #endif
242 #endif